Timing Circuit Including Jitter Compensation

This invention relates to timing circuits for use in digital transmission systems and, more particularly, to timing circuits including a phase locked loop.

It is well-known that local timing signals in a digital receiver must be synchronized to an incoming digital signal in order to recover the data. Heretofore, such timing signals were recovered from the incoming digital signal by employing a phase locked loop. The phase locked loop was responsive to the incoming digital signal for generating a phase error signal which, in turn, controls a voltage controlled oscillator to generate a local timing signal.

In frames of certain incoming digital signals, there are additional overhead bit positions and so-called stuffing bit positions which when eliminated leave gaps in the data stream. Because of such gaps, the recovered timing signal generated by a typical phase locked loop arrangement is not smooth causing jitter. As is well-known, jitter is extremely undesirable in timing signals. Additionally, it is desirable that the generated timing signal follow variations in the incoming digital signal caused by the stuffing bits.

The problem of jitter in a recovered timing signal caused by overhead bit removal from an incoming digital signal is overcome, in accordance with an aspect of the invention, by employing a clock signal that is synchronous with the incoming data signal as an input to a phase locked loop. The clock signal is divided by a first predetermined divisor to obtain a reference clock signal which is supplied as a first input to a phase detector in the phase locked loop. An output timing signal generated by the phase locked loop is divided by a second predetermined divisor to obtain a phase clock signal which is supplied as a second input to the phase detector. The phase detector generates a phase error signal which, in turn, controls a voltage controllable oscillator that generates the output timing signal. The first predetermined divisor is selected, in accordance with an aspect of the invention, to be in a prescribed relationship to the total number of bits in a frame of the incoming digital signal. The second predetermined divisor is selected, in accordance with an aspect of the invention, to be in a prescribed relationship with the number of data bits in a frame of hte incoming digital signal.

Variations in the output timing signal which follow variations in the actual data rate of the incoming digtal signal caused by stuffing bits are generated, in accordance with another aspect of the invention, by controllably compensating the phase clock signal generated in the phase locked loop. The phase clock signal compensation is dependent on the number of stuffing bit positions that include data or non-data bits.

The invention will be more fully understood from the following detailed description of an illustrative embodiment taken in conjunction with the appended figures in which, FIG. 1 shows in simplified block diagram form a timing circuit employing a phase locked loop incorporating an embodiment of the invention; and FIG. 2 illustrates a channel frame format of a signal for which the invention of FIG. 1 may be employed.

As indicated above, certain incoming digital signals may have large gaps in the data stream because of overhead bits and also because of stuffing bits. Several such signal formats are disclosed in co-pending U.S. patent application Ser. No. 769,427 filed Aug. 26, 1985. Specifically, attention is direct to FIGS. 4-7 of the application Ser. No. 769,427. One example of such a channel frame format is shown in FIG. 2. This particular channel frame format may be used for the DSI digital signal.

FIG. 1 depicts in simplified block diagram form a timing circuit including an embodiment of the invention. Accordingly, shown is local clock 10 which is responsive to a known reference signal F.sub.REF for generating timing signal F.sub.IN. Reference signal F.sub.REF is, for example, the so-called Basic Synchronization Reference Frequency (BSRF) signal which is used to derive timing signals for synchronous digital transmission systems.

In certain applications, signal F.sub.IN may not be at the same rate as the incoming digital signal and divider 11 is used to obtain a desired reference clock (REFCLK) rate. REFCLK is supplied as a first input to phase detector 12. First predetermined divisor M of divider 11 is selected, in accordance with an aspect of the invention, to be in a prescribed relationship with the total number of bits in a frame of the incoming digital signal. The prescribed relationship being that divisor M is a predetermined fractional protion of the total number of bit positions in a frame of the incoming digital signal. In one example, not to be construed as limiting the scope of the invention, the total number of bits in a frame of the incoming digital signal is 832, as shown in FIG. 2, divisor M is selected to be 208 and F.sub.IN is 1.664 MHz to obtain REFCLK=8 KHz. Thus, in this example, it is seen that divisor M is one fourth the total number of bits in the frame of the incoming digital signal. Similarly, for the DS1C and DS2 digital signals the total number of bits in a frame is 832 and divisor M=208. A phase clock (PHCLK) signal derived from the phase locked loop output timing signal F.sub.OUT is supplied as a second input to phase detector 12. Phase detector 12 generates an error signal (ES) in known fashion which is proportional to the algebraic difference between REFCLK and PHCLK. Error signal ES is supplied from phase detector 12 to low pass filter 13 which yields a smooth version thereof. In turn, the output from low pass filter 13 is supplied to control voltage controlled oscillator 14 in well-known fashion to generate output timing signal F.sub.OUT. Output timing signal F.sub.OUT is the desired local timing signal and is also feedback to controllable divider 15 which generates PHCLK. Second predetermined divisor N of controllable divider 15 is selected, in accordance with an aspect of the invention, to be in a prescribed relationship to the number of data bits in a frame of the incoming digital signal. The prescribed relationship being that divisor N is a predetermined fractional portion of the number of data bits in a frame of the incoming digital signal. In one example, not to be construed as limiting the scope of the invention, the number of data bit positions in a frame of the incoming digital signal is 772 corresponding to the DS1 digital rate as shown in FIG. 2 and divisor N is selected to be 193, to obtain REFCLK=8 KHz. Thus, in this example, it is seen that divisor N is one fourth the number of data bits in the frame of the incoming digital signal. Similarly, for the DS1C digital signal the number of data bits in a frame is 788 and for the DS2 digital signal the number of data bits in a frame is 789, and for both divisor N=197. The selection of divisors M and N of dividers 11 and 15, respectively, in the manner described eliminates jitter in the output timing signal F.sub.OUT caused by large gaps resulting from overhead bit removal from the incoming digital signal.

It is desirable to have variations in the bit rate of output timing signal F.sub.OUT that follow variations in the actual data rate of the incoming digital signal which are caused by the content of the stuffing bit positions. To this end, controllable divider 15 is controlled by signals S1 and S2 from stuff logic 16 to compensate, in accordance with an aspect of the invention, PHCLK depending on the content of the stuffing bit positions in the incoming digital signal. In this example, not to be construed as limiting the scope of the invention, two stuffing bit positions S1 and S2 are assumed as shown in FIG. 2. The content of each stuffing bit position as data or non-data is transmitted in each frame of the received signal by so-called stuffing bit indicator bits C.sub.1 and C.sub.2 for stuffing bit positions S1 and S2, respectively. In this example, three C.sub.1 bits and three C.sub.2 bits are in each frame of the incoming signal as shown in FIG. 2. Stuffing indicator bits C1 and C2 are obtained from the incoming signal by employing demultiplexer (DEMUX) 17, in well known fashion. A majority decision is made in stuff logic 16 as to whether the corresponding stuffing bit position includes a data bit or a non-data bit. Thus, a non-data bit is indicated by two or all logical 1's in the corresponding C-bit (C.sub.1 or C.sub.2) positions and a data bit is indicated by two or all logical 0's. For normal operation, S.sub.1 is a non-data bit represented by a logical 1 and S2 is a data bit represented by a logical 0. Consequently, in response to S1=1 and S2=0, divider 16 divides F.sub.OUT by the second predetermined divisor having the nominal value N. In this example, the normal bit rate of F.sub.OUT is 1.544 MHz (corresponding to the DS1 digital rate) and N=193 to generate PHCLK=8 KHz. When both stuffing bit positions include non-data bits as indicated by S1=1 and S2=1, divider 16 divides F.sub.OUT by a third predetermined divisor having a value N-Y, where in this example Y=1. This causes PHCLK to increase slightly which, in turn, causes error signal ES generated by phase detector 12 to decrease. The decrease in error signal ES causes a slight decrease in the bit rate of F.sub.OUT. When both stuffing bit positions include data bits as indicated by S1=0 and S2=0, divider 16 divides F.sub.OUT by a fourth predetermined divisor having a value N+Y, where in this example Y=1. This causes PHCLK to decrease slightly which, in turn, causes error signal ES generated by phase detector 12 to increase. The increase in error signal ES causes a slight increase in bit rate of F.sub.OUT. Thus, the bit rate of PHCLK is adjusted to compensate for a decrease in data when both stuffing bit positions are non-data bits and to compensate for an increase in data when both stuffing bit positions are data bits. Consequently, variations are caused in the bit rate of output timing signal F.sub.OUT which correspond to the variations in the actual data rate of the incoming digital signal. It is noted that the compensation to PHCLK is on a frame-by-frame basis of the incoming signal.

The invention has been described in the context of eliminating jitter caused by large gaps in an incoming digital signal resulting from overheat bit removal. It will be apparent to those skilled in the art that the invention is equally applicable for use with any incoming digital signal having large gaps whether or not they are caused by overhead bit removal. For example, there may just be excess data bit positions that are not being used. Additionally, the embodiment of the invention has been described in terms of the DS1 digital rate. It will also be apparent to those skilled in the art that the invention is applicable for obtaining a timing signal to correspond to an incoming digital signal having any one of a number of digital rates.