US 4,847,550 AGrant
Semiconductor Circuit
Issue Date:1989-07-11
•4 Claims
•5 Drawing Sheets
Abstract
A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.
Metadata
Assignee
- Hitachi, Ltd.
Inventors
- Satoshi Tanaka
- Hirotoshi Tanaka
- Taizo Kinoshita
- Nobuo Kotera
- Minoru Nagata
- Kiichi Yamashita
- Tomoyuki Watanabe
Application Information
Application Number:US 1438026
Filing Date:1988-01-14
Priority Date:1987-01-16
Art Unit:212
Classifications
IPC:
G05F 320
Field of Search:
323312;313;314;315;316;907
Patent Drawings (5 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to a semiconductor circuit, and in particular to a constant voltage circuit and a constant current circuit, which are suitable for integrated circuits using field effect transistors.
2. Description of the Prior Art
Heretofore a current mirror type current source using FETs is discussed in "Analysis and Design of Analog Integrated Circuit", Second Edition (1984), John Wiley & Sons, Inc. pp 709-718 (in particular, cf. p. 710 FIG. 12.5 etc.).
Summary of the Invention
In a standard current mirror circuit according to the prior art technique described above no attention is paid to fluctuations in the power supply voltage and the temperature or fluctuations of elements such as fluctuations in the threshold voltage, etc. when field effect transistors are used. Therefore there was a problem that current varied due to fluctuations in the power supply voltage and the temperature and fluctuations of elements.
Consequently an object of this invention is to provide a constant voltage circuit or a constant current circuit, which is not influenced by fluctuations in the power supply voltage or the temperature and more preferably which is not influenced by fluctuations of elements.
Other objects and new features of this invention will be obvious from the following description.
A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained.
A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.
As described above, since the element constants of the circuit elements constituting the constant voltage circuit are so set that fluctuations in the fluctuating voltage are cancelled, a constant voltage output can be obtained.
Further, since the constant current FET is biased by the constant voltage output, a constant current flows through the FET and thus a constant current circuit can be obtained.
Brief Description of the Drawings
FIG. 1 shows a circuit diagram representing a constant voltage circuit and constant current circuit according to a basic embodiment of this invention;
FIG. 2 shows a circuit diagram representing a constant voltage circuit and a constant current circuit according to a concrete embodiment of this invention;
FIGS. 3 to 7 show circuit diagrams representing semiconductor circuits according to modified embodiments of this invention; and
FIG. 8 shows a circuit diagram representing a prior art current amplifier.
Description of the Preferred Embodiments
FIG. 1 shows a circuit diagram representing a constant voltage circuit and a constant current circuit according to a basic embodiment of this invention. A voltage converting circuit 1 acts as first means generating a converted control voltage V.sub.2 by attenuating or dividing fluctuating voltage V.sub.1. The converted control voltage V.sub.2 is applied to the gate of an N-channel amplifying FET Q.sub.2 and the drain of the FET Q.sub.2 is connected with a fluctuating power source V.sub.1 through an impedance element 2 serving as load means. Further the source of the FET Q.sub.2 is connected with the ground potential GND. The attenuation or division ratio of the voltage converting circuit 1, the mutual conductance of the amplifying FET Q.sub.2 and the impedance of the impedance element 2 are so set that the voltage drop across the impedance element 2 cancels the fluctuating amount of the fluctuating voltage V.sub.2.
Consequently V.sub.2 increases with increasing V.sub.1 ; the current I flowing through the impedance element 2 increases; the voltage drop across the impedance element 2 increases; and thus the output voltage V.sub.3 is maintained constant. When V.sub.1 decreases, inverse phenomena occur. For the same reason V.sub.3 is maintained constant and thus it is possible to obtain the constant voltage output V.sub.3. The constant voltage output V.sub.3 obtained in this way is applied to the gates of constant current FETs Q.sub.31 -Q.sub.3n. Each of the constant currents I.sub.31 -I.sub.3n flows through the drain-source path of each of these constant current FETs Q.sub.31 -Q.sub.3n, respectively.
The constant voltage operation and the constant current operation described above will be analyzed below, by using some equations.
The relation between the input voltage V.sub.1 and the control voltage V.sub.0 of the voltage converting circuit 1 can be represented by the following equation;
On the other hand the current I flowing through the impedance element 2 is given by the following equation;
At the same time this current I is the drain current for the amplifying FET Q.sub.2, which is given by the following equation;
where V.sub.TH2 and K.sub.2 represent the threshold voltage and the mutual conductance of the FET Q.sub.2, respectively.
Transforming Eq. (2) stated above, the following equation can be obtained;
Substituting the right member of Eq. (3) for I in Eq. (4), the following equation is obtained.
Consequently the functions f and g as well as K.sub.2 and V.sub.TH2 are so set that the following equation (6) is satisfied;
g.sup.-1 {K.sub.2 .multidot.(f(V.sub.1)-V.sub.TH2).sup.2 }=V.sub.1 -.alpha.(6)
where .alpha. is a constant.
Transforming Eqs. (5) and (6), the following equation is obtained;
In this way it is possible to set the output voltage V.sub.3 at a constant value, which is substantially independent of the fluctuating voltge V.sub.1. When the constant voltage V.sub.3 =.alpha. is applied to the gates of the constant currents FETs Q.sub.31 -Q.sub.3n, the threshold voltage and the mutual conductance of the FET Q.sub.31 being V.sub.TH31 and K.sub.31, respectively, the current I.sub.31 flowing through the drain-source path of the FET Q.sub.31 is given by the following equation;
On the other hand, when Eq. (7) satisfies
where .beta. is a constant physical quantity, which depends hardly on fabrication fluctuations, variations in the temperature, etc., Eq. (8) is given by
and thus it is possible to realize a constant current source, which is not influenced by fabrication fluctuations, variations in the temperature and variations in the voltage V.sub.1.
Hereinbelow the meaning of f, g, .alpha. and .beta. and how to choose them will be explained more in detail by using concrete embodiments.
FIG. 2 shows a circuit diagram representing a constant voltage circuit and a constant current circuit according to a concrete embodiment of this invention. The embodiment differs from that represented by FIG. 1 in that the voltage converting circuit 1 is constituted by FETs Q.sub.1A and Q.sub.1B connected in series, whose drain and gate are short-circuited and that the impedance element 2 is constituted by an FET Q.sub.2A, whose drain and gate are similarly short-circuited. Representing the gate-source voltage, the threshold voltage and the mutual conductance of the FETs Q.sub.1A, Q.sub.1B, Q.sub.2A, Q.sub.2B, Q.sub.31 and Q.sub.3n by V.sub.gs1A, V.sub.gs1B, V.sub.gs2A, V.sub.gs2B, V.sub.gs31, V.sub.gs3n ; V.sub.th1A, V.sub.th1B, V.sub.th2A, V.sub.th2B, V.sub.th31, V.sub.th3n ; K.sub.1A, K.sub.1B, K.sub.2A, K.sub.2B, K.sub.31 and K.sub.3n, respectively, the following two equations are valid; ##EQU1##
Here, if the variables are so set that K.sub.1A =K.sub.1B and V.sub.th1A =V.sub.th1B are valid, using Eq. (11), a relation V.sub.gs1A =V.sub.gs1B can be obtained. Using this relation, Eq. (12) is transformed into; ##EQU2##
On the other hand, since a relation V.sub.gs1B =V.sub.gs2B is valid, the drain current I.sub.2 of the FET Q.sub.2B is given by the following equation; ##EQU3##
Further, since this current I.sub.2 flows also through the FET Q.sub.2A, the following equation is valid;
Transforming Eq. (15), the following equation is obtained; ##EQU4##
On the other hand, since a relation V.sub.3 =V.sub.1 -V.sub.gs2A is valid, inserting Eqs. (14) and (15) in this relation, the following equation is obtained; ##EQU5##
Here, if K.sub.2B and K.sub.2A are so set that K.sub.2B /K.sub.2A =4, Eq. (17) can be transformed as represented by the following equation; ##EQU6## and thus it is possible to obtain the constant voltage V.sub.3, which is independent of variations in the power source V.sub.1.
When FETs Q.sub.2A and Q.sub.2B are fabricated under same fabrication conditions, a relation V.sub.th2A =V.sub.th2B =V.sub.TH is obtained. When this relation is inserted into Eq. (18), it is transformed as indicated by the following equation and it is possible to take out the threshold voltage V.sub.TH therefrom. From this result it can be understood that this circuit is usable also as a threshold voltge detecting circuit;
On the other hand, when the drain current I.sub.31 of the FET Q.sub.31 is calculated by using Eq. (18), the following equation can be obtained; ##EQU7##
Consequently, when the FETs Q.sub.2A, Q.sub.2B and Q.sub.31 are fabricated under same fabricating conditions, a relation V.sub.th2A =V.sub.th2B =V.sub.th31 =V.sub.TH is obtained.
After that, by implanting impurity ions in the channel portions of the FETs Q.sub.2A and Q.sub.31, V.sub.th2A =V.sub.th31 =V.sub.TH -.DELTA.V.sub.TH is realized. This variation amount .DELTA.V.sub.TH is controlled with a high precision by controlling the amount of implanted ions. Inserting this condition in Eq. (20), the following equation is obtained; ##EQU8##
Consequently it can be understood that a constant current I.sub.3 set with a high precision is obtained by using Eq. (21).
On the other hand relations V.sub.th2B =V.sub.TH +.DELTA.V.sub.TH and V.sub.2A =V.sub.31 =V.sub.TH are obtained by implanting impurity ions in the channel portion of the FET Q.sub.2B after having fabricated the FETs Q.sub.2A, Q.sub.2B and Q.sub.31 under same fabrication conditions. Inserting these relations in Eq. (20), the following equation is obtained; ##EQU9##
Further relations V.sub.th2A =V.sub.TH -.DELTA.V.sub.TH and V.sub.th2B =V.sub.th31 =V.sub.TH are obtained by implanting impurity ions in the channel portion of the FET Q.sub.2A after having fabricated the FETs Q.sub.2A, Q.sub.2B and Q.sub.31 under same fabrication conditions. Inserting these relations in Eq. (20), the following equation is obtained; ##EQU10##
FIG. 3 indicates a modified embodiment, by which the following improvements are added to the embodiments indicated in FIG. 2.
That is, additional FETs Q.sub.31 '-Q.sub.3n ' are connected with the constant current FETs Q.sub.31 -Q.sub.3n in FIG. 2, respectively, and the gates of these additional FETs Q.sub.31 '-Q.sub.3n ' are biased with a voltage obtained by dividing the voltage V.sub.cc of the power source by means of resistances R.sub.1 and R.sub.2.
By this circuit connection indicated in FIG. 3 it is possible to reduce influences of the drain conductance on the constant current FETs Q.sub.31 -Q.sub.3n. In this way no unnecessarily high voltage is applied to the drains of the FETs Q.sub.31 -Q.sub.3n, even if the voltages V.sub.31 -V.sub.3n are high, and thus a result can be obtained that variations in the currents I.sub.31 -I.sub.3n are small.
FIG. 4 indicates another modified embodiment, by which the following improvements are added to the embodiment indicated in FIG. 2.
That is, FETs Q.sub.1C and Q.sub.31 '-Q.sub.3n ', whose gate and drain are short-circuited, and an FET Q.sub.2C are connected additionally therewith.
When an analysis similar to that described above is effected for the circuit indicated in FIG. 4, a conclusion described below can be obtained; ##EQU11##
Here, if relations K.sub.1A =K.sub.1B =K.sub.1C and V.sub.th1A =V.sub.th1B =V.sub.th1C are realized, a relation V.sub.gs1A =V.sub.gs1B =V.sub.gs1C is obtained. By operations similar to those described above the following equations can be obtained; ##EQU12##
Here, if K.sub.2C and K.sub.2A are so set that K.sub.2C /K.sub.2A =9 is fulfilled, Eq. (30) can be transformed as follows; ##EQU13##
On the other hand, the current flowing through the FETs Q.sub.31 and Q.sub.31 ' is expressed as follows; ##EQU14##
If the parameters are so set that relations K.sub.31 =K.sub.31 ' and V.sub.th31 =V.sub.th31 ' are realized, a relation V.sub.gs31 =V.sub.gs31 ' is obtained by using Eq. (32). On the other hand, since there is a relation V.sub.3 =V.sub.gs31 +V.sub.gs31 ', the following equation is obtained; ##EQU15##
Consequently the following equation can be obtained by using Eqs. (31), (32) and (33); ##EQU16##
In this way relations V.sub.th2A =V.sub.th31 =T.sub.TH -.DELTA.V.sub.TH and V.sub.th2C =V.sub.TH are obtained by implanting impurity ions in the channel portions of the FETs Q.sub.2A and Q.sub.31 after having fabricated the FETs Q.sub.2C, Q.sub.2A and Q.sub.31 under the same fabrication conditions. Inserting these relations in Eq. (34), the following equation is obtained; ##EQU17##
FIG. 5 indicates an embodiment, by which the following modification is added to the embodiment indicated in FIG. 2. That is, the FETs Q.sub.1A and Q.sub.1B in FIG. 2 are replaced by two resistances R.sub.1 and R.sub.2 in FIG. 5. If R.sub.1 and R.sub.2 are so set that R.sub.1 =R.sub.2, Eq. (13) is satisfied and it is easily understood that the circuit indicated in FIG. 5 works in the manner completely identical to that described for FIG. 2.
FIG. 6 indicates an embodiment, by which the N-channel FET in FIG. 2 is replaced by a P-channel FET. In this embodiment indicated in FIG. 6 the constant voltage is obtained between the power supply line V.sub.cc and the output V.sub.3 and the constant current flows out from the drains of the FETs Q.sub.31 -Q.sub.3n.
In the embodiment indicated in FIG. 7 the number of FETs connected in series in FIG. 4 is further increased and it is easily understood that the circuit indicated in FIG. 7 works in a manner similar to that described for FIG. 4.
FIG. 8 is a circuit diagram illustrating the construction of the current amplifier disclosed in Japanese Patent Unexamined Publication No. 50-43870 corresponding to Japanese patent application claiming Conventional priority on the basis of U.S. patent application Ser. No. 381,175 filed July 20, 1973 and the form itself of the circuit connection has a good similarity with the embodiment of this invention indicated in FIG. 2, except that the circuit elements are bipolar transistors. The effective area of the base-emitter junction of the transistors Q.sub.1A and Q.sub.2B is so set that it is m times as large as that of the other transistors. Consequently the relationship between the input current I.sub.IN and the output current I.sub.OUT of this current amplifier can be represented by; ##EQU18## and thus it differs from the operation of the constant voltage circuit or the constant current circuit according to this invention.
This invention is not restricted to the embodiments described above. For example junction type FETs, MOSFETs and further MESFETs (Metal Semiconductor Field Effect Transistor) can be used for the FETs.
As explained above, according to this invention, it is possible to realize a current source, whose output current is determined by the difference .DELTA.V.sub.TH between the K value and the threshold voltage of the transistors. Since these values are hardly influenced by variations in the power source voltage and the temperature, it is possible to realize a current source, whose output current value is not influenced by variations in the power source voltage and the temperature or fluctuations of the threshold voltage.
Claims
What is claimed is:
1. A semiconductor circuit comprising: (1) a first means for generating a converted voltage at an output thereof, a first end thereof being connected with a first operating potential, a second end thereof being connected with a second operating potential, said converted voltage being obtained by attenuating or dividing a potential difference between said first operating potential and said second operating potential; (2) an amplifying FET, having a gate, source and drain, the gate of which responds to said converted voltage of said first means and the source of which is connected to said second operating potential; and (3) load means, a first end thereof being connected to a drain of said amplifying FET, a second end thereof being connected with said first operating potential; wherein said load means is another FET whose gate and drain are connected with said first operating potential and whose source is connected with said drain of said amplifying FET, wherein an attenuation or dividing ratio of said first means is set to a predetermined value, and wherein a ratio of a conductance of said amplifying FET to a conductance of said other FET is set to a value which is substantially equal to a square number of a reciprocal number of said predetermined value, whereby a voltage drop across said load means substantially cancels fluctuations of a voltage at said drain of said amplifying FET due to fluctuations in said potential difference.
2. A semiconductor circuit according to claim 1 further comprising: (4) a constant current FET having a gate which responds to a voltage at said drain of said amplifying FET and having a source which is connected with said second operating potential, whereby a current maintained substantially constant flows through a drain-source path of said constant current FET.
3. A semiconductor circuit according to claim 2, wherein a threshold voltage of at least one of said amplifying FET, said constant current FET and said other FET is regulated by implanting impurity ions to a channel thereof.
4. A semiconductor circuit according to claim 3, further comprising: (5) an additional FET having a gate, source and drain, the source thereof being connected with said drain of said constant current FET, the gate thereof being biased at a predetermined potential, said constant current flowing through the drain thereof.
Patent Citations (9)
Non-Patent Literature (2)
- Wiley et al., "Analysis and Design of Analog Integrated Circuit", MOS Amplifier Design, 1984, pp. 709-718.
- Baitinger et al., "Constant Current Source Network", IBM Technical Disclosure, 2/71, pp. 2516.