Method and Apparatus for Processing Picture Image Signals

This invention relates to a digital color correction method which separates and corrects the colors of an original color image by photo-electronic scanning and then outputs picture image signals for reconstructing a color picture image and the apparatus therefor.

In the color tone correction generally conducted by scanners, etc., in addition to the basic masking for eliminating improper absorption of ink colors, there is provided means for removing distortion of colors or for slightly correcting the tone of a particular hue according to the taste of an individual operator. Such a correction is achieved by discriminating the hue and saturation of an original image with the basic three color signals and by adding appropriate correction signals to the basic signals. FIG. 1 shows an example of the structure disclosed in Japanese Kokoku No. 50-14845 wherein the color separation signals B, G, R, obtained by photo-electronic scanning using color separation filters of blue (B), green (G) and red (R), are converted to density signals Y.sub.0, M.sub.0, C.sub.o in logarithmic conversion circuits 1 through 3. The density signals Y.sub.0, M.sub.0, C.sub.0 are fed to masking circuits 4 through 6 and converted to the corrected density signals Y.sub.1, M.sub.1, C.sub.1. The masking circuits 4 to 6 perform computations such as Y.sub.1 =Y.sub.0 -aM.sub.0 -bC.sub.0 supply corrected density signals Y.sub.1, M.sub.1, C.sub.1 to a color correction signal generating circuit 7 which outputs color correction signals Y.sub.C, M.sub.C, C.sub.C which correspond to density signals Y.sub.1, M.sub.1, and C.sub.1. The color correction signal Y.sub.C is, for example, of a form of Y.sub.C =a1.multidot.(Y)+a2.multidot.(G)+a3.multidot.(C)+a4.multidot.(B)+a5.multid ot.(M)+a6.multidot.(R). The other color correction signals M.sub.C and C.sub.C are of a similar form. The symbols (Y), (G), . . . , (R) denote the hue signals formed in the color correction signal generating circuit 7. The color correction signals Y.sub.C, M.sub.C, C.sub.C are respectively inputted to the subtracting terminals of subtracters 8 through 10 and the density signals Y.sub.1, M.sub.1, C.sub.1 from the masking circuits 4 through 6 are respectively inputted to the adding terminals thereof; the subtracters 8, 9 and 10 output signals Y.sub.2 =Y.sub.1 -Y.sub. C, M.sub.2 =M.sub.1 -M.sub.C, C.sub.2 =C.sub.1 -C.sub.C, respectively. The coefficients a, b mentioned above may be arbitrarily varied by a potentiometer, etc., and the coefficients a1 through a6 are also arbitrarily varied. These coefficients are adjusted by an operator whenever necessary. The description of black print signal circuits for producing a black print is omitted for simplifying the explanation.

The correction system of the prior art mainly aims at eliminating incompleteness which means that the spectral characteristics of the inks overlap to a considerable extent. The masking circuits 4 through 6 attain such an object, being supplemented by an operator of the scanner who sets coefficients appropriately for producing prints with an accurate color rendition. The system therefore does not consider the correction of improperly absorbed components of color elements in an original image which are contained in the density signals Y.sub.0, M.sub.0, C.sub.0 obtained by photo-electronic scanning of the color image. Improperly absorbed components of color elements refer to those color elements having undesired spectral transmittances (e.g.--color dyes, color pigment inks, etc.). It is impossible to know the exact amount of these color elements. The weights of respective components in the corrected density signals Y.sub.1, M.sub.1, C.sub.1 which are to be inputted at the color correction signal generating circuit 7 are not always equal. Hue signals (Y), (G), (C), (B), (M), (R) are produced from the color correction signal generating circuits 7 based on the density signals Y.sub.1, M.sub.1, C.sub.1. When a neutral color portion of an original image is scanned, the hue signals of all the 6 types should be zero. But if the weight of the density signals Y.sub.1, M.sub.1, C.sub.1 is not equal, either one of the hue signals with a positive value is outputted and a correction signal implying as if the image is colored may be outputted accidentally. There cannot be more than two hue signals with a positive value. In other words, as the system conducts computation using symmetrical formulas on the 3 color signals, if the weight of respective signals is not equal, the image is discriminated to be a hue different from the actual hue, especially near the neutral color portion (gray), thereby producing undesirable tones in the reproduced picture image. When a noise or an error occurs in the color signal in the process prior thereto, a similar phenomenon may occur.

The hue signals (Y), (G), . . . , (R) used may be obtained by computation using the basic three color signals. Since the color in the original image belongs to one of the six hues of blue, cyan, green, yellow, red and magenta which are obtained by dividing a color space into six portions, the computation of one hue signal or the computation of at most two hue signals adjacent to the color of the original image would suffice. This relationship is shown in FIG. 3. However, since it is impossible to decide before computation to which hue it should be classified, all of the hue signals must be computed. If, in order to carry this out in an analog circuit, the number of circuits corresponding to the number of hues should be prepared so as to conduct parallel computation and circuits should be adjusted; this is not only troublesome but is likely to cause greater errors. If such a system is constructed exclusively by digital circuits, on the other hand, the space required by the circuits for parallel computation becomes large, pushing up the cost. Although hue signals may be computed by digital circuits in time sequence, the speed is slow compared to the parallel computation.

There has been proposed a circuit using digital operation in order to avoid the temperature dependency or chronological changes of analog circuit components which used to be utilized in the prior art color correction circuits. For instance, as disclosed in Japanese Laid-open Patent Application No. 123201/1978, for executing high-speed real time processing, a memory table of the outputs Y.sub.2, M.sub.2, C.sub.2 corresponding to the input density signals Y.sub.0, M.sub.0, C.sub.0, and interpolation are employed to avoid a large capacity memory. However, if input data is used as address as a means of digitalizing color computation and a memory table which has been written-in with output data is accessed, the memory table has to be prepared prior to actual scanning. Further, it is inconvenient in that the output data Y.sub.2, M.sub.2, C.sub.2 must be computed for all the combinations of the input density signals Y.sub.0, M.sub.0, C.sub.0. When coefficients which used to be set by a potentiometer in the analog circuit had to be varied, those computations must be redone for all the memory tables. Such procedures are not only complicated but might require operations extremely different from the conventional method. Even if the system is structured to divide the color computation into plural steps, to prepare such memory tables as mentioned above on each step, and to re-write only the tables which are related to the change of coefficients would not achieve the effectiveness which justifies all the trouble. If interpolation is employed in order to reduce the memory capacity, there runs a higher possibility of making output data unnatural by errors in computation. In order to avoid such mistakes, more complicated interpolation will be additionally needed, thereby incapacitating real time processing.

Accordingly, the principal object of the present invention is to provide a color correction method which can obviate above mentioned problems and the apparatus therefor. The method is adapted to equalize the weights of the three signals processed in the color processing operation of the picture image signal output, whereby the six hue signals produced from the weighted signals divide a color space when such method is used to photo-electronically scan a color original image and then reproduce a picture image by digitally processing the tone.

Another object of this invention is to provide a tone correction circuit which can obviate the aforementioned defects and inconveniences.

In other words, in the present invention, six hue signals (magenta, blue, cyan, green, yellow, and red) are generated from three color density signals (yellow, magenta, and cyan), and that these six hue signals are made to equally divide a color space. Three color correction signals as defined below are generated for a given color:

where k.sub.1j, k.sub.1k, k.sub.2j, k.sub.2k, k.sub.3j, and k.sub.3k are predetermined coefficients, and H.sub.1 and H.sub.2 are hue signals, all of which are defined in the table below:

The coefficients k.sub.1j, k.sub.2j, and k.sub.3j are selected to adjust the level of the predominant primary color component (yellow, magenta, or cyan)--for example, cyan (C) in the case where C>M>Y, shown in the first line of the table. The coefficients k.sub.1k, k.sub.2k, and k.sub.3k are selected to adjust the level of predominant secondary color component (blue, green, or red)--for example, blue (B) in the case where C>M>Y.

Essentially, the present invention involves generating three color correction signals by ranking the three color separation signals, Y, M, and C in order from largest to smallest (for example, C, M, Y), taking the difference between the two largest (C-M) and between the two smallest (M-Y), multiplying those differences by predetermined coefficients depending on which signal is to be corrected (Y, M, or C), and adding the results of the two multiplications to obtain the color correction signal for the color separation signal in questions (Y, M, or C).

The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

In the accompanying drawings:

FIG. 1 is a block diagram to show an embodiment of the prior art color correction system;

FIGS. 2A and 2B are block diagrams to show an embodiment of the apparatus according to the present invention;

FIG. 3 shows a portion of the operation of the apparatus in FIG. 2A;

FIG. 4 is a block diagram to specifically show an embodiment of a hue discriminating circuit;

FIG. 5 is a block diagram to shown an embodiment of a comparator to be used in the hue discriminating circuits; and

FIG. 6 is a block diagram to show another embodiment of the hue discriminating circuit.

This invention concerns a method and apparatus for digital color correction, which obtains and then converts input color separation signals of an original image to digital signals respectively, multiplies those digital color separation signals by predetermined coefficients and accumulates them for the equivalent neutral density conversion which produces an equal level at a gray point, obtains the divided hue signals such as yellow (Y), green (G), cyan (C), blue (B), magenta (M), and red (R) from equivalent neutral density signals which are produced by the equivalent neutral density conversion, multiplies those signals by correction coefficients and adds them to obtain color correction signals for yellow, magenta and cyan.

The operation thereof will now be explained referring to the circuit shown in FIGS. 2A and 2B.

Three color separation signals Y.sub.0, M.sub.0, C.sub.0 which are obtained by photo-electronic scanning of a color original image and processed through color separation filters and logarithmic converters are inputted to A/D converters 11, 12 and 13, respectively. An unsharp signal U.sub.0 which is obtained through a greater aperture and a logarithmic converter is inputted to an A/D converter 14. The digital density signals Y.sub.1 through C.sub.1 which are outputted from the A/D converters 11 through 13 are respectively inputted into a data selector 16. A digital unsharp signal U.sub.1 supplied from the A/D converter 14 is inputted into an unsharp mask signal generating circuit 15 together with a digital density signal M.sub.1 and an unsharp mask signal U.sub.2 generated therein is inputted to the data selector 16. The outputs from the data selector 16 (X.sub.11 to X.sub.31) are fed to multiplier/accumulators 20 through 22 whose outputs P.sub.1 through P.sub.3 are fed to registers 26 to 28 as well as to data selectors 33 to 35 via slicers 23 to 25. The outputs Y.sub.E ' to C.sub.E ' from the registers 26 to 28 are inputted to a hue discriminating circuit 29. A hue signal CL which has been discriminated by the hue discriminating circuit 29 is inputted into the data selector 16, and a hue address signal CAD indicating which hue is being outputted is fed into a memory address generating circuit 31 and a memory address signal MAD from the memory address generating circuit 31 is inputted to memories 17 through 19 via the data selector 32.

The outputs ASY through ASC from the data selectors 33 to 35 are inputted respectively to memory tables 36 to 38 for gradation conversion and the hue data Y.sub.3 through C.sub.3 which has been gradation-converted in the memory tables 36 to 38 are inputted to D/A converters 45 to 47 for analog conversion respectively via registers 42 to 44 so as to be outputted as color-corrected hue signals Y.sub.4 to C.sub.4.

The outputs X.sub.12 to X.sub.32 from the memories 17 to 19 are inputted to multiplier/accumulators 20 to 22 while address data are inputted to the memories 17 to 19 via an address bus AB connected to a computer, etc. and the data selector 32. The memories are adapted to store the data (coefficient) which is transmitted by the data bus DB to the address designated by the abovenoted address data through input lines DI.sub.1 to DI.sub.3. The memory tables 36 to 38 store the data transmitted by the data bus DB at the address designated by the address data which has been inputted from the address bus AB through data selectors 33 to 35, by supplying the data through gates 39 to 41. These memories 17 to 19 and the memory tables 36 to 38 are constructed with RAMs (Random Access Memories). The memory address generating circuit 31 and the hue discriminating circuit 29 are timing controlled by a timing control circuit 30 so that the timing signals T (t.sub.1 to t.sub.20) respectively control the data selector 16, the memories 17 to 19, the data selectors 32 to 35, the gates 39 to 41, the memory tables 36 to 38 and the registers 26 to 28 and 42 to 44 with a predetermined timing.

In the structure mentioned above, the digital density signals Y.sub.0, M.sub.0, C.sub.0 of the color original image which have been measured through the 3-color separation filter include improper absorption related to the color elements comprising the color original image and the filter. The weights of these three digital density signals Y.sub.0 to C.sub.0 are not necessarily equal to each other. However, the above mentioned two problems may be eliminated by operating the equivalent neutral density conversion indicated below. ##EQU1##

The matrix elements aij in the above formula (1) are constants which can be determined by the color element system of the color original image and the color separation filter and are set at values which make Y.sub.E, M.sub.E, C.sub.E on the same level when the gray portion of the image is measured. Since the formula (1) above is expressed in the sum of the multiplication of the constant aij by the signals Y.sub.1, M.sub.1, C.sub.1, for instance Y.sub.E =a11.multidot.Y.sub.1 +a12.multidot.M.sub.1 +a13.multidot.C.sub.1, it is executable by carrying out multiplication and then addition thereof for Y.sub.E, M.sub.E, C.sub.E consecutively. The coefficient data DI.sub.1 (all to a14 and k11 to k16), DI.sub.2 (a21 to a24 and k21 to k26) and DI.sub.3 (a31 to a34 and k31 to k36) transmitted from a computer, etc. through the data bus DB have been written-in preliminarily at the address designated by the address data transmitted from a computer, etc. through the address bus AB. The coefficients a14, a24, a34, k11 to k16, k21 to k26 and k31 to k36 will be described below. The multiplier/accumulators 20 to 22 are adapted to multiply the digital density signals Y.sub.1 to C.sub.1 transmitted through the data selector 16 by the coefficients stored in the memories 17 to 19, and to accumulate the resulting products.

The timing control circuit 30 first controls the data selector 16 with the timing signal t.sub.1 to select the digital density signal Y.sub.1 out of the input signals so as to feed it to the multiplier/accumulators 20, 21, 22. The memory address data from the memory address generating circuit 31 is added by the timing signal t.sub.5 to the address lines of the memories 17 to 19 via the data selector 32. As a result, the coefficient all is outputted from the memory 17, the coefficient a21 from the memory 18, and the coefficient a31 from the memory 19 to be fed to the multiplier/accumulators 20, 21, 22, respectively. Thus, the products a11.multidot.Y.sub.1, a21.multidot.Y.sub.1, a31.multidot.Y.sub.1 are respectively outputted to the outputs P.sub.1, P.sub.2, P.sub.3 of the multiplier/accumulators 20, 21 and 22. (timing I for the above).

With the next timing II, a digital density signal M.sub.1 is selected from the data selector 16 to be inputted to the multiplier/accumulators 20 to 22 while the memory address signal MAD from the memory address generating circuit 31 selects the coefficient a12 which is stored in the memory 17 via the data selector 32 as well as a coefficient a22 stored in the memory 18 and a coefficient a32 stored in the memory 19 so as to feed them to the multiplier/accumulators 20, 21, 22. Accordingly, the digital density signals M.sub.1 and the coefficients a12 to a32 are multiplied in the multiplier/accumulators 20 to 22 and the product thereof is added to the result of the previous multiplication. Therefore, the respective outputs P.sub.1, P.sub.2, P.sub.3 of the multiplier/accumulators 20, 21, 22 are fed with a11.multidot.Y.sub.1 +a12.multidot.M.sub.1, a21.multidot.Y.sub.1 +a22.multidot.M.sub.1, a31.multidot.Y.sub.1 +a32.multidot.M.sub.1.

With the next timing III, since the digital density signal C.sub.1 is selected from the data selector 16 and inputted to the multiplier/accumulators 20 to 22, while coefficients a13, a23, a33 are respectively outputted from the memories 17 to 19 to be fed to the multiplier/accumulators 20 to 22, the result P.sub.1, P.sub.2, P.sub.3 of the multiplication and accumulation by the multiplier/accumulators 20, 21, 22 become respectively a11.multidot.Y.sub.1 +a12.multidot.M.sub.1 +a13.multidot.C.sub.1, a21.multidot.Y.sub.1 +a22.multidot.M.sub.1 +a23.multidot.C.sub.1, a31.multidot.Y.sub.1 +a32.multidot.M.sub.1 +a33.multidot.C.sub.1.

As indicated above, with the timings I to III, the outputs P.sub.1 to P.sub.3 of the multiplier/accumulators 20 to 22 receive the equivalent neutral density Y.sub.E, M.sub.E, C.sub.E which is expressed by the formula (2), which is a modification of the formula (1); ##EQU2## The equivalent neutral densities Y.sub.E, M.sub.E, C.sub.E thus obtained are stored in the registers 26 to 28 (as Y.sub.E ', M.sub.E ', C.sub.E ') via the slicers 23 to 25. The slicers 23 to 25 are operated to output the predetermined maximum or the minimum values when the input (Y.sub.E to C.sub.E) exceeds those predetermined values. During the above mentioned timings I to III, an unsharp mask signal U.sub.2 is generated in the unsharp mask signal generating circuit 15. In this case, the unsharp mask signal U.sub.2 is computed by the formula, U.sub.2 =M.sub.1 -U.sub.1.

With the next timing IV, an unsharp mask signal U.sub.2 is outputted from the data selector 16 and is inputted to the multiplier/accumulators 20 to 22 together with the coefficients a14 to a34 which have been selectively outputted from the memories 17 to 19. Since the multiplier/accumulators 20 to 22 multiply the input unsharp mask signal U.sub.2 and the coefficients a14 to a34, and then add the products thereof to the accumulation Y.sub.E to C.sub.E, the results, Y.sub.S to C.sub.S, of the formula below will be outputted to the outputs P.sub.1 to P.sub.3 thereof. ##EQU3##

With the next timing V, selective color correction computation is conducted wherein selective color correction is expressed by Y.sub.C =Y.sub.S +Y.sub.CC, M.sub.C =M.sub.S +M.sub.CC, C.sub.C =C.sub.S +C.sub.CC using Y.sub.CC, M.sub.CC, C.sub.CC as the correction signals. The correction signals Y.sub.CC, M.sub.CC, C.sub.CC are expressed by the formula below: ##EQU4##

(Y), (G), (C), (B), (M) and (R) are hue signals which are obtained by dividing all hues as shown in FIG. 3 in accordance with Table 2 described hereinafter. Although Table 2 does not show the case of the equivalent neutral density, it is easily applicable to the equivalent neutral density. The hue signals (Y) to (R) are different from the digital separation signals, respectively. That is, the present of () means the hue of colors and therefore the meanings of, for example (Y) and Y are different. The hue signals (Y) to (R) are generated in the hue discriminating circuit 29 during the above mentioned timing IV. As is clear from FIG. 3, since two of the six hue signals at most are outputted for each one of color tones, it would suffice if the operation of multiplying and adding the coefficient kij is conducted by the multiplier/accumulators 20 to 22 for these two hue signals alone. Thus, (C) and (G) are outputted if the hue is a middle hue between cyan and green. The system operates in a similar fashion for other hues and at most, two hue signals are output. In other words, one (CL) of the hue signals (Y) to (R) is outputted from the hue discriminating circuit 29 by the timing control of the timing control circuit 30 at the timing V, and is fed to the multiplier/accumulators 20 to 22 via the data selector 16. The coefficient kij is set at a desired value by an operator. A hue address signal CAD is transmitted from the hue discriminating circuit 29 to the memory address generating circuit 31 to indicate which hue signal is being outputted, and the memory address generating circuit 31 outputs a memory address signal MAD in order to read out a coefficient kij corresponding to the hue signal which is being outputted to the memory address generating circuit 31. By feeding this memory address signal MAD to the memories 17 to 19 via the data selector 32, the coefficient kij which has been stored in advance in the memories 17 to 19 is selectively outputted to be fed to the multiplier/accumulators 20 to 22. The result of the multiplication of the hue signals and the coefficient kij conducted in the multiplier/accumulators is added to the accumulation values Y.sub.S, M.sub.S, C.sub.S which have been obtained up to the last operation. At the next timing VI, as similar operation is conducted for another hue signal, thereby outputting Y.sub.C, M.sub.C, C.sub.C to the outputs P.sub.1 to P.sub.3 of the multiplier/accumulators 20 to 22.

As described above, the equivalent neutral density conversion is executed at the timings I through III, and the adding of the unsharp mask signal is then executed at the timing IV, and the adding of the selective color correction signal is finally executed at the timings V and VI. The hue signal for the selective color correction uses the equivalent neutral density in the foregoing. The accuracy and the stability of the selective color correction are respectively high due to the character of the equivalent neutral density in the case of generating the hue signal for the selective color correction from the equivalent neutral density. It is easy to store the signals Y.sub.S, M.sub.S, C.sub.S in the registers 26 through 28 via the slicers 23 through 25 after the timing IV and to put the stored signals to use for generating of the hue signal for the purpose of the selective color correction by timing-controlling of the control circuit 30.

The above hue discriminating circuit 29 can be constructed, for instance, as shown in FIG. 4. The operation thereof will be explained below:

Y.sub.E ', M.sub.E ', C.sub.E ' are inputted to a comparating circuit 48 and a data selector 50. The comparating circuit 48 transmits signals of 3 bits, D.sub.1, D.sub.2, D.sub.3 to a control circuit 49 depending on the dimensional relation amount Y.sub.E ', M.sub.E ', C.sub.E '. For instance, if the relationship is Y.sub.E '>M.sub.E '>C.sub.E ', the output signal D.sub.1, D.sub.2, and D.sub.3 from the comparing circuit 48 will become "1", "1", and "0", respectively. Based on the above, the control circuit 49 outputs a control signal CT so that at the first timing (T.sub.56 ="0") the data selector 50 can select Y.sub.E ', M.sub.E ' to output them to the outputs X.sub.1, X.sub.2 and at the second timing (T.sub.56 ="1"), C.sub.E '. The Y.sub.E ' and M.sub.E ' which are outputted to the outputs X.sub.1, X.sub.2 of the data selector 50 at the timing 1 are transmitted to the addition input and the subtraction input terminals of the subtracter 51 while the output of the subtracter 51 receives the subtraction result CL=Y.sub.E '-M.sub.E '. At the subsequent timing 2, the outputs X.sub.1, X.sub.2 of the data selector 50 are similarly fed with M.sub.E ' and C.sub.E ' and the output of the subtracter 51 receives the subtraction result of CL=M.sub.E '-C.sub.E '. The signals CL output at the first and second timings above correspond to hue signals (Y) and (R), respectively. The hue discriminating circuit 29 will be further discussed below.

Table 1 shows the relationship between the inputs X.sub.11, X.sub.12 and the output P.sub.1 at the timings I to VI. A similar relationship holds for other input lines X.sub.21, X.sub.31, X.sub.22, X.sub.32 and the outputs P.sub.2, P.sub.3.

The series of multiplications and additions end as shown above. The obtained hue signals Y.sub.C, M.sub.C, C.sub.C become address signals ASY, ASM, ASC of the memory tables 36 to 38 for gradation conversion through the slicers 23 to 25 and the data selectors 33 to 35. The memory tables 36 to 38 comprise a data table wherein one input corresponds to one output. If an arbitrary data is written-in preliminarily as a value corresponding to an address, desired gradation conversion can be attained. The hue signals Y.sub.3, M.sub.3, C.sub.3 which have been gradation-converted in those memories 36 to 38 are transmitted via registers 42 to 44 for latch to the D/A converters 45 to 47, and then converted to analog values for output.

In the case when a coefficient data is written in the memories 17 to 19, the address signal thereof is outputted from a computer, etc. to the address bus AB, applied to the address line of the memories 17 to 19 via the data selector 32, and at the same time a coefficient data is outputted to the data bus DB and applied to the data input lines DI.sub.1 to DI.sub.3 of the memories 17 to 19, thereby successively writing in the coefficient data at the addresses designated by the input of the write-in strobed signal (t.sub.2 to t.sub.4). At such a time the data selector 32 operates to select address signals from outside. Similarly, in the case when data is to be written in the memory tables 36 to 38, an address signal on the address bus AB is supplied to the address lines (ASY to ASC) of the memory tables 36 to 38, and the data on the data bus DB is then supplied to the data input/output line of the memory tables 36 to 38 via the gates 39 to 41, thereby successively writing in the gradation conversion data at the addresses designated by the input of the write-in strobed signals (C.sub.12 to t.sub.14).

No explanation was given in the foregoing for the black signal (BK) which is necessary when preparing a separation printer for printing. The black print signals can be generated in parallel to the selective color correction by taking out Y.sub.S, M.sub.S, C.sub.S from the output P.sub.1 to P.sub.3 at the time when the operations have been completed until the timing IV, and inputting then separately into a black printer signal generating circuit for the operation at the timings V and IV for a black printer signal generation. The coefficients which are to be stored in the memories 17 to 19 are arbitrary. An alternative is, therefore, that the coefficients corresponding to various color original image materials are stored in advance in either a RAM or ROM (Read Only Memory) in coordination. When one of these color original images is designated, the coefficient corresponding thereto may be selectively outputted by a separate selection means (either manual or automatic) which is responsive thereto. In such a case, the coefficient may be set by a digital switch, etc. Although the unsharp mask signal U.sub.2 is operated by the formula (M.sub.1 -U.sub.1) in the foregoing, the formula may be either (Y.sub.1 -U.sub.1) or (C.sub.1 -U.sub.1), and the unsharp signal U.sub.1 may be subtracted from the synthetic signals Y.sub.1 to C.sub.1.

According to the present invention, a color space is divided into the six hues, i.e. magenta (M), blue (B), cyan (C), green (G), yellow (Y) and red (R). A given color can be expressed not only by one hue and may be located between two hues, such that the delicate hue can be represented by the distance from the center of each hue. This invention, therefor, employs as shown in FIG. 3, the hue signals (M), (B), (C), (G), (Y), and (R) having values which become maximum at the respective centers of the six hues and symmetrically and gradually reduce to zero at the center of the adjacent two hues. However, as is obvious from FIG. 3, since at most two of the hue signals (M) to (R) can be outputted for an arbitrary tint, the hue signal to be outputted next is predictable due to the sizewise relationship of the basic color signals Y, M and C as shown below in Table 2.

It is obvious from Table 2 where in a case that the sizewise relationship is C>M>Y, the hue signal (C) can be obtained by the formula:

and the hue signal (B) is obtained by the formula

In other words, the image signals Y, M and C are arranged in order of level value thereof, the hue signal I is obtained by subtracting the middle signal from the maximum signal and the hue signal II is obtained by subtracting the minimum signal from the middle signal. The hue signal I corresponds to a hue of the maximum signal and the hue signal II corresponds to a hue of the complementary color of the minimum signal.

In the above case, wherein the sizewise order is C, M and Y, therefore, two hue signals (C) and (B) can be obtained almost in parallel if the hue signal (C) is obtained from C-M at the first timing t.sub.1 and the hue signal (B) is obtained from M-Y at the second timing t.sub.2. The hue discriminating circuit 29 in accordance with the present invention is constructed based upon such a principle as above which will be described again referring to FIG. 4.

The circuit is arranged such that the color separation signals obtained by photo-electronic scanning of a color original image are processed by the basic operation, and digitalized color signals Y.sub.E ', M.sub.E ', C.sub.E ' are inputted to the comparing circuit 48 as well as to the data selector 50, and binary signals of 3 bits D.sub.1 to D.sub.3 are outputted from the comparing circuit 48 based upon the sizewise comparison of the color separation signals Y, M, C. FIG. 5 shows an example of the comparing circuit 48 wherein comparators 481 to 483 discriminate two inputs sizewise. The discriminating signal D1 becomes "1" when the color separation signal Y is greater than the level of the color separation signal M, (Y>M), the discriminating signal D2 becomes "1" when the color separation signal M is greater than the color separation signal C, (M>C), and the discriminating signal D3 becomes "1" when the color separation signal C is greater than the color separation signal Y, (C>Y). These discriminating signals D1 to D3 are inputted to the control circuit 49 and the control circuit 49 responds to the combination of these discriminating signals D1 to D3 and inputs a control signal CT to the data selector 50. The control circuit 49 outputs control signal CT to the data selector 50 for outputting the color separation signals X.sub.1, X.sub.2 corresponding to the combination of the discriminating signals D1 to D3 at the timing t.sub.1, t.sub.2 as shown in Table 3. The two color separation signals X.sub.1, X.sub.2 selected by the data selector 50 are inputted to the subtracter 51 and the difference between them (X.sub.1 -X.sub.2) is outputted as a correction hue signal CL.

In the structure shown above, if the level of the color separation signals Y, M, C, lowers in that order (Y>M>C), the discriminating signals D1 and D2 becomes "1" and the discriminating signal D3 becomes "0" as obvious from Table 3. Judging from such state, the control circuit 49 outputs first at the timing t.sub.1 a color separation signal Y as X.sub.1 from the data selector 50 as well as the color separation signal M as X.sub.2. The subtracter 51 accordingly performs the subtraction Y-M, to output the hue signal (Y) as the correction hue signal CL. At the subsequent timing t.sub.2, the color separation signal M is outputted as X.sub.1 and the color separation signal C as X.sub.2. The subtracter 51 performs the calculation M-C to output the hue signal (R) as the correction hue signal CL. The color tone is corrected as shown above by multiplying the correction hue signals CL (t.sub.1), CL (t.sub.2) output at the timings t.sub.1 and t.sub.2 by corresponding constants and adding the results for the basic color signals. Since the sizewise relationship of the color separation signals can be discriminated from Table 3, at each timing a hue signal is transmitted. The symbol * in Table 3 denotes the state where any of the color separation signals Y, M, C can be inputted.

FIG. 6 indicates another embodiment of the present invention including a threshold data memory 60 for storing threshold data for respective hues, a subtracter 61 for subtracting the threshold data T.sub.H selectively output from the threshold data memory 60 from the hue signal CL output from the subtracter 51 and an AND circuit 62 for obtaining a AND product of both positive and negative code signals SG responsive to the subtraction result and the subtracter output (CL-T.sub.H) from the subtracter 61. The threshold data memory 60 comprises a ROM or a RAM and is adapted to be arbitrarily set a threshold value correspondingly to each hue to be stored at a predetermined address. The threshold value T.sub.H which has been stored in the threshold data memory 60 is selectively outputted by the address signal CAD output from the control circuit 49 responsive to the state of the discriminating signals D1 to D3. The code signal SG output from the subtracter 61 becomes "1" when (CL-T.sub.H) is 0 or more, and "0" when (CL-T.sub.H) is negative, (CL-T.sub.H) <0. When (CL-T.sub.H) is positive, AND circuit 62 outputs (CL-T.sub.H) as is as a correction hue signal CL'. When (CL- T.sub.H) is 0 is less, the correction hue signal CL' becomes "0".

As described in the foregoing, the digital color correction system and the apparatus therefor can make three color signals equivalent by conducting a process to convert the basic three color signals to the equivalent neutral density of the color elements of the original image. In other words, when scanning the gray portion of the original image, the levels of the three hue signals become completely identical. Without using large storage capacity interpolation memory tables, but simply by inputting the operative color signals and the operational coefficients which have been written in the memory into high speed multipliers consecutively at a proper timing, multiplying and accumulating the same and continuously operating, it is possible to realize a circuit which enables color processing computation in real time.

The color correction circuit in accordance with the present invention can successively discriminate hue signals before the operation thereof, and operates two hue signals at most, thereby enabling real time operation at a higher speed but with a smaller circuit construction. By setting a threshold value on the hue signals, it can prevent errors in hue judgement which otherwise might be caused especially around neutral colors of a low saturation.

The description in the foregoing has been given for positive logic with respect to comparing circuits, etc., but a similar operation is applicable for negative logic circuits.