Data Bit Synchronizer

The present patent application is related to U.S. patent application Ser. No. 926,149, entitled, "Multiplexing Character Processor". The present patent application is also related to U.S. patent application Ser. No. 926,946 entitled, "Communications Base Microcontroller".

The present invention is directed to a system which is capable of interconnecting a multiplicity of peripheral devices, of various protocols, to a central processor. The peripheral devices such as terminals or other computers, transfer data in serial data streams. Several differing protocols have been established to initiate, control, verify, and terminate the data transfer between the peripheral devices and the central processor.

In prior art systems, peripheral devices are connected to communication lines and the communication lines are connected to a central processor bus (data channel or data storage). In these systems, a control function exists between a communication line and the central processor and between the communication line and a peripheral device. These controllers execute communication protocol between controllers and execute data exchange procedures between the controller and the central processor.

In prior art systems, when a communication line event occurs; such as series of bits being assembled into a byte, the beginning of the disassembly of a byte into a sequence of bits, or that a control signal has changed its binary state; a signal (request) is generated for the central processor. In systems where a multiplicity of peripheral devices are attempting to gain the attention of the central processor, various techniques such as polling (for requests) or hardware interrupting, enable the peripheral device to have access to the central processor based on the priority assigned to each peripheral device.

The present invention uses software to assemble and disassemble the protocol functions and uses hardware to do the multiplexing. The hardware directs indirect branching of software to permit the software to execute straight lines of software which branch back to hardware upon completion. The present multiplexing processor migrates traditional hardware functions into software routines.

Generally speaking, in prior art system the communication lines connected to the peripheral devices are scanned (multiplexed) for a line that is carrying a signal requiring (requesting) access to the central processor bus. Once a line has beenbeen found that is requesting bus access, if the priority of the peripheral device connected to that line has an assigned priority which is higher than any other peripheral device requesting access, it is granted exclusive access to the central processor bus until its communication task is completed. When the task is completed, the next highest priority peripheral device is granted access to the central processor bus and this procedure continues until all the requesting peripheral devices have been serviced. In some instances, a busy, high-priority peripheral device, once having gained access, will prevent the access of a lower-priority device thereby providing an unsatisfactory condition. The present invention eliminates the contention of peripheral devices for central processor software programs by synchronizing the central processor to the maximum total information rate of the connected peripheral devices. The basic machine cycle of the central processor is an integer factor of the bit time period of any of the connected communication lines.

The present invention eliminates priority, or contention problems by interleaving all incoming data, that is, every peripheral device requesting access to the communication processor is granted access and the signals from each of the peripheral devices are handled essentially simultaneously by a process called bit slicing.

In addition, the present invention is configured to accept a multiplicity of differing protocols from the peripheral devices. The present multiplexing character processor is designed to terminate a plurality of communication lines and to multiplex the data on the communication lines to a central processor bus.

In the present system, there is provided a program control, associated with each communication line, for disassembling the data received as a function of the protocol of the peripheral device connected to the communication line. A means is provided for multiplexing each program control in synchronism with the scanning of the communication lines.

In operation, the input data, having a particular bit width associated with a single transition of data, is bit sliced a multiplicity of times during its existence for each of the respective communication lines such that the signals applied to the central processor bus contain serial sequences each comprised of at least one slice of the signals on each of the communication lines. The corresponding program control functions are also sliced so that a multiplicity of program control functions, one associated with each peripheral device, are processed sequentially within each serial sequence to give the appearance of being handled simultaneously because the sequences repeat at a relatively high rate.

FIG. 1 illustrates the multiplexing character processor system interfacing a plurality of peripheral devices to a front end processor.

FIGS. 2A-2C, assembled in accordance with the map of FIG. 2, illustrates in schematic form, one-half of a line set interface adapter denoted generally as 100 in FIG. 1.

FIGS. 3A-3D, assembled in accordance with the map of FIG. 3, illustrate in schematic form, a latching and decoding circuit used in the line set interface adapter of FIGS. 2A-2C.

FIGS. 4A-4L, assembled in accordance with the map of FIG. 4, illustrate in schematic form the multiplexing character processor system of FIG. 1.

FIGS. 5A-5H, assembled in accordance with the map of FIG. 5, illustrate in schematic form, a data bit synchronizer (DBS) chip 302 which is the main part of block 300 in FIG. 1.

FIG. 6 illustrates a set of data bit synchronizer timing signals useful for an understanding of the operation of the present invention.

FIGS. 7A and 7B illustrate a set of data bit synchronizer control signals useful for an understanding of the operation of the present invention.

FIGS. 8A and 8B illustrate, in schematic form, one of nine control/status RAMs used in the DBS of FIGS. 5A-5H.

FIG. 9 illustrates a circuit diagram of one bit cell from the RAM of FIGS. 8A and 8B.

FIG. 10 illustrates a circuit diagram of one sense amplifier and bit driver from the RAM of FIGS. 8A and 8B.

FIG. 11 illustrates, in schematic form, the address decoder used in the RAM of FIGS. 8A and 8B.

FIGS. 12A-12C, assembled in accordance with the map of FIG. 12, illustrate, in block diagram form, the communications base microcontroller (CBuC) shown as block 700 in FIG. 1.

FIG. 13 illustrates, in schematic form, the timing chain used in the CBuC of FIGS. 12A-12C.

FIGS. 14A-14D, assembled in accordance with the map of FIG. 14, illustrate, in schematic form, the scan list and flags logic used in the CBuC of FIGS. 12A-12C.

FIGS. 15A-15D, assembled in accordance with the map of FIG. 15, illustrate, in schematic form, the control register used in the CBuC of FIGS. 12A-12C.

FIG. 16 illustrates, in schematic form, the real time clock used in the CBuC of FIGS. 12A-12C.

FIGS. 17A and 17B illustrate, in schematic form, the interval timer used in the CBuC of FIGS. 12A-12C.

FIGS. 18A-18C, assembled in accordance with the map of FIG. 18, illustrate, in schematic form, the line status word RAM used in the CBuC of FIGS. 12A-12C.

FIGS. 19A and 19B illustrate, in schematic form, the vector encoding logic used in the CBuC of FIGS. 12A-12C.

FIGS. 20A-20D, assembled in accordance with the map of FIG. 20, illustrate, in schematic form, the program counter RAM used in the CBuC of FIGS. 12A-12C.

FIG. 21 illustrates, in schematic form, the PN+1, MUX and PN register used in the CBuC of FIGS. 12A-12C.

FIG. 22 illustrates, in schematic form, the break-pt register used in the CBuC of FIGS. 12A-12C.

FIGS. 23A and 23B illustrate, in schematic form, the instruction bus buffers used in the CBuC of FIGS. 12A-12C.

FIGS. 24A and 24B illustrate, in schematic form, the data bus buffers used in the CBuC of FIGS. 12A-12C.

FIGS. 25A-25C, assembled in accordance with the map of FIG. 25, illustrate, in schematic form, the state RAM, MUX and pre-instruction register used in the CBuC of FIGS. 12A-12C.

FIGS. 26A-26E, assembled in accordance with the map of FIG. 26, illustrate, in schematic form, the instruction decode and test used in the CBuC of FIGS. 12A-12C.

FIG. 27 illustrates, in schematic form, the field extract used in the CBuC of FIGS. 12A-12C.

FIGS. 28A and 28B illustrate, in schematic form, the ALU and shift used in the CBuC of FIGS. 12A-12C.

FIG. 29 illustrates, in schematic form, the CRC used in the CBuC of FIGS. 12A-12C.

FIGS. 30A and 30B illustrate, in schematic form, the condition code used in the CBuC of FIGS. 12A-12C.

FIGS. 31A-31C, assembled in accordance with the map of FIG. 31, illustrate, in schematic form, the memory address register used in the CBuC of FIGS. 12A-12C.

FIGS. 32A and 32B illustrate, in schematic form, the memory data register used in the CBuC of FIGS. 12A-12C.

FIGS. 33A and 33B illustrate, in schematic form, the general register RAM used in the CBuC of FIGS. 12A-12C.

FIG. 34 illustrates, in schematic form, the auxiliary RAM used in the CBuC of FIGS. 12A-12C.

FIG. 35 illustrates, in schematic form, the default line number register used in the CBuC of FIGS. 12A-12C.

FIG. 36 illustrates, in schematic form, the address detection logic used in the CBuC of FIGS. 12A-12C.

FIGS. 37A-37D assembled in accordance with the map of FIG. 37, illustrate, in block diagram form, the communications processor interface (CPIF) shown as block 500 in FIG. 1.

FIG. 38 illustrates, in schematic form, the address latch 510 used in the CPIF of FIGS. 37A-37D.

FIG. 39 illustrates, in schematic form, the 64.times.8 dual port RAM used in the CPIF of FIGS. 37A-37D.

FIGS. 40A-40C, assembled in accordance with the map of FIG. 40, illustrate, in schematic form, the utility registers used in the CPIF of FIGS. 37A-37D.

FIGS. 41A and 41B illustrate, in schematic form, the request FIFO used in the CPIF of FIGS. 37A-37D.

FIG. 42 illustrates, in schematic form, the timing chain used in the CPIF of FIGS. 37A-37D.

FIGS. 43A-43E, assembled in accordance with the map of FIG. 43 illustrate, in schematic form, a first portion of the I/O sequencer used in the CPIF of FIGS. 37A-37D.

FIGS. 44A-44C, assembled in accordance with the map of FIG. 44 illustrate, in schematic form, a second portion of the I/O sequencer used in the CPIF of FIGS. 37A-37D.

FIGS. 45A-45D, assembled in accordance with the map of FIG. 45 illustrate, in schematic form, the inbound interface registers used in the CPIF of FIGS. 37A-37D.

FIGS. 46A-46D, assembled in accordance with the map of FIG. 46 illustrate, in schematic form, the outbound interface registers used in the CPIF of FIGS. 37A-37D.

FIGS. 47A and 47B illustrate, in schematic form, the flag RAM used in the CPIF of FIGS. 37A-37D.

FIGS. 48A-48C illustrate waveforms associated with the operation of the system of FIG. 1 for timing, instruction memory, data bus, scanner bus and the line set interface bus, useful for an understanding of the operation of the invention.

FIG. 49 illustrates processor interface timing waveforms useful for an understanding of the operation of the invention.

FIGS. 50-75 are flow charts depicting the sequences of software operation for the system of FIG. 1.

Referring to FIG. 1, a plurality of peripheral devices, PD0-PD7, are shown connected in pairs, by means of cables 10, to line set interface adapters 100A through 100D. Each line set interface adapter 100 is capable of supporting two peripheral devices, of differing protocols in a duplex mode. A line set interface bus 20 interconnects each of the line set interface adapters to a multiplexing character processor 120. A front-end (central) processor 140 is connected to the multiplexing character processor 120 via a central processor bus 130.

The multiplexing character processor 120 performs two primary functions, the first is to multiplex the data characters from the plurality of peripheral devices to the central processor bus 130, the second is to perform the assembly and the disassembly of data characters from and to the serial bit stream communicating with the peripheral devices.

The multiplexing character processor 120 is comprised of: a data bit synchronizer (DBS) 300, which performs input bit detection, output bit synchronization, interface signal monitoring, and baud rate clock generation for up to eight differing rate lines; a data RAM 400, which may be a 4K byte RAM for holding operand vectors (starting points); a communication processor interface (CPIF) 500, which contains transfer registers and command/data buffers for interfacing to the front-end processor 140; an instruction RAM/ROM 600 which is 16-bits wide, with an additional 2 parity bits (one for each 8-bit field or instruction byte); and a communications base microcontroller (CBuC ) 700 for multiplexing and using hardware dispatch software, via vectors, such that the protocol functions and character assembly/disassembly is performed under program control. The CBuC 700 also provides counter and timing outputs to other components of the processor 120. The CBuC 700 is comprised of a program control (PC) 70, real time clock and interval timers circuit (RTC) 80, a scan list and direction unit 90, and an instruction execution unit (IEU) 110.

The scan list and direction unit 90 determines the line address and the direction of the next line scan, that is, whether the next machine cycle is input processing or output processing. The scan list contains the order in which the line sets and the multiplexing character processor are time division multiplexed.

The PC control 70 contains thirty-three program counters (to be described later), which are multiplexed to the instruction RAM/ROM 600 under control of the scan list 90. Of the thirty-three counters, four are dedicated to each communication line to store the state of the input character assembly, the input protocol handler, the output character disassembly, and the output protocol handling routine. The PC control 70 operates from signals received from the IEU 110 to select a pointer (address to the vector) to the next program control.

In the present embodiment, the address of the vector is called a pointer and the vector determines the address of the instruction. The RTC timers 80, provide two interval timing signals for each line set and an RTC signal. One internal timing signal is for input timing and the other is for output timing. The RTC signals are used by the software to keep its time.

The IEU 110 is a pipeline processor which utilizes independent instructions and operand memory buses. The IEU 110 executes from a 16-bit instruction word which is fetched during the machine cycle preceding the execution cycle. A bi-directional bus, T, interconnects the IEU 110 to the PC control 70. The IEU 110 uses the T-bus to transfer operand end results between the IEU and the PC control 70. The IEU 110 is time sliced under scan list control to give the appearance of seventeen independent processors.

Multiple cycle instructions are suspended after each machine cycle until the next execution cycle for that same program counter. Each slot in the scan list corresponds to one execution cycle. Intermediate results are stored in an auxiliary register (to be described later). The instruction word and cycle count for multi-cycle instructions is stored in a state register (to be described later). One auxiliary and one state register exist for each general register set.

A data bus E, connects the IEU 110 to the PC control 70, scan list 90, the RTC timers 80, and the data bus D.

The signal flow, from the front-end processor 140 to the multiplexing character processor 120 and the peripheral devices, is defined as being the outbound signal flow. The signal flow, from the peripheral devices towards the multiplexing character processor 120 and the front-end processor 140 is defined as being the inbound signal flow.

The main function of the aforementioned system is to provide a non-prioritized communication capability between various types of peripheral devices, possibly having different protocol features, and the front-end processor. An additional function of the aforementioned system is to provide a pipeline operation which is not branch instruction sensitive.

Referring to FIGS. 2A-2C, assembled in accordance with the map of FIG. 2, one-half of a line set interface adapter 100 is shown configured to support the physical layer defined by an RS232C protocol. Interface adapters responsive to different protocols may also be used as one or more of the line set interface adapters 100A-100D using the present teaching. The line set interface adapters are provided with three input/output terminals labeled generically, A-In, A-Out and C. Terminal C is connected to the bus 20 and terminals A-In and A-Out are connected to the respective peripheral device PD. The line set adapter consists of substantially two identical circuit portions, an A portion for handling the peripheral device attached to terminal A, and a B portion for handling the peripheral device attached to terminal B. In FIGS. 2A-2C, the A portion of the interface adapter needed to service the peripheral device connected to the A terminal is shown in detail. The bus 20, connected between the DBS 300 and the input labeled C on the line set interface adapter, is comprised of sixteen conductors. The terminal A-In is comprised of ten conductors for handling the signal flow from the peripheral device to the interface adapter and the terminal A-Out is comprised of nine conductors for handling the signal flow from the interface adapter to the peripheral device.

The protocol of the peripheral device dictates which conductors of the input and the output are to receive and/or transmit specific signals. A plurality of line receivers 30 are interposed in each of the ten conductors comprising the A-In terminal. The line receivers 30 may each be a FAIRCHILD 1489 chip. A latching and decoding circuit 40 (shown in detail in FIGS. 3A-3D) receives the signals from the line receivers 30 and directs those signals out the C terminals onto the bus 20. Signals received on the C terminals are processed through the latching and decoding circuit 40 and are directed to the peripheral device via a set of line drivers 50. Each line driver, in the preferred embodiment, is a Motorola 1488L chip specifically adapted for handling four lines with the RS232C protocol. As previously stated, each interface adapter has an A portion and a B portion. The B portion of the interface circuitry is identical to that shown in FIGS. 2A-2C, except that terminal 18 of the decoding circuit 40 is held at a logic level "0" by being held to ground instead of being held at a logic level "1" by being connected to a +5 volt source.

Referring to FIGS. 3A-3D, assembled in accordance with the map of FIG. 3, the latching and decoding circuit 40 is shown in logic circuit detail in FIGS. 3A-3D. The input pin numbers correspond to like numbers appearing in FIGS. 2A-2C. Pin numbers 6-15 are connected to a plurality of tri-state amplifiers 60, for amplifying their respective input signals and for providing at their outputs, signals which are directed to the D inputs of a plurality of D-type flip-flops 61. The peripheral device connected to the A terminal is selected by applying address signals to the address terminals numbered 16 and 17. The input address terminal 18, for the A portion, is held at a logic level "1", as previously explained. The address signals are directed to the inputs of amplifiers 63 and from there to two sets of gates 64 and 66. The group of gates 64 are further connected to receive at their inputs the Q output signals of a group of three D-type latches 75A. The D inputs of the latches are connected, via amplifiers 60, to the pins 10-12. The gates 64 compare the Line Address asserted by pins 16-18 to the Read Address stored in the latches 75A. If the Line Address and Read Address are equal, the gates 64 will enable gates 62. Pin 5 receives a READ ENABLE signal which is also directed to the inputs of the group of gates 62 to provide at the two outputs of the gate group 62 enabling signals. One enabling signal is applied to the tri-state enable input of the bi-directional amplifiers 60, connected to pins 6-10, and the other enabling signal is applied to the tri-state enable input of the bi-directional amplifiers 60, connected to pins 11-15. The group of gates 64 are further connected to receive at their inputs the output signals, at the Q outputs, of a first group of three D-type latches 75A. The D-inputs of the latches 75A are connected, via amplifiers 60, to pins 10-12. A second group of three D-type latches 75B have their D inputs connected, via amplifiers 60, to pins 13-15. The Q outputs of the second group of latches 75B are connected to the inputs of the group of gates 66. The gates 66 compare the Line Address asserted by pins 16-18 to the Write Address stored in latches 75B. If the Line Address and Write Address are equal, the gates 66 will enable the clock inputs of the bank of flip-flops 61 upon the occurrence of the Data Strobe signal generated by the gates 78. With proper gate selection, the signals present on the pins 6 and 8-15 are gated to the output pins 31-38.

Data coming from the peripheral device is received on pins 21-30. A bank of amplifiers 72 restore the received signals to binary signal levels sufficient to drive logic circuitry. The restored signals are directed to a bank of D-type flip-flops 74 which operate as a latch to hold the signals received from amplifiers 72 for one clock period. The flip-flops 74 provide resynchronization of the input signals from the peripheral devices. A sufficient time delay is provided from the clocking of the flip-flops 74 to the access by the Multiplexing Character Processor logic, such that the probability of failure due to a metastable condition is acceptably low. The clocking signal AS/DS for the flip-flops 74 is generated by the group of gates 78. The signals latched into the flip-flops 74, when read out, are directed to a bank of 2-to-1 multiplexers 76. The output signals, from the multiplexers 76, are labeled LSIF0 through LSIF9 and are directed to the like-labeled conductors connected to the inputs of a bank of bi-directional amplifiers 60. When properly enabled, signals present on pins 21-30 will be directed to pins 6-15 and in turn to the parallel bus 20.

Set forth below, is a listing of the pin numbers for latching and decoding circuit 40, the name of the signals appearing on the pins and a short description of the function of the signals.

In operation, the lineset interface bus 20 is a time multiplexed bus operating in three cycles: an address cycle, an output cycle, and an input cycle (output is defined as a flow towards the communications line). During the address cycle, the read address is sent on pins 10-12 and the write address is sent on pins 13-15. The address data is latched on AS/DS. The address line set interface adapter is determined by the state of the signals on pins 16-18. During the output cycle, if the write address is equal to the line set interface adapter address, the data present on the lineset interface bus will be latched on AS/DS. The output data will be presented at the output interface if SNF/ASYN was a logic "1" during the output cycle. If SNF/ASYN was a logic "0" during the output cycle, then the new output data bit will not be presented to the output interface until the high-to-low transition of Transmit Clock (TC/). During the input cycle, if the read address is equal to the line set interface adapter address, the lineset interface bus will transmit to the multiplexing character processor while the RE signal is a logic "1".

Referring to FIGS. 4A-4L, assembled in accordance with the map of FIG. 4, the multiplexing character processor 120 is shown in integrated circuit (IC) chip schematic form with each of the major numbered blocks, shown with dotted lines therearound, corresponding to the like numbered blocks of FIG. 1. The multiplexing character processor 120 is comprised of three custom IC chips, 502, 302 and 700, with the remaining IC chips being commercially available and identified with industry-standard part numbers.

The Instruction RAM/ROM 600 is a 16-bit wide memory consisting of three 8K words by 8-bits of ultra-violet erasable PROMs 608, 610 and 612. The programming of these PROMs is set forth in Appendix A. Additionally, there is provided three 8K words by 8-bits of static RAMs, 614, 616 and 618. The PROMs used in the preferred embodiment are type 2764 chips manufactured by INTEL, and the RAMs used are HM6264P-15 chips manufactured by HITACHI. The instruction memory 600 in addition to being 16-bits wide is provided with a parity bit for each instruction byte. A programmable array logic unit PAL 606 selects either the PROMs or RAMs as the source/destination of the instruction bus based on the instruction address stored in the latches 602 and 604. The PROM address range is 0000-1FFF in hexadecimal notation. The RAM address range is 2000-3FFF in hexadecimal notation. The PAL 606 and a PAL 410 are PAL 16L8 AND-OR-INVERT gate array chips, of the type manufactured by Monolithic Memories.

The Boolean expressions, using the operators: for the Boolean product, + for the Boolean sum, and / for the Boolean invert; for the PALS 410 and 606 are as follows:

The RAM chips are selected by receiving a low signal at their chip select inputs CS (pin 20) which signal emanates at pin 12 of PAL 606. The PROMs are selected by receiving a low signal on their inputs CS (pin 20) which signal emanates at pin 13 of PAL 606. Additionally, PAL 606 will enable the Invalid Instruction Address signal (IIA) on pin 19 when the instruction address exceeds the hexadecimal value 3FFF. The Boolean expressions for PAL 414 are as follows:

Two 8-bit transparent latches 602 and 604 each receive 8-bits of instruction address from the I-bus and latch that address upon the occurrence of an enabling high signal on their CP inputs (pin 11). (Shown in the timing diagram in FIG. 48A). Upon being latched into the latches, the data is available at the output pins 2, 5, 6, 9, 12, 15, 16 and 19. The output of the latches are held non-tri-state because the OE inputs (pin 1) are strapped low. The high enabling signal, applied to the CP inputs, is generated by the CBuC chip 700 and is provided at the output labeled IALE (pin 66) which is an abbreviation for instruction address latch enable. The input pin 27 labeled PGM for PROMs 608, 610 and 612, and the input pin 26 labeled CS2 for RAMs 614, 616 and 618 are all maintained at a high level by a connection through a 1K ohm resistor, 619, to a +5 volt potential source. Two signals, Instruction Output Enable/ (IOE/) and Instruction Write Enable/ (IWE/) are generated by the CBuC to control reading and writing instructions to/from the I-bus.

The Data RAM 400 is comprised of four interconnected RAM units 408, 412, 416 and 418. RAMs 408 and 412 provide 8-bits of a 16-bit output with RAMs 416 and 418 providing the remaining 8-bits. The RAMs are HM6116P-2 chips manufactured by HITACHI and are each organized as 2K words by 8-bits. The 16-bit output from these RAMs is directed to the D-bus which interconnects the CPIF 500, the DBS 300, and the CBuC 700. The data RAM 400 is further organized with an even parity bit for each data byte. The data RAM is byte (8-bit) or 16-bit addressable. The least significant byte will reside at an even memory address and the most significant byte of a 16-bit word will reside at an odd memory address. Latches 404 and 406 are each connected to receive 8-bits of address information from the D-bus and operate to latch that information to their respective outputs under control of the data address enable signal. The four high order bits, from the output of latch 404, and the least significant bit of latch 406 are directed to a PAL 410. The PAL 410 also receives three additional inputs from the CBuC 700 on the input pins numbered 8, 9 and 11. These signals, Data Output Enable (DOE/), Data Write Enable (DWE/) and 8/16B control the timing of data transfer to/from the D-bus (see the data bus timing diagram and FIG. 48B). The PAL 410 determines if the data address latched into the latches 404 and 406 is in the range allocated to the data RAMs 412 and 416; or the line number register 402; or the interrupt register PAL 414. The data RAMs are allocated data addresses 0000 through 0FFF in hexadecimal notation. If the data address is not in the range allocated to any of the devices connected to the D-bus, the signal Invalid Data Address (IDA) is made active on output pin 12 of PAL 410. PAL 410 enables the tri-state drivers on its output pins 13-14, and enables the tri-state drivers of PAL 414 when the four high order bits of the data address are all high and the control signal DOE/ is low. PAL 410 resets the register contained in PAL 414 when the four high order bits of the data address are all high and the control signal DWE/ is low. The PAL 414 generates an interrupt signal to the Instruction Execution Unit of the CBuC 700 when one or more of the error or initialization signals are active. The error signals consist of the invalid instruction address generated by the invalid data address generated by PAL 410. The initialization signals consist of Channel Reset (CR/) and Master Reset (MR/) inputted via connector 130, and Force Load (FL/) generated by the CPIF 502. There are 4-bits of addressing data sent to the transparent latch 402, 2-bits of the addressing data come from the latch 406 and the other 2-bits come from the latch 404. These four address bits comprise the line address field of the data address when an instruction utilizing the line space addressing mode (described later) is executed by the CBuC 700. The enablement of latch 402 onto the data bus D8-D15 is achieved under control of the signal emanating from PAL 410, output pin 18. Four inputs (pins 13, 14, 17 and 18) to the latch 402 are strapped to ground. PAL 414 is of the type PAL 16R6 manufactured by Monolithic Memories.

The Communication Processor Interface (CPIF) 500 includes the CPIF chip 502 which is connected to the scanner bus on pins numbered 5-9. The D-Bus is connected to the CPIF chip 502 at the pins numbered 12-24. The front-end processor 140 is connected to the CPIF chip 502 via nine conductors of bus 130. One conductor is dedicated as a parity bit line with the remaining eight conductors being used to transmit 8-bits of data in a bi-directional mode. Two octal bi-directional bus interfaces 506 and 508 control the transmission direction, either in bound or out bound, between the CPIF chip 502 and the front-end processor 140 in response to the signals CB SEL and CB READ applied to their EN and S/R inputs, respectively. The parity bit is supplied to the CPIF chip 502 at the pin numbered 29. The remaining 8-bits of data are supplied to the CPIF chip 502 at the pins numbered 30-37. The input of a hex inverter 504 is connected to pin 4 of the CPIF chip 502 and provides at its output the signal designated REQUEST/.

The Data Bit Synchronizer (DBS) 300 includes the DBS chip 302 which is connected to the scanner bus at the pins numbered 1-7. The bus 20 is interfaced to the DBS chip 302 by a pair of octal bi-directional bus interfaces 304 and 306. In the preferred embodiment of the invention interface chips 304, 306, 506 and 508 are 74LS245 chips.

A hex inverter 308 has its inputs connected to pins 25-27 of the DBS chip 302 to provide at its output the signals designated Read Enable (RE), SNF/ASYN and AS/DS which signals are directed over bus 20 to the line set interfaces 100 (See FIG. 2A).

Referring now to FIGS. 5A-5M, assembled in accordance with the map of FIG. 5, the DBS chip 302 is shown in block diagram form with the pin numbering corresponding to like numbered pins shown in FIGS. 4E and 4J. The DBS chip performs input data detection, output data bit synchronization, interface control signal monitoring and baud rate clock generation for up to eight full duplex communication lines.

The major elements of the DBS are control/status dual port RAM 315, bit rate clock generator 326, input data control logic 328, output data control logic 330, interface signal comparator 334, flag RAM 340 and, timing chain 324.

The dual port RAM 315 consists of eight 72-bit words which contain the control and status information of each of the communications lines. The bit rate clock generator, input data control logic, output data control logic, and interface signal comparator are time multiplexed to control the eight communication lines. The flag RAM 340 is used to buffer flags to be presented on the scanner bus.

The DBS chip 302 interfaces to the communications base microcontroller chip 700 (CBuC) via the D-bus and the scanner bus. The D-bus accesses the control/ status dual port RAM 315; allowing the CBuC to configure the protocol and line speed parameters, and access the input and output interface control signals. The scanner (flag) bus is used by the CBuC to solicit flags (i.e. Bit Request, Line Signal Detect) from the DBS chip 302. The sequence in which the CBuC scans lines on the scanner bus determines the sequence in which the DBS scans the communications lines on the line set interface bus 20. The DBS performs a full duplex scan; whereas the CBuC performs a half duplex scan. This feature allows the CBuC to be configured such that the scan rate of the line is twice the processing rate in the CBuC. The DBS connects up to eight line set interface circuits via the line set interface bus 20.

The system clock rate of 8.2944 megahertz is divided into a six-phase timing chain which yields a 723.4 nanosecond machine cycle. A scan may be performed during each cycle. The scanner bus is time sliced into two phases (see the timing diagram of FIG. 48C). The CBuC presents the line number to be scanned on the scanner bus and strobes it to the DBS with a Line Number Valid (LNV) signal. The DBS reads the pending flags for the specified line number from the flag RAM 340 and presents the flags on the scanner bus during the time slot allocated for flag access. The line number is used as a scan address on the line set interface bus and is used to address the 72-bit word from the control/status dual port RAM. The 72-bit word contains the control and previous state of the hardware sequencers for the communications line. The previous state (from the RAM) and current state (from the line set interface) is propagated through the sequencers. The result is the next state which is stored back in the RAM and the next flags which are stored in the flag RAM.

The timing chain internally generates twelve phases of the 8.2944 megahertz system clock. The clock phases, labeled MT1A-MT6B are shown in the timing diagram of FIG. 6. The MT1A, MT2A, . . . MT6A phases are the outputs of a shift register (not shown) which is clocked on the falling edge of the system clock. The MT1A, MT2A, . . . MT6A phases correspond to the MT1-MT6 timing chain contained in the CBuC. The MT1B, MT2B, . . . MT6B phases are the outputs of a shift register which is clocked on the rising edge of the system clock. The Data Address Latch Enable (DALE) signal is inputted to the DBS timing chain so that it is synchronized to the timing chain in the CBuC. The DALE signal nominally occurs at the MT4 phase of the CBuC. The DALE signal is latched by the DBS on the rising edge of the system clock to generate the MT4B phase. The MT4B signal is latched on the falling edge of the system clock to generate the MT5A phase, and so on. The DALE signal is generated by the CBuC every MT4 so that the timing chain runs continuously.

Logical combinations of the timing phases provide time elements for the control signals which are outputted from the timing chain 324. The control signals are defined by the following logic equations and are illustrated in the timing diagram of FIGS. 7A and 7B.

The control/status RAM consists of nine 8.times.8 pseudo dual port RAMs 314 and two address decode circuits 362. Write driver and sense amps are provided for both the A port and the B port. The address decode and bit lines are time shared between the A and B ports. A block schematic of the 8.times.8 RAM 314 with address decode 362 is shown in FIGS. 8A and 8B.

The RAM 314 is comprised of a matrix of 64-bit cells 360. One bit cell 360 is shown in detail in FIG. 9, comprised of cross-coupled inverter pairs 3601 with a field effect transistor connected to each inverter output. The gates of the field effect transistors are connected to receive an enable bit X from the address decode circuit 362 of FIGS. 8A and 8B and one electrode from each of the field effect transistors is connected to receive the signals on the conductors T and F, respectively, from a sense amplifier and bit driver circuit 364. The circuit 364 is shown in detail in FIG. 10 comprised of cross-coupled sense amplifiers 3641 for performing a latching function, drivers 3642, a pair of NOR gates 3643, and FET pairs 3644 and 3645. When the SEL and RD signals are active, the sense amplifier 3641 and the driver 3642 are connected to the RAM bit cells 360 by means of the conductors labeled T and F and data, D-OUT, is read out. When the SEL signal is active and when the signal WE/ is active, the signal D-IN is applied to the bit cell 360 over the conductors T and F. FIG. 11 illustrates, in logic diagram form, the address decoder 362. The decoder 362 functions to transform the DA signals 6, 7 and 8 to one of the row select signals X.sub.0 through X.sub.7.

The B port data input and output signal names are summarized in the following chart:

The function of the address detection and byte select logic 312 is to map the addresses of the control/status RAM into the control linespace address space of the data bus at offsets 10-18. The actual data address is formed by concatenation 1XXXX0111Xdddddd, where 111 is the line number, dddddd is the linespace offset, and XXXX are indeterminate (don't care). The address detection logic determines if the address is in the range allocated to the DBS. The byte select logic enables the byte specified by the linespace offset.

B10SEL-B18SEL are the A port select lines to the 8.times.8 RAMs which comprise the control/status RAM. The numbers 10-18, within the RAM blocks correspond to the B numbered SELECT signal received by that RAM. To simplify the specification and to limit the number of detailed drawings, the Boolean logic expressions corresponding to the logic functions performed by various blocks of the DBS 302 will be set forth hereinafter. Any person skilled in this art will be able to replicate the logic circuitry for performing the given Boolean expressions.

The bit clock generator 326 generates timing signals corresponding to the output data rate. Alternately, timing signals can be gated to the lineset interface bus 20 for locally clocked synchronous applications. The bit clock generator range varies by data rate due to the variable number of samples per bit time. The bit clock generator directs its outputs OC0-0C5 and LC to the byte 18 RAM 314 for storage at offset 18, bits 0-5. The bit clock count range, as a function of output data rate, is given in the following table.

The inputs, outputs and logic expression which define the bit clock generator 326 are as follows:

The input data control logic 328 controls the input state counter 336 and generates the Input Bit Request and Input Data Bit signals which are transferred to the CBuC 700 via the flag RAM 340. The input data control logic is driven from the control and status information stored in the control/status RAM 315, and from the Receive Clock and Input Interface Signal 7 scanned on the line set interface bus 20. Definitions of the inputs and outputs of the input control logic are as follows:

The input state counter is a 5-bit synchronous counter. The counter can be synchronously reset or preset to a value of two. The counter increments on each occurrence of both the CLK signal high and the Enable Count signal high. The Reset Count signal overrides the Enable Count signal. The Preset Count signal has effect only when the Reset Count is active and acts to reset the counter to a value of two rather than zero. The Preset Count and Reset Count only have effect when the CLK signal is high. The input state counter has no storage elements since the input state count resides in the RAM 315 at offset 16, bits 0-4. The inputs, outputs and Boolean logic equations for the input state counter are as follows:

The output data control logic 330 synchronizes the output data bits to the TR CLK signal when in the synchronous mode or to the CLK signal when in the asynchronous mode. Edge noise is filtered from the TR CLK signal to prevent inadvertent transitions which will cause synchronization failure. The inputs, outputs, and Boolean logic expressions for the output data control logic 330 are as follows:

The clock divider 332 consists of an 11-bit ripple counter (not shown) which increments on the falling edge of MT1B. The outputs of the counter are inputted to the 16-to-1 multiplexer selectors 356 and 357 which generate the Input Timing (IT) and Output Timing (OT) signals. The outputs of the counter are labeled 2X, 4X, 8X, . . . 2048X; representative of the decimal multiplier of the machine cycle time period. The bit rate selects contained in Byte 11 of the RAM 315 are used to control the multiplexers. The clock divider output, selected as a function of bit rate clock selects, is given in the following table.

The IT signal is one-half the frequency of the required scan rate for a given frequency. A scan is performed on both the rising and falling transition of the IT signal. This feature allows the CBuC to scan the DBS at the minimum rate required to reconstruct the input data from a serial data signal.

The interface control signal comparator 334 monitors the input interface signals for coincidence with the Input Interface Condition specified in Byte 13 of the RAM 315. A bit-by-bit comparison is made between the input interface condition byte and the input interface signals. If any of the coincident bit pairs also have the corresponding bit set in the Interface Signal Mask byte (Byte 12), the Line Signal Detect signal will be made active to the flag RAM 340. The bit position(s) in the Interface Signal Mask byte which caused the Line Signal Detect are cleared by the interface control signal comparator 334. The inputs, outputs and the Boolean logic expressions are given in the following tables.

The flag RAM 340 is an 8.times.6 pseudo dual-port RAM used to buffer the Bit Request (BR), Data Bit (DB) and Line Signal Detect (LS DETECT) flags for access by the CBuC. The dual-port RAM is functionally equivalent to the 8.times.8 RAMs 314 which comprise the control/status RAM 315 with the addition of reset circuitry in the address decode logic 342. The flag enable logic 358 sets bits in the flag RAM 340 designating the occurrence of an Output Bit Request (OBR), Input Bit Request (IBR), or Line Signal Detect (LS DETECT) signal. The NRZI decoded state of the Input Data Bit (IDB) corresponding to the Input Bit Request is stored in the flag RAM 340. The previous state of the Output Data Bit (ODB) is stored in the flag RAM 340 upon occurrence of an Output Bit Request. The Line Signal Detect signal is stored in 2-bit positions within the flag RAM 340 so that it can be accessed on both the input and output scans by the CBuC. The flag read logic 350 clears the bits in the flag RAM 340 when they have been accessed by the CBuC via the scanner bus. The line address driven on the scanner bus (pins 2-4) is latched on the trailing edge of the LNV/strobe (pin 1). The outputs of the latch are used as the "B" port address for the read-modify-write operation performed by the flag read logic 350. The flag read logic 350 presents the state of the bit request, data bit, and line signal detent flags selected by the line address and scan direction. Any active flags presented to the scanner bus are cleared in the "B" port write operation. The "B" port address is latched and delayed until the completion of the line scan so that the next state of the flags, may be set by the flag enable logic 358. The flag enable logic 358 sets flags, while retaining pending flags, by performing a read-modify-write operation to the "A" port of the flag RAM 340.

The line set interface bus 20 is time sliced into three phases; line address, output data, and input data. During the line address phase, two 3-bit addresses are propagated onto the line set interface bus. One address (WA0-WA2) designates the line set interface which is the destination of the data during the output data phase. The other address (SA0-SA2) specifies the line set interface adapter which is the source of the data during the input data phase of the bus. The rising edge of the Address/Date Strobe (AS/DS) designates valid signals on the line set interface bus. The first low-to-high transition of AS/DS following the high-to-low transition of the Read Enable (RE) signal designates the line address is valid on the line set interface bus. The second rising transition of AS/DS following the falling of RE designates that the output data is valid on the line set interface bus.

Referring to FIGS. 12A-12C, wherein is shown in block diagram form the CBuC 700 chip. The CBuC 700 is shown comprised of major blocks whose dotted outline corresponds to the blocks of FIG. 1. The I-Bus is coupled to the instruction RAM/ROM 600 by means of an instruction bus buffer 712. The E-bus is coupled to the data bit synchronizer 300, data RAM 400 and communication processor interface 500 by means of data bus buffer 714. Positioned on the microcontroller chip is a timing chain 716 which provides as outputs timing signals MT1-MT6, PHASE 1, and PHASE 2, all derived from the signal, CLK. The timing chain 716 is shown in schematic block diagram form in FIG. 13. Each of the blocks associated with FIGS. 12A-12C will be described and shown with output ports and input ports labeled with the signals carried thereon and will have in parentheses the number of the drawing FIG. wherein the associated signals are connected. For example, in FIG. 13 the MT-RST signal applied to the RST input to the 6-bit shift register 7163 comes from a source which is shown in FIG. 15.

Referring now to the circuitry of 716, an input latching circuit 7161 receives on its input pin 60, the signal CLK and provides at its output two complimentary clock signals denoted P1 and P2. These signals are employed as inputs to a two-phase, underlapped, clock generator 7162 and to a 6-bit shift register 7163. The clock generator 7162 provides as its outputs two phase related signals denoted PHASE 1 and PHASE 2. The 6-bit output from shift register 7163 is denoted MT1-MT6. The signals MT1-MT6 are mutually exclusive phases of the timing chain. The signals MT1-MT5 are connected as inputs to a NOR gate 7164. The NOR gate enables the shift input of the 6-bit shift register 7163 when outputs MT1-MT5 are all low. In this manner, the timing chain will initiate with pulse MT1 and continuously cycle from MT1 through MT6 when the MT-RST is inactive.

Referring now to FIGS. 14A-14D, assembled in accordance with the map of FIG. 14 wherein is disclosed the flags logic 722. The flags logic 722 is comprised of six amplifiers 7221, each connected respectively to pins 20-25 for receiving the designated signals and for providing those signals to a corresponding number of AND gates 7222. The outputs of the AND gates are directed to a 7-bit latch 7223. The 7-bit latch also receives as inputs the TIMER EXP signal and the MT1 signal. The AND gates 7222 each receives as an enabling input the signal LNA-B from a 5-bit latch 7190. The output signals from the 7-bit latch 7223 are directed to the inputs of a vector encoding logic block 730 (FIG. 19A).

The scan/direction logic 718 is shown comprised of a 4-bit binary up counter 7181 for receiving on its inputs the signal MT6 and for providing at its output signals to a 4-bit multiplexer 7182 and an AND gate 7199. The AND gate outputs the signal RTC CLK. The 4-bit signal from the multiplexing latch 7182 is directed as the address signal to a scan list RAM 7183 such that the signals at the address input are cycled to scan the table stored in the RAM in a sequential cyclical order. The address of a corresponding peripheral device appears at the scan list RAM output labeled Q0-3. Those signals are directed to a 4-bit latch 7184 and to a tri-state device interposed between the scan list RAM and the E-bus. These tri-state gates along with multiplexer 7182 provide read and write access to the scan list RAM from the instruction execution unit 110. Software programs have the ability to inspect and change the contents of the scan list RAM via execution of load or store instructions to the hexadecimal data memory addresses 8400 through 840F. Data addresses within this range will cause activation of the signal SCAN LIST SEL to gates 7187 and 7188, from the address detection logic 764. The gates 7187 and 7188 will either enable tri-state gates or the write enable (WE) of the scan list RAM on occurrence of either the RD signal or WR signal, respectively. The definition of the bit positions of the scan list RAM as seen by the program registers, is as follows:

LNA, when set, designates the 3-bit field LN0-LN2 is an active line address. LN0-LN2 is a 3-bit address selecting one of eight peripheral devices (PD0-PD7). The resetting of bits 0-3 of the scan list RAM is accomplished by the tri-state gates with their inputs tied to circuit ground.

A 3-bit multiplexer latch 7185 receives the three line address bits (LN0-LN2) from the 4-bit latch 7184 and three address bits, E ADDR 6-8; and, under control of the clocking signals MT2 and MT5, outputs one of the group of bits to the address inputs of direction list RAM 7186. The direction list RAM output bits are available at the output Q0-3 and are directed to the input of the 8-bit latch 7190. The direction list RAM outputs are also connected to tri-state gates which in turn are connected to the E-bus at bit positions 8 and 12-14. These tri-state gates along with multiplexer 7189 provide read and write access to the direction list RAM from the instruction execution unit 110. Software programs have the ability to inspect and change the contents of the direction list RAM via execution of load and store instructions to the data memory address 100000LLLX000010 in binary format. The three bit field, LLL, designates the line address of the peripheral devices PD0-PD7, while X designates a "don't care" condition. Data memory addresses within this address range will cause activation of the DIR LIST SEL by the address detection logic 764. The gates 7189, 7197, and 7198 will either enable the outputs of the tri-state gates to the E-bus, or enable the write enable input (WE) to the direction list RAM, dependent on the RD or WR signals, respectively. The definition of the bit positions of the direction list RAM, is as follows:

LN3 is the direction of the next line scan. LN3, when set, designates the next scan will be output. IA enables scans in the input direction. OA enables scans of the output direction. FDX enables alternating scans in the input and output directions. The resetting of bits 1-3 and 7 of the scan list RAM is accomplished by the tri-state gates connected to E-bus bits 9-11 and 15.

Five bits from the output of the 8-bit latch 7190 are directed to a next direction PLA 7192 when latched by the signal MT3. The logical function of the next direction PLA is defined by the following logic expressions:

The next direction PLA 7192 provides a 4-bit output which is directed to one set of inputs to a 4-bit multiplexing latch 7189. The other set of inputs are the E-bus bits 12-15. The output of the 4-bit multiplexing latch 7189 is directed to the data input terminal labeled D0-3 of the direction list RAM 7186 under control of the clocking signal MT4 and the signals DIR LIST SEL and WR that are ANDed by an AND gate 7197. A 4-bit comparator 7191 compares the LN0A-LN3A bits present at the output of the 8-bit latch 7190 with four of the bits received from a 5-bit latch 7194 and upon achieving coincidence the comparator provides an output signal which is directed to the inputs of a NAND gate 7195, the output of which is connected to an input of an AND gate 7196. The gates 7191, and 7195 will disable gate 7196 when the signals LN0A-LN3A equal the same signals during the previous scan cycle. The signal SLE generated by the control register 719 enables gate 7196.

A 5-bit latch 7193 stores the one bit from the AND gate 7196 and the four bits LN0A-LN3A upon enablement by the clocking signal MT4. The outputs from the 5-bit latch 7193 are directed to the inputs of the 5-bit latch 7194 which is latched by the signal MT6. The output signals from the 5-bit latch 7194 are directed back to the input to the 4-bit comparator 7191 with 1-bit from the 5-bit latch being directed to the input of the NAND gate 7195.

An AND gate 7188, responsive to the signal WR and the signal SCAN LIST SEL, provides as its output a write enable signal to the WE terminal of the scan list RAM 7183. The AND gate 7187, responsive to the signal SCAN LIST SEL and the signal RD provides as its output the enabling signal to the tri-state amplifier pair connected to the Q0-3 output of 7183 and to ground. The AND gate 7189, responsive to the signals on its inputs provides the enabling signal to the tri-state amplifier pair connected to the Q0-3 output of the direction list RAM 7186. The WE signal applied to the direction list RAM 7186 is derived from the signal MT4 and the output from the AND gate 7197 by an OR circuit 7198.

The flag solicitation logic 720 is shown comprised of a latch 7201 which receives at its S and R inputs the clocking signals MT3 and MT6, respectively. The latch output signal acts as the enabling signal to the four tri-state amplifiers denoted generally as 7202. The signals LN0A-LN3A, are directed to the like labeled inputs to the tri-state devices and are passed, upon enablement, to the pins labeled 30-33, respectively.

Referring to FIGS. 15A-15D assembled in accordance with the map of FIG. 15 wherein is illustrated the control register 719. The main function of the control register 719 is to resynchronize and store key interrupt and error conditions which disable normal program execution. The instruction execution unit 110 has access to the control register via the E-bus. Software programs have the ability to inspect and change the contents of the control register via execution of load or store instructions to the hexadecimal data memory address 84FF. The data address 84FF will activate the CNTL REG SEL by the address detection logic. The bit definition of the control register as seen by the program registers is as follows:

Where SLE, when set, enables vector dispatching by the program control logic. BPE enables interruption of the normal instruction execution when the BPDET signal is activated by the break point register 70. PEL, when clear, enables the interruption of the normal instruction execution upon activation of either DPE or IPE signals generated by the data parity logic 761 or the instruction parity logic 759. The BPD bit sets upon activation of the BPDET signal, conditioned with BPE signal. The INT signal sets upon activation of the INT/ signal on pin 58. The DPE and IPE bits set on detection of parity errors by the data parity logic and instruction parity logic, respectively. Clearing of the control register bits is accomplished by the appropriate instruction sequence executed by the instruction execution unit.

Four latches 800 receive E-bus bits 8-11 and latch the signals to their outputs when CNTL REG SEL, WR, L4F, and MT6 are all active. CNTL REG SEL, SR, L4F, and MT6 are ANDed together by the AND gate 810. The latches 800 are reset by activation of the R inputs by the RESET generated by the cross coupled latch 822B. The resetting signal RST/ is applied to a resynchronization circuit 822 which is comprised of cross-coupled (CC) latches 822A-822D. The latches 822A and 822B are latched with the RST/ signal by clock signals MT4 and MT2, respectively, to provide at the output of latch 822B the signal RESET. In a like manner, the INT/ signal is directed to a negative edge triggered D-type flip-flop, the output of which is connected to the cross-coupled latches 822C and 822D to provide an output signal to a latch 804B, which latch is part of a 4-bit latch group 804. The latch 804 are latched under control of the timing signal MT3. The outputs of the latch 804 are reset by the enabling of the R input by the RESET signal.

A group of tri-state amplifiers 802, enabled by the output signal from an AND gate 812, permits the signals stored in the latch group 800 to be directed onto the E-bus conductors 8-11. The output signals from the latch group 804 are directed individually to the inputs of the AND gate group 828A-828D. The other input to the AND gates is the signal from the logic gates 820 which signal is the logical combination of the signals present at the outputs of the SR flip-flop group 806 and the output of the latch connected to the E-bus 10 terminal.

A group of inverters 824A-824D are connected to the E-bus conductors 12-15 to couple the signals thereon to inputs of an AND gate group 826. The enabling input to the AND gate group 826 comes from the output of the AND gate 810. An OR gate group 827 receives the output from the AND gate group 826 along with the signal RESET and provides at its output the reset signal for the SR flip-flop group 806. The output signal from the AND gates 828A-828D are applied to the S inputs of corresponding flip-flops of the group 806. The output signals available on the Q terminals of the flip-flop group 806 are directed, as inputs, to the tri-state amplifiers group 808.

Referring to FIG. 16 wherein the real time clock 850 is shown in logic block form comprised of 8-bit counters 852A-C, AND gates 854, 856A-C, 860A-C and OR gates 862A and B. The 8-bit counters 852A-852C form a 24-bit counter which is utilized by the software programs for a time reference. The instruction execution unit is allowed read and write access to the real time clock counters at data memory addresses 8410-8412. Data addresses of 8410, 8411, 8412 will cause activation of the RTC0SEL, RTC1SEL, and RTC2SEL, respectively. The AND gates 856A-856C have their output terminals connected to the LOAD input of the 8-bit counters 852A-C, respectively, and their inputs connected to various labeled signals for controlling the loading operation of each of the counters. The AND gates 860A-860C provide the enabling signals for the tri-state amplifiers 864A-864C, respectively, so as to couple the output from the counters to the output of the tri-state amplifiers. The counters are clocked by the signals MT2 and RTC CLK directed to their CLK inputs by the AND gate 854. The carry signal from counter 852A is coupled to the CIN input of counter 862B by OR gate 862A and in a like manner, the carry signal from 862B is coupled to the CIN input of counter 852C by the OR gate 862B. One of the 8-bit counts, the next to least significant bits, from counter 852B is directed to an output as the signal INT CLK. The remaining outputs, dependent upon the activation of the tri-state gates, are directed onto the E-bus as bits 8-15.

Referring to FIGS. 17A and 17B wherein is shown the interval timer 870. The interval timer functions to store the maximum time periods permitted for an action by a particular protocol such that if the actin is not performed within the permitted time period, a TIMER EXP signal ceases or modifies the activity of that protocol within the processor. With a multiplicity of protocols being handled by the processor, it can be appreciated that a multiplicity of timing intervals associated with each of the protocols must be accommodated by the interval timer 870.

A 16.times.8 RAM 8708 stores the count for up to sixteen different protocols. The 16.times.1 RAM 8706 retains the state of the interval clock signal from the last scan of the selected peripheral device. The Q0 output is latched into latch 8710 at the clock time MT3. A 4-bit multiplexing latch 8704 under latching control of the clocking signals MT3 and MT5, alternately provides four address bits to the four A labeled inputs of RAM 8706 and 8708 which alternating address bits are E ADDR 6-9 and LN0A-LN3A. The output count is available at the Q0-7 output of RAM 8708 which output is directed to an 8-bit latch 8712.

The 8-bit latch 8712 is latched with the timing signal MT3 and provides at its output the latched bits which are directed to a decrementer 8714. The decrementer decrements by one the count at its input. When the decrementer 8714 outputs a zero the logic circuitry 8722 provides the TIMER EXP signal to a latch 8718 which under enabling control of the clocking signal MT4 outputs the TIMER EXP signal.

Gating circuitry 8720 receives on its inputs the output from the latching circuit 8710 and the signal INTCLK inverted by inverter 8728, and the 8-bit output signal from the latch 8712, along with the signal LNA-A. Upon meeting the logic conditions illustrated by the logic circuitry of the logic gate group 8720 a signal is outputted to the control input of the 8-bit multiplexer 8716 to control which block of eight signals appear at its output. The multiplexer 8716 will pass the outputs of the decrementer 8714 when the output of gates 8720 are active. The 8-bits from the multiplexer 8716 are directed back as a group of 8-bits to the 8-bit multiplexing latch 8702 along with the 8-bits from the E-bus bits 8-15. The outputs of an interval timer RAM 8708 are enabled onto E-bus bits 8-15 when an AND gate 8726 becomes active. The AND gate ANDs the signals SELTIM and RD.

The clocking signal MT4, the LNA-A signal and the signals WR and SELTIM control the multiplexer 8702. The logic gate group 8719 provides the signal WE to the inputs of RAMs 8706 and 8708. The 8-bit output from the 8-bits multiplexing latch 8702 is directed to the data input D0-7 of RAM 8708. The data input D0 of RAM 8706 is the interval clock signal INTCLK.

Referring to FIGS. 18A-18C assembled in accordance with the map of FIG. 18 wherein is illustrated the line status word RAM 880 which functions to store pending flags for designating events and for modifying the flow of control progress for each communication line.

The RAM 880 is comprised of a 16.times.1 RAM 8802, a 16.times.8 dual port RAM 8804, an address decode 8806, a 16.times.8 dual port RAM 8808 and a 16.times.2 RAM 8810. The address decode 8806 receives the 4-bit multiplexed input from lines LN0B-LN3B or from lines E ADDR 6-8, 13 under control of the clock signals MT1 and MT5. The address decode 8806 selects the output from RAM 8804 and 8808. These outputs are available at the A out and B out terminals simultaneously. The B out signals of RAMs 8804 and 8808 are directed to the 8-bit latches 8818 and 8817, respectively. The RAM 8810, likewise, has a latch 8813 connected to receive its 2-bit output on terminals Q0 and Q1 for latching the output upon receipt of the clocking signal MT1. The RAM 8802 has its output latched by a latch 8819. The WE signal for RAMs 8802, 8804, and 8808 is derived from the output of an AND gate 8805 and the logical combination of signals MT4 and RESET. A reset for all of the RAMs is derived from the output of AND gate 8803.

A 7-bit multiplexer 8809 directs the E-bus bits 8-14 to the address input AIN0-6 of RAM 8808 and in the test mode recirculates the data bits from the output labeled AOUT0-6 through a 7-bit latch 8816 back to the data inputs AIN0-6. The 7-bit latch 8816 is enabled by the clocking signal MT5. The RAM 8810 operates one machine cycle delayed from the RAMs 8802, 8804 and 8808.

The instruction execution unit 110 has access to the scan list RAMs 8804 and 8808 via the E-bus. The data memory address in binary, 100000LLLX000D00 selects the RAM 8808 by enablement of signal LSW1SEL. The data memory address 100000LLLX000D01 selects the RAM 8804 through enablement of signal LSW2SEL. The variable field, LLL, designates the line address of the peripheral device. Where the variable D specifies the direction, the bit definitions of RAMs 8802, 8804, and 8806 can be derived from the input labeling to the vector encoding PLA and logic 7301 of FIG. 19A.

Referring now to FIGS. 19A and 19B wherein is shown the vector encoding logic 730 and the PTG vector logic 735. The vector encoding logic 730 is comprised of the vector encoding PLA and logic circuitry 7301 and a 5-bit latch 7302. The Boolean logic expressions for 7301 are as follows:

The PTG vector logic 735 is comprised of a 9-bit latch 7351, a latch 7352 and a bank of FET devices 7353. The 9-bit latch 7351 receives the outputs labeled V0-V3 from the vector encode logic 7301 and the latched bits, LN0B-LN3B from the latch 7302. The 9-bit latch 7351 is enabled by the clock signal MT5. Upon receipt of the signal PV-RD applied to the gates of FETs 7353, the signals at the outputs of latch 7331 are applied to the T-bus.

At the bottom of FIG. 19B, a logic circuit for deriving the signal MC' is disclosed.

The vector encoding logic selects either the level 2 or level 3 program counter of the peripheral device specified by the line address signals LN0C-LN3C by setting or clearing the L2C signal, respectively. Alternately, the vector encoding logic will initiate the vector dispatch sequence by enablement of the FETCH signal to latches 7351 and 7352. If neither the level 2 program nor the level 3 program is active and the vector dispatch sequence is disabled, the level 4 program will be selected for the next instruction fetch and subsequent instruction execution cycle.

Referring now to FIGS. 20A-20D assembled in accordance with the map of FIG. 20 wherein is shown the program counter RAM 737 and associated logic circuitry. A 16-bit multiplexer 739, 16-bit incrementer 750, and 33.times.16 RAM 737 form the thirty-three counters previously referred to in the specification. Referring now specifically to FIG. 20C, the signals present at the output of a 6-bit multiplexing latch 7371 are latched and selected under the control of clocking signals MT1 and MT3. The signals are LN0C-LN3C, L2C and L4C which are either directly outputted or are delayed by latching through two 6-bit latches 7372 and 7373.

The WE enabling signal for the RAM 737 is derived by the logic gate group 7374 which logically combines the PHASE 2 signal and the BR-WR signal with the signal B-DIS. The RAM 737 receives at its ADDR input the 6 latched bits from latch 7371 and outputs at the terminals Q0-15, 16-bits of addressed data. The 16-bits, which correspond to the instruction address, are latched by a 16-bit latch 7376 to the line labeled PC0-15 under control of a reset signal from a logic circuit 7378. The outputted 16-bits are also directed to the input of the 16-bit incrementer INCR 750 which up counts, by one, the count represented by the 16-bits and provides this incremented count to one input of the 16-bit multiplexing latch 739. The other input to the multiplexing latch 739 is comprised of the bits present on the T-bus 0-15.

Under control of the ANDed clocking signal MT1 and the signal BR-WR, or alternately, MT6, the multiplexing latch 739 selects one of the two sets of sixteen signals on its inputs to provide those signals as the data inputs to the RAM 737.

The remaining logic circuitry of FIGS. 20A and 20B, denoted generally as 7377, provides a means for discontinuing the normal incrementing of the instruction RAM and for providing the signals, cycle steal delay CS-DLY, DPOW-IN and the signals CS and CS/. Shown at the bottom of the drawing is logic circuitry 7378 which provides the signal INT1 and a latching signal for the 16-bit latch 7367. These two signals are provided by the logical combination of the labeled signals on the input of the circuit.

Referring to FIG. 21, a 16-bit multiplexing latch 755 receives on one bank to its 16-bit inputs the PC bits 0-15 and on its other bank of 16-bit inputs the T-bus bits 0-15. Under control of the logic circuitry 7551 the multiplexing latch 755 latches either PC 0-15 or T-bus 0-15. The PN+1 register is connected to the I-bus bits 0-15, by means of the tri-state devices. The tri-state devices are activated by the signal ITSEN. In a like manner, the 16-bits at the output of the multiplexer are directed to the PN+1 delaying circuit 753 which circuit is comprised of two 16-bit latches serially connected and clocked with the clocking signals MT3 and MT6. A tri-state amplifier outputs the 16-bits onto the T-bus under control of the signal PN-RD.

Latch 756, for deriving the signal NNL4, is shown in the lower left corner of FIG. 21 as a miscellaneous circuit. The signal NNL4 designates the next instruction fetch cycle which is allocated to the level 4 program.

Referring now to FIG. 22 wherein is shown the last portion of the logic circuitry for the PC control 70. The break-pt register 757 is comprised of a 16-bit comparator 7572 which comparator compares 8-bits from the E-bus bits, 8-15 from logic circuitry 7574 and the 8-bits from the E-bus, bits 8-15 from logic circuitry 7576 against the corresponding bits on the I-bus 0-7 and the I-bus 8-15. The latches 7575 and 7577 contain logic which allow them to be accessed by a software program via execution of the appropriate load and store instructions to data memory addresses 84FD and 84FE, respectively. Upon receiving a 1-to-1 bit comparison, the 16-bit comparator outputs a signal to a latch 7478 which latch upon being enabled by the clocking signal MT4 outputs the bit BP DET.

Referring to FIGS. 23A and 23B, the instruction bus buffers 712 contain a first group of bi-directional tri-state amplifiers 712A and 712B. The direction of transmission for the tri-state amplifiers is controlled by the enabling signal RD/WRB. The parity signals IPAR1, IPAR2, and IPE circuits 759A and B are formulated by the logic shown comprised of an 8-bit exclusive OR gate along with associated logic. Additionally, within the logic circuitry of 759B, there is provided a latch 7591 for latching to its output the signal denoted IPE. IPE sets upon detection of an instruction parity error on a read operation of instruction memory.

The instruction control logic 760 shown in FIG. 23A is comprised of a plurality of logic gates interconnected as shown for operating upon the input signals MT4, ROMTEST, IWR, MT2 and MT3 to provide at its outputs the signals IALE, IWE/ and IOE/ along with an input and an enabling logic signal to the NOR gate 7601 to generate the signal RD/WRB. For instruction bus time relationships refer to the timing diagram of FIG. 48A.

Referring now to FIGS. 24A and 24B wherein the data bus buffers 714, parity circuit 761 and the data memory controls logic circuitry 762 are illustrated. The data bus buffers 714 are bi-directional tri-state amplifiers 714A and 714B and are shown interconnecting the E-bus conductors 0-15, respectively, to the data bus outputs 0-15 under directional control of an enabling signal from a NOR gate 7621. The parity 761 logic is shown comprised of logic circuitry 761A and logic circuitry 761B, each comprised generally of an 8-bit exclusive OR gate, for receiving the E-bus and Data bus bits and for logically combining the same to formulate the parity signals.

The data memory control circuit 762 is comprised of a plurality of logic gates interconnected as shown to provide the output signals ALE, DALE, RD, DOEB, WR and DWEB. For data bus timing relationhips refer to the timing diagram in FIG. 48B.

Referring to FIGS. 25A-25C assembled according to the map of FIG. 25 wherein is shown the state RAM 117, a pre-instruction register 113 and a multiplexing circuit 115. The multiplexing circuit 115 consists of logic circuitry, shown in FIGS. 25A and 25B, for providing four control inputs and, latching circuitry 113, for providing one of four selection inputs, to a 16-bit 4:1 multiplexing latch 1151. The output of the multiplexing latch 1151 is directed to the H-bus as bits 0-15. The state RAM 117 is comprised of a 17.times.2 RAM 1171 and a 17.times.16 RAM 1173, the output of which is coupled to a 16-bit latch 1175. Under latch control of the clocking signal MT6, the 16-bit latch 1175 outputs 16-bits to one input of a 16-bit multiplexer 1179. The multiplexer functions as a test selector. Upon receipt of a ROM TEST enabling signal, the multiplexer 1179 connects the I-bus 0-15 bits to its output and to one input of the multiplexing latch 1151.

A 2-bit latch 1171 receives the outputs from the Q0 and Q1 outputs of the RAM 1177 and directs those 2-bits to the inputs of an incrementer 1178. The incrementer increases the count of the bits on its input by one and outputs the count to one input of a pair of AND gates. The other input to the AND gates is the enabling signals D-DIS and DLAM. The outputs from the two AND gates are directed back to the D0 and D1 data inputs of the RAM 1171.

The RAM 1173 receives data on its data input D0-D15 from the H-bus conductors 0-15 with four of the bits being directed to an AND gate which is enabled by the signals W and MT1 latched with a flip-flop at its S and R inputs, respectively. The 16-bit latch 1175 and the 2-bit latch 1177 are each toggled to the enabling state by the clocking signal MT6.

The state RAM 117 retains the instruction opcode and status of instructions requiring more than one execution cycle for completion.

The 16-bit output of the pre-instruction latch 113 is selected by the 4:1 multiplexing latch if an instruction is to be executed. If an instruction requiring more than one execution cycle is executed, the state RAM is keeping an incrementing count corresponding to the particular instruction cycle to be executed. With the signal PIR-RD enabling the tri-state amplifier portion of the pre-instruction register 113, the 16-bit latch output is applied to the T-bus conductors 0-15. The multiplexing latch 115 has two constant values applied to its inputs, 1F48 and 001F, which are generated by strapping the appropriate input bits to either the +5 V supply or to circuit ground. The multiplexing latch input labeled, 1F48 HEX, is selected when no operation is desired as the result of a reset condition.

The multiplexing latch input labeled 001F HEX is selected when the instruction execution unit is to execute the PTG FETCH instruction. The PTG FETCH instruction is a single cycle indirect branch which is hand-wired into the instruction execution unit to effect the vector dispatch mechanism.

Referring to FIGS. 26A-26E assembled in accordance with the map of FIG. 26, the instruction decode logic 130 is comprised of six, microcycle AND plane devices 1301A-1301F, receiving as inputs 16-bits from the H-bus along with clocking enabling signals MT1-MT6. The output from each of the microcycle AND planes is directed to an OR plane logic device 1303. The output from the OR plane logic is directed to a latch group 1305 which latch upon receiving the signal PHASE 1 latches the signals on its input to its output.

A bank of 3:1 multiplexers 1307 receive on their inputs three of the labeled signals and upon receiving one of the group of bank select signals BANK SEL 0-2 selects one of the input signals to provide at its output. A group of tri-state devices 1309 upon receiving the signal ROM TEST connects the multiplexer outputs to the like labeled E-bus conductors 0-15. The ROM TEST signal and the BANK SEL signals are generated by a logic circuit 1311. The logic circuit 1311 receives, on its inputs, the signal RT1 and RT2.

Appendix B lists the mnemonics and opcodes for each of the instructions supported by the instruction execution unit. The instruction decode logic generates the appropriate sequence of control signals at the outputs of latch 1305 required to execute the function selected by the instruction opcode as defined in Appendix C. Appendix D contains the logic expression and coding for the instruction decode PLA comprised of AND PLANES 1301A-1301F and OR PLANE 1303.

Referring to FIG. 27 wherein is shown the logic block diagram for the field extract 135. The circuit is comprised of three 5:1 multiplexing latches 1351, 1353 and 1355 along with a bank of AND gates 1357; and a 3 to 8 decoder 1359 and associated tri-state amplifiers. The 5:1 latches each receive on their control inputs one of the outputs from the bank of AND gates 1357 and under their control select one of a group of P REG signals to provide at their outputs the signals designated R.sub.0, R.sub.1, and R.sub.2, respectively. The 3 to 8 decoder 1359 receives on its input the P REG 5-7 bits and decodes those bits to 8-bits and directs them to the T-bus 8-15 under control of the enabling signal DEC-RD applied to one of the tri-state devices. Additionally, a second tri-state device, under the control of the enabling signal IMMD-RD, places the P REG 8-15 bits onto the T-bus 8-15.

Referring to FIGS. 28A and 28B wherein is disclosed the logic for the shift circuit 136 and the arithmetic logic units (ALU) 137. The ALU 137 is comprised of a 7-bit latch 1371 and an 8-bit ALU 1373 and a like ALU unit 1375. The outputs from the ALU 1375 are available on the terminals labeled R0-7 and are directed to: a NOR gate to provide the output signal ZEROH; to an AND gate to provide the signal ONESH; and to the inputs of a tri-state amplifier to provide, under enabling control of the signal ALU-OUT, the eight output bits to the inputs of the shift circuit 136. In a like manner, the bits 8-15 are available on terminal R8-15 of the ALU 1373, directed through a NOR gate to provide the output labeled ZEROL, and directed through a tri-state device when enabled by the signal ALU-OUT.

The 7-bit latch 1371 is coupled to the control inputs CI, CGEN, OR, AND and SUB of the ALUs. The signals on the inputs to the 7-bit latch are latched into the device upon the concurrence of the signals PHASE 2 and MT3. Following is a truth table defining the ALU as a function of inputs CGEN, OR, AND, and SUB.

All other combinations of the inputs CGEN, OR, AND, and SUB are not of interest.

The shift circuit 136 is comprised of one 5:1 multiplexing latch 1361 and three 3:1 multiplexing latches 1363, 1365 and 1367. The 16-bits from the T-bus are available on the inputs of each of the multiplexing latches. The 8-bit outputs from each of the latches are directed to the indicated A and B inputs to the ALU units.

The 5:1 multiplexing latch 1361 allows right shifting or left shifting, by one bit position, the A8-15 inputs of ALU 1373. The P register bit P8 fills the new bit position caused by the shift. The signal, BUMPBIT, is the bit position shifted out of the multiplexing latch 1361. The multiplexing latches 1361, 1363, 1365, and 1367 are reset by the latching of circuit ground to their respective outputs with each occurrence of the timing signal MT3. The INCR2 signal acts to set the output of multiplexing latch 1361 which is connected to the A14 input of ALU 1373.

Referring to the CRC circuit 138 of FIG. 29, the 16-bits of the ALUOUT signal are directed to an 8-bit Exclusive OR gate 1381, a CRC-CCITT polynomial generator 1383, and a CRC-16 polynomial generator 1385. The output of the 8-bit Exclusive OR is the signal PARITY. The output signals from the polynomial generators 1383 and 1385 are applied to the input of a 16-bit multiplexer 1386, which under control of a selection signal from a latch 1387, directs one or the other of its inputs to a NOR gate and to a tri-state device which under the control of the enabling signal CRG-OUT directs the 16-bits to the T-bus 0-15. The output of the NOR gate is the signal CRCZERO. The latch 1387 latches upon the occurrence of the clocking signal MT3 and latches the signal CRCX/Y to its output. The Boolean logic expressions for the polynomial generators 1383 and 1385 are as follows:

Referring now to FIGS. 30A and 30B wherein is shown the condition code unit 139. A 6-bit latch 1397 latches the indicated signals onto its output upon the occurrence of the clocking signal MT3. These outputs are then directed to the inputs of a next condition PLA 1398. The W, X, Y and Z signals are also directed to the inputs of a condition control PLA 1396.

The Boolean Expressions for the PLAs 1396 and 1398 are as follows:

The remaining indicated signals are applied to the inputs to the next condition PLA 1398 which unit outputs the signals NCC0-NCC2 to the inputs of a 2:1 multiplexer 1399A-1399C. The multiplexers under the control of signals CC0EN, CC1EN, and CC2EN select the NCC0-NCC2 signals or the signals CC0-CC2 to provide the signals at the outputs of the multiplexer which signals are directed to the D0-D2 inputs of a 33.times.3 RAM 1391. The RAM receives the signals LN0F-LN3F, L2F and L4F at its ADDR input. The output of the RAM is available at the terminals Q0-Q2 which outputs are coupled to a latch 1392 when the latch is enabled by the clocking signal MT3. The output signals from the latch 1392 are the signals CC0-CC2, which aside from being directed to the multiplexers 1399A-C, respectively, are also directed to the inputs of a condition verification PLA 1393.

Three bits, P REG 3-5, are also applied as inputs to the PLA 1393. The output signal M from the PLA 1393 is directed as an input to the latch 1395 upon being latched with the signal available at the Q output of the flip-flop 1394. The Boolean expressions for the condition verification PLA 1393 are as follows:

The signal designated M is applied as an input to the condition control PLA 1396. The PLA 1396 additionally provides the output signals B-DIS, G-DIS and D-DIS.

Referring now to FIGS. 31A-31C assembled in accordance with the map of FIG. 31, wherein is shown the logic circuitry for the memory address register 140. The register is comprised of 4-bit, 2:1 multiplexers formed in an array 1401. The array selects groups of 4-bits from the indicated signals upon the occurrence of the selection signal LSA. The LSA signal selects the linespace addressing mode to specify the data memory address. The linespace address consists of a concatenation of the line address with bits from the instruction opcode. The format for the linespace addresses, in binary, is M00000LLLLDDDDDD. Where M is bit 9 of the opcode, LLLL is the line address and scan direction, and DDDDDD are bits 10-15 of the instruction opcode. The selected 4-bits appearing at the output of each of the multiplexers is directed to the inputs of a corresponding array of 4-bit latches 1403 which latches perform the latching function upon receipt of the logically combined clock signal MT4 and the PHASE 1 signal. The latched signals available at the output of the latching array 1403 are directed to the indicated conductors of the E-bus upon receipt of an enabling signal, derived from the gating logic circuit 1406 by logically combining the clock signal MT4, ALE and ROM TEST.

Referring to FIGS. 32A and 32B wherein is disclosed the logic circuitry for the memory data register 141. Signals from the T-bus bits 0-15 are directed to a pair of 3:1 multiplexing latches 1415 and 1414. Logic circuitry 1411 logically combines the signals indicated on its inputs to provide the selection input to the multiplexers. The multiplexers in turn provide at their outputs signals which may be directed to the E-bus conductors 0-15 by means of enabling the tri-state devices 1418 and 1419 with an enabling signal from the latch 1416. The latch 1416 receives on its S input the ANDed signals RD and MT6 from the AND gate 1417 and on its reset input, R, the clocking signal MT2. Using substantially similar circuitry, signals present on the E-bus conductors 0-15 may be directed to the T-bus conductors 0-15 by the circuit 1420 and the associated logic circuitry 1412 for providing the three selection input signals to the multiplexing latches which form part of the circuitry of 1420.

Referring to FIGS. 33A and 33B wherein is disclosed the logic circuitry for the general register RAM 143. The general register RAM contains the eight program registers allocated to the input and output programs for each of the communications lines, and the level 4 program. The program registers are selected by the R0-R2 signals generated by the field extraction logic 135. The values 0-5 on the RO-R2 signals select eight bit program registers 0-5. The values of 6 and 7 on the R0-R2 signals select 16-bit program registers 6 and 7, respectively. Two 85.times.8 RAMs 1432 and 1433 each provide an 8-bit output that is directed to an 8-bit latch 1437 and 1436, respectively. The output of the 8-bit latch 1436 is directed to a pair of tri-state devices 1438 and 1439 with the output of 1439 being the 8-bit signal applied to the T-bus 0-7. The output signals from the tri-state devices 1438 are directed to the D0-7 input of the RAM 1432 and to the T-bus conductors 8-15. The D0-7 inputs of the RAM 1433 are derived from an 8-bit multiplexer 1434 which multiplexer receives on its inputs the 8-bits from the T-bus 0-7 and the 8-bits from the T-bus 8-15 toggled or enabled by the signal at the output of the AND gate 1435. The address bits for the RAMs are derived from an 8-bit combination of the signals R0-R2, LN0F-LN3F and L4B. The latching action of the latches 1436 and 1437 is controlled by the signals GR-RD, GR-WR and the signal PHASE 2. Activation of the tri-state devices 1438 and 1439 is by way of enabling signals coming from a logic circuit 1431 which receives as its inputs the signals PHASE 1, PHASE 2 and R0-R2.

Referring now to FIG. 34 wherein is disclosed the logic circuitry for the auxiliary RAM 144. The RAM is comprised of a central memory 17.times.16 in size labeled 1441 for latching out a 16-bit output in response to the 5-bit signal labeled LN0F-LN3F, L4F, applied to its ADDR input. The 16-bits are latched by the latch 1443 under control of the enabling signal derived as a logical combination of the signals AUXRD, MT3 and AUXWR. Passage of the 16-bit latch signal to the T-bus 0-15 is accomplished with enablement of the tri-state device 1445 by the application of the signal AUXRD.

Referring to FIG. 35 wherein is disclosed the default line number register 145 comprised of two 4-bit latches 1451 and 1452 along with a 6-bit latch 1453. The primary function of the default line number register is to provide the level 4 program with a means for utilizing the linespace addressing mode. The 4-bit latch 1451 receives the E-bus signals 12-15 and latches those signals under control of the logically combined signals DEFLNSEL, RD and WR. The 4-bit latch 1451 is mapped onto the E-bus at hexadecimal data address 84FC. The output of the 4-bit latch 1451 is directed to the 4-bit multiplexer 1452 along with the signals LN0E-LN3E. An enabling signal L4E selects which of the 4-bit inputs will appear at the output with the output being directed to a 6-bit latch 1453. The 6-bit latch in response to the timing signal MT3 latches the 4-bits previously mentioned and the signals L4E and L2E to its output.

Referring to FIG. 36 wherein is disclosed the circuitry for the address detection circuit 764. The circuit is comprised of an address detection PLA 7641 and dynamic latches 7643 and 7645. The clocking signal MT4 causes each of the latches to latch the 8-bits appearing at their inputs to the outputs and in turn to the inputs of the address detection PLA 7641. Dynamic latch 7643 receives the 8-bits from E-bus 0-7 while the dynamic latch 7645 receives the 8-bits from the E-bus 8-15. The inputs, outputs and Boolean logic equations for the address detection PLA 7641 are as follows:

Referring to FIGS. 37A-37D, assembled in accordance with the map of FIG. 37 is a block schematic diagram of the CPIF interfacing control logic chip 502. The CPIF monitors signals from the outbound control register, service request FIFO, and the inbound interface register in order to determine if one of eight CPIF transfer sequences is to be executed. The CPIF transfer sequences are classified as inbound or outbound depending on the direction of the transfer. An outbound transfer which is from the I/O controller will be made for both input and output directions of a communications line. Likewise, an inbound transfer (to the I/O controller) will be made for both directions of the communications line.

The CPIF transfers data to the front-end processor in a byte serial mode, as illustrated in the timing diagram of FIG. 49.

The CPIF chip 502 is comprised of an address latch 510, address detection logic 520, a timing chain 530, a request FIFO 540, a 64.times.8 dual port RAM 550, and a utility register 560. Additionally, there is provided an I/O transfer sequencer 570, an inbound interface register 580, an outbound interface register 590, and a flag RAM 595. A number of inverters and tri-state devices bring signals into the chip from the numbered pins which numbers correspond to the chip pin numbers shown in FIG. 4E. Each of the aforementioned major blocks will be described and shown in detail in the remainder of the specification.

Referring to FIG. 38 wherein is shown the address latch 510 and the address detection logic 520. The address latch 510 receives the signal DB0 and the signals DB5-7 to comprise four of its input bits and from a tri-state device the signals DB8-15 to provide data output addresses DA0, 5-15 upon receipt of an enabling signal DALE. The data address signals are sent to a register select logic 5201 which is a component part of the address detection logic 520 outlined with dotted lines.

The input signals, and output signals in Boolean logic equation form for the register select logic 5201 are as follows:

The register select logic 5201, in response to the data output enabling signal DOE/ and the addressbits received on its B input selects one or more of the registers by activating corresponding signals on its output. The RAM SEL signal is directed to a group of AND gates 5203 as an enabling signal. The gates operate in conjunction with a latch and clocking signals MT4B, MT1B, and the signal DWE/ to provide the output signals; ADDRSEL, ARDEN and AWREN. The output enable signal OUT EN/ from the register select logic 5201 is used to enable the tri-state devices connected to pins 12-19.

Referring to FIG. 39 wherein is disclosed the 64.times.8 dual port RAM 550. A pair of 2:1 multiplexers 5501 and 5503 receive on their A and B inputs the indicated eight and six bits, respectively. The signal ADDRSEL applied to the SEL A inputs of the multiplexers direct either the A or B signals onto the C labeled outputs and to the A0-5 addressing inputs of a 64.times.8 RAM 5505. The outputs of multiplexer 5501 are data bits which are directed to the D0-7 labeled inputs of the RAM 5505. The AND gate 5507 in response to the signals AWREN/ and BWREN/ provides a write enable signal to the RAM 5505. The 8-bit output signal is provided at Q0-7 and is directed to the input of a pair of tri-state devices 5509. The amplifiers are enabled by signals from AND gates 5506 and 5508 in accordance with the level of the signals indicated on their respective inputs.

Referring to FIGS. 40A-40C assembled in accordance with the map of FIG. 40 wherein the utility registers 560 are shown comprised basically of a group of latches 5601A-5601G for receiving on their inputs the data bits 8-15, either directly or through multiplexing circuits 5603, 5605 and 5607. Various combinations of logic gates operate upon the input signals to provide the latch enabling and reset function signals EN and RST and to select the inputs to the multiplexers. The output signals of these latches are transferred to the data bus by enablement of a plurality of tri-state devices.

Referring now to FIGS. 41A and 41B wherein is disclosed the logic circuits for the request FIFO 540. The central component of the request FIFO is a 16.times.4 register file 5409 which receives on its Din input the signals DA 6-9 and under the control of signals ADDR, WRE/ and RST provide at its output, in the sequential order received, the signal FIFO LN0-3. The address signal is received from the C output of a 2:1 multiplexer 5407 which under control of the signal on its SEL input selects as addresses the bits OD0-3 or the bits ID0-3 from the 4-bit binary counters 5403 and 5404, respectively. The SEL signal is derived from the state of a latch 5405. Logic circuitry 5401 provides bits to the counter 5403 while the logic circuitry 5402 provides bits to the counter 5404. The signal MR is used to reset both counters.

A comparator 5406 receives the output signals from the 4-bit counters and upon receiving an equal count provides at its output, labeled C, an enabling signal to a group of AND gates 5408. The output signal from one of the AND gates is the signal EMPTY/ which indicates whether the register file is empty or not. The output signal from the other AND gate is directed to a NAND gate along with the signal MT5B and the ANDed signals DWE and FIFOSEL to form the signal WRE/ applied to the register file 5409.

FIG. 42 is a logic block diagram of the timing chain 530 shown comprised of two 6-bit shift registers 5301 and 5302 for generating the clocking signals MT1B-MT6B and MT1A-MT6A. The basic clocking signal CLK is received on pin 11 and is directed via an amplifier to the CP inputs to the registers 5301 and 5302.

Referring now to FIGS. 43A-43D assembled in accordance with the map of FIG. 43 wherein is disclosed a portion of the I/O transfer sequencer denoted 570A. The sequencer functions to control data movement between the inbound and outbound registers 580 and 590, respectively. The logic circuitry of FIG. 570A is straight-forward and will not be described in detail as the circuitry does direct logical combination of the signals on its input to arrive at the designated signals at the outputs. In a like manner, the B portion of 570 shown in FIGS. 44A-44C performs straight logic functioning on the input signals to derive the indicated output signals. The three multiplexing latches operate with the enabling signal on their ENA input to select the signals appearing at the A labeled input and to provide those signals at the output labeled C. In a like manner, an enabling signal at their ENB input will select the signals at the B labeled input and provide those signals at the output labeled C.

Referring to FIGS. 45A-45D assembled in accordance with the map of FIG. 45 wherein is shown the inbound interface registers 580. Designated input signals are applied to terminals A, B and C of 3:1 multiplexing latches 5802, 5803 and 5804. Under control of the enabling signals ENA-ENC, one of the inputs A, B or C is selected to appear at the D output of each of the multiplexers. The outputs on the D labeled terminals are directed to the terminals labeled A0-7, B0-7 and C0-7 of a 4:1 multiplexer 5805. The input terminal labeled D3-7 receives the 5-bit output signal from the logic circuitry 5808. The 5-bit signal is derived from a logical combination of the signals SB0, SB1, DSQ, SETRI, MR, CLRICNTL, NSTAT4, IUTST and OWRAPST. These signals and combinational logic form the inbound control signals INCTL 3, 4, 5, and 6, and 7.

A 2:4 decoder 5801 (FIG. 45A) receives on its M labeled input the signal REG SEL 0 and on its L labeled input the signal REG SEL 1 and provides at its output four signals which are directed to the SA, SB, SC and SD selection inputs of the 4:1 multiplexer 5805 and to the corresponding inputs of the 4:1 multiplexer 5806. The 8-bit output from multiplexer 5805 is the signal CPIN 0-7 and the output of multiplexer 5806 is the signal CPPARIN.

Referring to FIGS 46A-46D assembled in accordance with the map of FIG. 46. The outbound interface registers 590 are shown in logic schematic form. The logic circuitry shown in FIGS. 46A-46D is straightforward combinational logic such that the signals BS0 and BS1 from FIG. 45A are directed to a 2:4 decoder 5901 with 1-bit of each of the four outputs being used as an input to a group of AND gates 5902. The signal CB SEL/, applied to an inverter, generates another input to each of the AND gates of the group 5902. The remaining input is derived from the signal CB STROBE inverted by logic circuitry. The gated signals from the AND gates 5902 are directed to a pair of 8-bit latches 5905 as the enabling signal EN and to the enabling input of a 4-bit latch 5904 and to the clocking input of the D-type flip-flops 5906A-5906D. The signals present at the Q outputs of the 8-bit latches 5905 are selected by a 2:1 multiplexer 5903 under control of the selection signal OSMXC to provide at its C labeled output the signal RAM BIN 0-7.

The flag RAM 595 shown in FIGS. 47A and 47B is comprised of three major logic circuits, the flag control logic 5951, the flag write logic 5952, and the flag read logic 5954. The above will be described in terms of input and output signals and Boolean logic equations.

Additional support circuitry for deriving the signals represented by the Boolean equations is comprised of a pair of latches 5959 and 5960 along with a 2:1 multiplexer 5958 and a comparator 5957. The latch 5959 is enabled with the enabling signal CYC1 to latch the input signal OUTLN 0-3 to its Q output which output is directed to an input of the comparator 5957 and the A labeled input of the multiplexer 5958. The latch 5960 is enabled by the signal LNV to latch the signal LNDIR and LN0-2/ FLAGS to its output Q0-3. The signals latched to the output are directed to an input of the comparator 5957 and to the B labeled input of the multiplexer 5958. The selection signal for the multiplexer 5958 is the signal FADS, available at the S labeled output of the flag control logic 5951. The signal multiplexed out of 5958 is directed to the ADDR input of the 16.times.4 register file 5953.

The comparator 5957 provides a comparing signal when the signals on its input are equal, which signal is defined as LNEQ and which signal is directed to the N labeled inputs of the flag control logic 5951 and the flag write logic 5952. The data stored in the register file 5953 is directed to the Din input and is labeled FIN0-3 and appears at the P output of the flag write logic 5952.

The flow charts contained in FIGS. 50-54 define the program flow of the level 2 software executed to perform the character assembly function of a HDLC protocol. FIGS. 55-57A illustrate the program flow of the level 2 software used to perform character assembly for peripheral devices communicating under a IBM Bisynchronous communications protocol. The level 2 software program flow of the character assembly routine for a start-stop communications protocol is contained in FIGS. 57B-60. The flow charts contained in FIGS. 61-65 define the program flow of the level 2 software executed to perform the character disassembly function of the HDLC protocol. FIGS. 66-69 illustrate the program flow of the level 2 software used to perform the character disassembly function for peripheral devices communicating under the Bisynchronous protocol. The level 2 software program flow of the character disassembly routine for the start-stop communications protocol is contained in FIGS. 70-75. A person, skilled in the art, can implement these program flows in the instruction set defined in Appendix B.

A method of using the Least Common Multiple of common bit rates; 19,200, 14,400, 9,600, 7,200, 1,800, 3,600, 2,400, 1,800, 1,200, 600, 300; was used to determine the time division interval for time division communication processing. It was assumed for this implementation that a minimum of 16 samples per bit would be adequate to recover received serial data or generate output data rates while providing enough resolution to practically preserve the chronological order of communication line control signal changes of binary state with respect to serial data transfers. An objective of connecting 8 communication lines is assumed. However, the line connectivity can be reduced to four communications if all lines are operating at a bit rate of 19,200 bits per second.

The least common multiple of 19,200, 14,400, 9,600, 7,200, 1,800, 3,600, 2,400, 1,800, 1,200, 600, and 300 is 57,600. This is 3 times the bit rate of 19,200, but less than the desired minimum of 16 samples per bit at 19,200 bits per second. The lowest integer that can be multiplied by 3 that satisfies the minimum sample rate of 16 is 6. The result is 18 samples per bit for a 19,200 bit per second communications line. The number of time divisions per second necessary to connect four 19,200 bits per second communication lines is the multiplication product of 4, 19,200, and 18 or 1,382,400. The scan list time interval becomes the reciprocal of 1,382,400 bits per second or approximately 723.3796 nanoseconds.

It was assumed that a minimum bit rate of 4,800 bits per second is adequate for any of 8 connected communication lines. Therefore, a scan list length of 16 is provided. Each scan list entry represents 18 samples per bit at 4,800 bits per second. If four lines are entered symmetrically in the scan list, each line appears four times and represents 18 samples per bit at 19,200 bits per second. Two alternating communications lines appear 8 times representing 38,400 bits per second. Eight lines symmetrically entered in the scan list each appear twice and each represent 9,600 bits per second.

Communication lines that operate at bit rates containing two prime factors of 3 (14,400, 7,200, 3,600, etc.) are given 24 time division intervals per bit by the scan list and therefore, are considered to be equivalent to 4/3 there actual bit rate with respect to scan list entries.

While there has been shown what is considered to be the preferred embodiment of the invention, it will be manifest that many changes and modifications may be made therein without departing from the essential spirit of the invention. It is intended, therefore, in the annexed claims, to cover all such changes and modifications as fall within the true scope of the invention. ##SPC1##