Integrated High Voltage Generating System

This invention relates to an integrated high voltage generating system, and more particularly to an integrated high voltage generating system having a charge pump.

Various products have recently been developed which are portable and compact, and, as a result, they tend to have a lower supply voltage obtained from a single power source. For example, the power voltage of portable radio or portable tape recorder is about 1.5 to 3.0 V. When a high power voltage is required for a product, a high voltage generating system is incorporated in the product or a semiconductor device used in the product. When an integrated high voltage generating sytem is incorported in a semiconductor device, the high voltage is generated by using a charge pump. Furthermore, if a high voltage power source having different potentials is needed, a high voltage is first generated by the charge pump, and this high voltage is divided and stepped down. The output is controlled using this divided voltage, thereby creating another high voltage source different from the original high voltage source. However, since the current supply capacity of the charge pump in the device is smaller in relation to its area, the electric power consumed in this dividing circuit cannot be ignored.

A conventional integrated high voltage generating system using a charge pump is described below.

FIG. 7 shows a conventional example of an integrated high voltage generating system using a charge pump for delivering two different power voltages. It comprises a charge pump having four unit circuits connected in series composed of diode-connected N-channel MOS transistors 1 to 5 and capacitors 6 to 9, a dividing circuit composed of two MOS transistors 17, 18, and a step-down control part composed of a MOS transistor 11 gated by the divided voltage of the dividing circuit.

The operation of the conventional integrated high voltage generating system is explained by referring to FIG. 7.

The electric charge coming in through the MOS transistor 1 from power source V.sub.cc connected to the power source input terminal is sequentially transferred among four stages of unit circuit controlled by clock signals CLK, CLK of normal and reverse phases with an amplitude of V.sub.cc, and is sequentially boosted in this process. The boosted power supply voltage is delivered to a first power supply output terminal OUT 1. Part of this power supply voltage is delivered to a second power supply output terminal OUT 2 as another power supply voltage, by way of a step-down MOS transistor 11 which is gated by the divided output of the dividing circuit composed of two MOS transistors 17, 18. However, when a dividing circuit is used within the integrated high voltage generating system, the stability and response of this circuit and the current consumption are in conflict with each other, and accordingly the current consumption cannot be significantly decreased. The reason is as follows. Usually, at the first power supply output terminal OUT 1, a current flows of about several microamperes. On the other hand, when the MOS transistors 17, 18 are fabricated according to the design rule of about 3 microns, the gate width (W) and gate length (L) of the gate electrode are usually about 60 microns and 3.0 microns respectively and their ratio W/L is about 20. At this time, the circuit IL flowing in the MOS transistors 17, 18 is about 5 mA. That is, when such MOS transistors 17, 18 are used, the majority of the current of several milliamperes delivered from the charge pump is consumed in the dividing circuit, and the function as the integrated high voltage generating system is sacrificed. Hence, as one of the methods of decreasing the current consumption in the dividing circuit to, for example about 5 .mu.A, it may be considered to design the gate width (W) at about 3 microns and the gate length (L) about 1500 microns, that is, the W/L of about 0.002. In turn, hoever, when the gate of MOS transistors 17, 18 is fabricated in such a size, since the gate width (W) itself is only about 3 microns, if its dimension varies about .+-.0.3 micron, the effect of fluctuation is significant, and the stability of the device is impaired. Or when the gate is reduced to such a size, the stray capacitance of the gate increases. As a result, the response of the circuit is worsened. Thus, in the conventional integrated high voltage generating system using a dividing circuit, it was extremely difficult to lower the current consumption without spoiling the stability and response of the circuit.

Additionally, as another method of decreasing the current consumption, it may be considered to raise the dividing resistance. For example, when dividing 20 V into 15 V, in a 3-micron process, by using a MOS transistor of about 3 mm.sup.2, the current consumption becomes about 100 .mu.A. To reduce this current consumption, additional MOS transistors as the dividing resistances should be inserted between the power supply terminals of the dividing circuit (more than a dozen in the above example). Thus, the value of the current flowing in the dividing circuit may be reduced to sevaral microamperes, and the current consumption can be decreased. This method however, becomes sensitive to fluctuations of the threshold voltages of the MOS transistors. Accordingly the circuit stability is poor.

On the other hand, the charge pump power supply is extremely small in the supply electric power per umit area, as compared with the power supplied by merely dividing the external power source. Therefore, if the capacity of the charge pump is increased in order to compensate for the slight power consumption in the dividing circuit, the area occupied by the charge pump within the semiconductor device becomes extremely large, and the chip size itself becomes larger.

It is hence a first object of this invention to present an integrated high voltage generating system capable of obtaining a potential between the input power supply voltage and the output power supply voltage without consuming unnecessary current.

It is a second object of this invention to present an integrated high voltage generating system capable of obtaining a potential between the input power supply potential and the output power supply potential without causing the chip area to be increased.

This invention may be briefly summerized as an integrated high voltage generating system including a charge pump having a plurality of unit circuits composed of diodes or diode-connected MOS transistors and capacitors of which one end is connected to the input side of the diodes or the MOS transistors and the other end to the clock signal source, connected in series so that the diode polarities may be in a same direction and clock phases applied to adjacent capacitors may be mutually reverse, wherein an intermediate potential is taken out from the intermediate node between the power supply input terminal of the charge pump and the first power supply output terminal, and this intermediate potential is applied to the gate of the MOS transistor connected between the first power supply output terminal and the second power supply output terminal.

In this constitution, without consuming the unnecessary current as experienced in the dividing circuit, and without causing the chip area to be increased, a potential between the input power supply potential and the first power supply output potential may be obtained from the second power supply output terminal.

Other features and objects of the present invention will be apparent from the following description taken in connection with the accompanying drawings.

FIG. 1 is a circuit diagram of one embodiment of an integrated high voltage generating system of this invention;

FIG. 2 is a conceptual diagram modeling the voltage changes at each stage of the charge pump in FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of this invention;

FIG. 4 is a circuit diagram of third embodiment of this invention;

FIG. 5 is a circuit diagram of a fourth embodiment of this invention;

FIG. 6 is a circuit diagram of a fifth embodiment of this invention; and

FIG. 7 is a circuit diagram of a conventional integrated high voltage generating system.

Referring now to the drawings, this invention is described relating to some of the embodiments in detail below.

FIG. 1 is a circuit diagram showing one of the embodiments of this invention. In this diagram, the charge pump constructed by the series connection of four stages of a unit circuit composed of diode-connected N-channel MOS transistor 1 to 5 and capacitors 6 to 9 is same as in the prior art. However, in this charge pump an intermediate potential is taken out from the intermediate node (the second stage in the case of the embodiment in FIG. 1) between the power supply input terminal and power supply output terminal. This intermediate potential gates MOS transistor 11 which couples a first power supply output terminal OUT 1 and a second power supply output terminal OUT 2. The first power supply voltage V.sub.OUT 1 is supplied into a voltage detector circuit (not shown), while the second power supply voltage V.sub.OUT 2 is supplied into a load (not shown). Capacitors 10, 12 are smoothing capacitors to lessen the repple of the first and second power supply output voltage V.sub.OUT 1, V.sub.OUT 2. At each stage of the charge pump, clock signals CLK, CLK of mutually opposite phases are applied to adjacent pumps, and their amplitude is V.sub.cc, equal to that of the power supply voltage.

In this constitution, the electric charge running in through the MOS transistor 1 by way of the power supply V.sub.cc connected to the power supply input terminal is sequentially transferred among four stages of the charge pump being controlled by the clock signals CLK, CLK of normal and reverse phases having an amplitude of V.sub.cc.

The conceptual drawing of the voltage waveform of each node of the charge pump at this time is shown in FIG. 2, is which the output of the first power supply output terminal OUT 1 is V.sub.OUT, the sum of the currents flowing out is I, and the threshold voltage of the MOS transistors is VT.

The first stage of the charge pump is explained as follows. For the sake of simplicity, the clock signal is suppose to have no transient time and phases of the clock signals CLK and CLK are accurately reverse and the capacity of the capacitors 6 to 8 for the charge pump is supposed to be sufficiently larger than the stray capacitance. When the clock signal CLK connected to the capacitor 6 is LOW, the potential of this capacitor 6 is V.sub.cc -VT. At phase 1, the clock signal CLK rises, and the capacitor potential at the first stage instantly goes up to V.sub.cc -VT+V.sub.cc to reach the peak voltage. At this moment, the clock signal CLK for the capacitor of the next stage (second stage) falls, so that the electric charge stored in the capacitor 6 of the first stage is transferred to the capacitor 7 of the next stage via the MOS transistor 2. As a result, the potential of the capacitor 6 changes by -dV. At phase 2, since the clock signal CLK of the capacitor 6 falls, the potential of the capacitor 6 changes by -V.sub.cc. Accordingly, the potential is decreased to the bottom voltage in a moment and then receiving electric charges from the preceding stage, the potential changes by +dV, and the node potential becomes V.sub.cc -VT. Here, assuming the frequency of the clock signals CLK and CLK to be f [Hz] and the capacitance of the capacitor in the charge pump to be C [F], in the stationary state, the electric charge C.multidot.dV transferred once from the capacitor 6 to 7 is equal to the sum of the current I/f flowing out per one clock time. Hence, dV=I/fC. Such a cycle occurs in each charge pump.

This operation may be also explained as follows. In the actual charge pump, the ON resistance of the transistors 2 to 5 are inserted in series to the input side of the diode-connected MOS transistors 2 to 5. Accordingly, each stage of the charge pump possesses some time constant due to capacitors 6 to 9 and the ON resistances. Therefore, when clock signals CLK, CLK are applied to each stage, the potential of each intermediate node momentarily reaches the peak voltage (or the bottom voltage) when the clock signal rises (or falls), and then changes to a stationary voltage of a high level (or low level) according to the time constant. If rise and fall of clock signals CLK, CLK are sufficiently steep, the peak voltage at the n-th stage, the stationary voltage of a high level, the stationary voltage of a low level and the bottom voltage are respectively expressed in equations (1) to (4).

Peak voltage at the n-th stage:

High level stationary voltage at the n-th stage:

Low level stationary voltage at the n-th stage:

Bottom voltage at the n-th stage:

where Rs is an equivalent resistance per stage, Rs=I/fC. Incidentally, equations (1) to (4) may be also expressed as in equations (5) to (8) respectively, in terms of the first power supply output voltage V.sub.OUT 1 and the power supply voltage V.sub.cc. In these equations, N denotes the total number of stages of the unit circuit in the charge pump.

From equation (7) it is known that the low level stationary potential of the potential of the intermediate node obtained from the n-th stage is equal to the potential of interior division between the voltage V.sub.OUT 1 of the first power supply voltage OUT 1 and the value lower by V.sub.T than the voltage V.sub.cc of the power supply input terminal into N-n+1; n-1, that is, a divided voltage.

In the embodiment shown in FIG. 1, an intermediate potential is obtained from the intermediate node at the second stage, which corresponds to the case where n=2. In this circuit, from the second power supply output terminal OUT 2, a voltage lower than the maximum voltage applied to the gate of the MOS transistor 11 by V.sub.T (threshold voltage of the MOS transistor 11) is taken out as the second power supply output voltage V.sub.OUT 2. That is, the second power supply voltage V.sub.OUT 2 is

As clearly understood from this embodiment, by selecting the intermediate node (that is, in this case, setting n to any one of 1 to 4), the value of the second power supply voltage V.sub.OUT 2 can be changed. Furthermore, in this circuit, since the dividing circuit as used in the conventional example shown in FIG. 7 is not used, a potential between the input power supply voltage and the second power supply output voltage V.sub.OUT 2 may be obtained without consuming any unnecessary current.

FIG. 3 shows a second embodiment of this invention, combining two pieces of the embodiments shown in FIG. 1, and the parts indicated by reference numbers 1' to 11' are identical in function with 1 to 11 in FIG. 1, respectively. At the power supply input terminal of each charge pump, power supply V.sub.cc is connected, and the power supply output terminals are commonly connected. Furthermore, clock signals CLK, CLK are applied to each stage of two charge pumps so that the phase may be reverse to each other. Accordingly, the output voltages are same as in the first embodiment in FIG. 1, but the phase of operation of each charge pump is reverse to each other, so that the operation is effected in such a manner as to reduce the ripple of the first and second power supply output voltage V.sub.OUT 1, V.sub.OUT 2 of the first and second power supply output terminals OUT 1, OUT 2. That is, in the case using one line of a charge pump as in FIG. 1, pulsating currents similar to when a half-wave rectifying voltage is smoothed are caused, and the ripple content increases. However, when two lines of charge pump are driven alternately in reverse phases as shown in FIG. 3, the pulsating currents become as if full-wave rectifying voltage were being smoothed, so that the ripple content is decreased correspondingly.

FIG. 4 shows a third embodiment of this invention, in which a diode-connected MOS transistor 13 and a smoothing capacitor 14 are inserted between the intermediate node and the step-down MOS transistor 11 in FIG. 1. By constructing the circuit in this way, the gate voltage of the step-down MOS transistor 11 is stabilized, and the second power supply output voltage V.sub.OUT 2 is also stabilized. The reason for this is as follows. As stated above, from the second power supply output terminal OUT 2, voltage lower than the maximum voltage applied to the gate of the MOS transistor 11 by V.sub.T (the threshold voltage of the MOS transistor 11) is taken out as the second power supply output voltage V.sub.OUT 2. Since the voltage applied to the gate of the MOS transistor 11 is a voltage from the intermediate node, it fluctuates periodically in synchronism with the clock signals, CLK, CLK. Therefore, for instance, if the gate voltage fluctuates between 11 V and 16 V and the threshold voltage V.sub.T of the MOS transistor 11 is 1 V, the second power supply output voltage V.sub.OUT 2 has a possibility of varying between 10 V and 15 V. Accordingly, by connecting the diode-connected MOS transistor 13 and the smoothing capacitor 14 between the intermediate node and the MOS transistor 11, the voltage applied to the gate of the step-down MOS transistor 11 can be flattened by the rectifying and smoothing action of the MOS transistor 13 and smoothing capacitor 14. As a result, the second power supply output voltage V.sub.OUT 2 is lower than the flattened gate voltage by the portion of threshold voltage V.sub.T, and an extremely stabilized voltage is obtained. In this circuit, the second power supply output voltage V.sub.OUT 2 is expressed as follows:

Incidentally, a similar effect will be obtained by using an ordinary diode instead of the diode-connected MOS transistor 13.

In the above embodiments, meanwhile, the gate potential of the step-down MOS transistor 11 is determined by the peak voltage of the intermediate node, or, in other words, the top value of the transient response at the moment of rise (or fall) of clock signals CLK, CLK. This top value of transient response suffers extremely by fluctuations of the ON resistances of MOS transistors 2 to 5 and the phase deviations between the two clock signals CLK, CLK. Therefore, it is not wise to determine the gate potential of the step-down MOS transistor using the top value.

Accordingly, FIG. 5 shows a fourth embodiment of this invention which makes design easier and more precise than the foregoing embodiments. In this embodiment, the intermediate potential is taken out from the intermediate node through a MOS transistor 16 which is gated by the node signal in the previous stage. In this case, in the newly added MOS transistor 16, the gate potential and the charge pump side potential of the source drain are driven in opposite phases, and since the gate side is connected to the node of the previous stage (i.e. to one-stage lower voltage point), the maximum value of the intermediate potential is a low level stationary value (not the top value) of the n-th stage. Therefore, designing becomes easier and more precise. At this time, the second power supply voltage V.sub.OUT 2 is

As clear from equation (11), in this embodiment, the second power supply output voltage V.sub.OUT 2 is determined only by two elements, that is, the first power supply voltage V.sub.OUT 1 and V.sub.cc -V.sub.T. (In all foregoing embodiments, the element of current I was contained.)

FIG. 6 shows a fifth embodiment, in which the charge pump 19 contains the elements 1 to 10, 13, 14 or 16 shown in FIG. 1, 3, 4 and 5. A voltage detection circuit 20 is composed of a transistor 21 for detection of voltage, a load transistor 22 and an inverter 23. The output of the voltage detection circuit 20 controls the clock signal source 24.

The input power supply voltage V.sub.cc is boosted by the charge pump 19, and when the voltage V.sub.OUT 1 of the first power supply output terminal OUT 1 exceeds a predetermined value, the voltage detection transistor 21 is turned on, and the output of the inverter 23 becomes a high level signal. In consequence, the frequency of the clock signal source 24 decreases, and the first power supply output voltage V.sub.OUT 1 is lowered. As a result, when the first power supply output voltage V.sub.OUT 1 becomes lower than the predetermined voltage, the voltage detection transistor 21 is turned off, and the output of the inverter 23 becomes a low level. Hence, the frequency of the clock signal source 24 increases, and the first power supply output voltage V.sub.OUT 1 rises. By repeating such an operation, the first power supply output voltage V.sub.OUT 1 is maintained at a predetermined voltage. When the first power supply output voltage V.sub.OUT 1 is maintained at a predetermined voltage, the second power supply output voltage V.sub.OUT 2 is also maintained at a voltage lower by V.sub.T (threshold voltage of the MOS transistor 11). Therefore, the second power supply current voltage applied to the load can be stabilized.

Particularly, as with the charge pump 19 is FIG. 6, when the charge pump shown in the embodiment in FIG. 5 is used, the second power supply output voltage V.sub.OUT 2 is determined only by the two elements of the first supply output voltage V.sub.OUT 1 and V.sub.cc -V.sub.T, and the element of current I is not contained, so that the stabilization of the second power supply output voltage V.sub.OUT 2 becomes extremely easy.

In the foregoing embodiments, meanwhile, the unit circuits of the charge pump were composed of diode-connected MOS transistors, but the same effects will be obtained if composed of ordinary diodes.

Thus, by using the integrated high voltage generating system of this invention, since an intermediate potential between the output end potential and input end potential is taken out from the intermediate node of the charge pump, there is no extra current consumption due to the dividing circuit, and the layout area is not to increased due to the dividing circuit, so that excellent effects may be obtained.