US 4,833,647 AGrant
Semiconductor Memory Device Having High Capacitance and Improved Radiation Immunity
Issue Date:1989-05-23
•8 Claims
•4 Drawing Sheets
Abstract
The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.
Metadata
Assignee
- Kabushiki Kaisha Toshiba
Inventors
- Satoshi Maeda
- Shizuo Sawada
Application Information
Application Number:US 903997&
Filing Date:1986-09-05
Priority Date:1985-09-10
Art Unit:233
Classifications
IPC:
G11C 1134G11C 1124H01L 2978H01L 2702
Field of Search:
365357149;18223.6;24;41
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to a semiconductor memory device and method for manufacturing it. The invention is particularly related to a dynamic random access memory (to be referred to as a dynamic RAM hereinafter).
2. Description of Invention Background
Recently, a number of methods which decrease the size of semiconductor integrated circuit elements have been tried to increase packaging density. For example, in dynamic RAMs, MOS capacitors which store data are formed by a parallel combination of two capacitors. One capacitor is formed between an electrode and an inversion region (with anooxidation area therebetween), and another capacitor is formed between the inversion region and a semiconductor substrate. However, since the capacitance is small in this configuration, the area of the memory cell must be large to obtain a large capacitance.
As shown in FIGS. 1 and 2, a memory cell structure of reduced size which removes these faults is illustrated in "The Hi-C RAM Cell Concept" IEEE, ED-25, No. 1, JANUARY 1978, P88 by ALF, TASCH. FIG. 1 is a sectional structure drawing. FIG. 2 is an equivalent circuit of FIG. 1. As shown in FIG. 1, a P type semiconductor substrate 11 consists of, for example, silicon. The doping concentration of substrate 11 is 2.times.10.sup.15 cm.sup.-3. A N.sup.+ type source region 12 and a N.sup.+ type drain region 13 are formed in semiconductor substrate 11. A gate electrode 16 is formed on an insulation layer 15 which is formed on a channel region 14 between source and drain regions and 13. The result is an insulation gate type field effect transistor Q. Source and drain regions and 13 are respectively formed by doping with having arsenic a concentration of 10.sup.20 cm.sup.-3.
MOS capacitor C is formed adjacent to source 12. MOS capacitor C includes a P.sup.- type impurity region 17 adjoining source region 12, N.sup.+ type impurity region 18 which has a shallow diffusion depth and is formed in impurity region 17, an insulation layer 19 formed on N.sup.+ type impurity region 18 and a polycrystalline silicon gate 20 formed on insulation layer 19. Drain region 13 is connected to a bit line BL, gate electrode 16 is connected to a word line WL and polycrystalline silicon gate 20 is connected to a negative power supply Vs or positive power supply.
In the above configuration, the memory capacitance results from a parallel capacitance of PN junction capacitance Cj between P.sup.- type impurity region 17 and N.sup.+ type impurity region 18 and an oxide capacitor Ci including insulating layer 19 between polycrystalline silicon gate 20 and N.sup.+ type impurity region 18. For this structure, the capacitance value per unit area can be increased and chip area can be reduced.
However, in the above structure, when alpha particles penetrate the surface of semiconductor substrate 11, it can create a significant number of electron-hole pairs near a storage node. Electrons, as minor carriers of the electron-hole pairs, are absorbed in N.sup.+ source region 12 to erroneously cause the memory data to change from "1" to "0" (i.e., a soft error). Also, when the memory cell is selected and transistor Q is conductive, the electrons created by the alpha particle radiation are absorbed in N.sup.+ impurity region 18 through drain region 13, channel region 14 and source region 12 causing the memory data to erroneously change from "1" to "0".
Furthermore, the concentration of source region 12 is higher than that of N.sup.+ impurity region 88. As a result, impurities are diffused in the lateral direction when source region 12 is formed. Therefore, N.sup.+ type impurity region 12' diffuses into P.sup.- type impurity region 17 as illustrated in FIG. 3. As a result, the contact area between P.sup.- type impurity region 17 and N.sup.+ type impurity region 18 is decreased, decreasing the memory capacitance.
Summary of the Invention
An object of this invention is to provide a semiconductor memory device and method of manufacturing the same with which an MOS capacitor is simply formed and has a simple structure, while preventing soft errors.
This is achieved in the present invention with a semiconductor substrate of a first conductive type on which a memory cell is formed. The memory cell has a switching MOS transistor with at least first impurity region of a second conductive type and a capacitance connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position completely separating the first impurity region from the substrate. In this manner, the invention makes it possible to prevent electrons created in the semiconductor substrate by alpha particle radiation from entering the first impurity region.
Brief Description of the Drawings
Other objects and advantages of the invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor memory device;
FIG. 2 is an equivalent circuit of the conventional device shown in FIG. 1;
FIG. 3 is a cross-sectional view illustrating another conventional semiconductor memory device;
FIGS. 4(a) through 4(f) are cross-sectional views showing the manufacturing steps to provide an embodiment of the semiconductor memory device in accordance with this invention; and
FIG. 5 shows the impurity concentration profile of the semiconductor surface shown in FIG. 4(f).
Detailed Description of the Preferred Embodiment
The present invention will now be described in detail according to a preferred embodiment, an example of which is illustrated in the accompanying drawings.
The embodiment of a semiconductor device according to the present invention is shown in FIGS. 4(a) through 4(f). FIGS. 4(a) through 4(f) are cross-sectional views showing the manufacturing steps.
First, as shown in FIG. 4(a), field insulation layers 22a, 22b consisting of an oxidation layer are formed by a selective oxidation method on a surface of a semiconductor substrate 21, for example a P.sup.- type silicon substrate. Semiconductor substrate 21 is made of silicon with a doping concentration of about 2.times.10.sup.15 cm.sup.-3.
Next, as shown in FIG. 4(b), an insulation layer (oxidation layer) 23 is formed on a surface of a cell region of semiconductor substrate 21 separated by field insulation layers 22a and 22b. Then P.sup.- type impurity region 24 and N.sup.+ impurity region 25 constituting a MOS capacitance C are formed by selectively ion implanting P type and N type impurity materials, for example boron and phosphorus, respectively, through insulation layer 23. With ion implantation, either P type impurity material or N type impurity material may be implanted into semiconductor substrate 21 before the other impurity material is implanted. The concentration of P.sup.- type impurity region 24 is about 10.sup.17 cm.sup.-3 and the concentration of N.sup.+ type impurity region 25 is about 10.sup.19 cm.sup.-3.
As shown in FIG. 4(c), a polycrystalline silicon layer 26 is deposited on the entire surface of semiconductor substrate 21. As shown in FIG. 4(d), polycrystalline silicon layer 26 and insulation layer 23 are selectively removed by a photo etching method according to a pattern so as to form an MOS capacitor C.
Next, as shown in FIG. 4(e), an insulation layer and a polycrystalline silicon layer are deposited on the surface of semiconductor substrate 21 and are selectively removed by a photo etching process. This forms a gate insulation layer 27 and a gate electrode 28 for a field insulation gate type transistor.
Next, as shown in FIG. 4(f), P.sup.- type impurity regions 29a, 29b and N.sup.- type third and fourth impurity regions 30a and 30b positioned within P.sup.- type impurity regions 29a, 29b are respectively formed by ion implanting P type impurity and N type impurity using gate electrode 28 as a mask. This completes the formation of field insulation gate type transistor Q. The impurity concentration of P.sup.- type impurity regions 29a and 29b and N.sup.- type impurity regions 30a and 30b of this transistor are about 10.sup.17 cm.sup.-3 and 10.sup.18 cm.sup.-3, respectively. And in case of ion implantation, either P type impurity or N type impurity may be implanted into the semiconductor substrate before the other impurity is implanted.
Drain region 30b, gate electrode 28 and electrode 26 of MOS capacitance C are respectively connected to bit line BL, word line WL and negative or positive power source Vs. Then the semiconductor memory device is completed.
FIG. 5 shows the impurity concentration profile of P.sup.- type impurity region 29a and N.sup.- impurity region 30a shown in FIG. 4(f). The lateral axis shows the depth from the substrate surface and the longitudinal axis shows the impurity concentration. Boron is used as the P type impurity material and phosphorus is used as the N type impurity material. Phosphorus, as the N type impurity material is better than arsenic with respect to the transistor characteristics.
As would be obvious to those skilled in the art studying FIG. 5, the peak impurity concentration of region 29a is located deeper from the surface of the device, in a direction toward substrate region 21, than that of 30a.
According to this structure, P.sup.- type impurity regions 24, 29a and 29b, having a higher impurity concentration than that of semiconductor substrate 11, are formed under and at the lateral sides of N.sup.+ type impurity region 25 and N.sup.- type impurity regions 30a and 30b, which have an opposite conductive type from semiconductor substrate 21. These regions 24, 29a and 29b are used as barriers for electrons and prevent the electrons of the electron-hole pairs, created by alpha particle radiation into semiconductor substrate 21, from reaching the cell region. As a result, soft errors produced by alpha particles are prevented and a semiconductor memory device having a high reliability is obtained.
Furthermore, the impurity concentration o third impurity region 30a shown in FIG. 4(f) is lower than that of the source region shown in FIG. 1 and FIG. 3 and lower than that of N.sup.+ impurity region 25 shown in FIG. 4(f). No impurities of third impurity region 30a diffuse into N.sup.+ impurity region 25 of MOS capacitor C during the formation of third impurity region 30a. Therefore, the capacitance of MOS capacitor C does not decrease.
Also, since impurity regions 30a and 30b of transistor Q are formed in a self-alignment manner using gate electrode 28 as a mask, the manufacturing process is simple.
As described in detail above, this invention makes it possible to obtain a semiconductor memory device and a method for manufacturing thereof with which a MOS capacitor is simply formed and has a simple structure, while preventing soft errors.
Although only a single preferred embodiment has been described in detail above, those skilled in the art will appreciate that many modifications are possible without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included in this invention as defined, by the following claims.
Claims
What is claimed is:
1. A semiconductor memory device comprising: a semiconductor substrate region of a first conductivity type; a memory cell including a switching MOS transistor having a first and a second impurity region of a second conductivity type and a capacitor connected to said transistor for storing memory data; and a third and a fourth impurity region of said first conductivity type, said third impurity region being formed between and entirely separating said substrate region from both said first impurity region and said capacitor and having a higher impurity concentration than that of said substrate region, said fourth impurity region being formed between and entirely separating said substrate region from said second impurity region and having a higher impurity concentration than that of said substrate region, said third and fourth regions enhancing radiation immunity of said memory device.
2. A semiconductor memory device of claim 1 wherein said capacitor includes a capacitance impurity region of said second conductivity type, said capacitance impurity region being disposed contiguous with and electrically contacting said third impurity region, said third impurity region being formed between and entirely separating said substrate region from said first impurity region and said capacitance impurity region.
3. A semiconductor memory device of claim 2 wherein an impurity concentration of said capacitance impurity region is higher than that of said first impurity region.
4. A semiconductor memory device of claim 1 wherein a peak impurity concentration of said third and fourth impurity regions is located deeper from a surface of said device in a direction toward said substrate region than that of said first and second impurity regions.
5. A semiconductor memory device comprising: a semiconductor substrate region of a first conductivity type; a first capacitance impurity region of said type and having a higher impurity concentration than that of said substrate region; a second capacitance impurity region of a second conductivity type, said first capacitance impurity region being between and entirely separating said second capacitance impurity region from said substrate region; a capacitance insulating film formed on said second capacitance impurity region; a capacitance electrode formed on said capacitance insulating film; a gate insulating film formed on a surface of said semiconductor substrate; a gate electrode formed on said gate insulating film, said gate electrode having a first and a second side; a first and a second impurity region, of said second conductivity type formed on said first and said second sides of said gate electrode, respectively, said first impurity region being adjacent to and contacting said second capacitance impurity region; and a third and fourth impurity region of said first conductivity type, said third impurity region being formed between and entirely separating said first impurity region from said substrate region and having a higher impurity concentration than that of said semiconductor substrate region, and said fourth impurity region being formed between and entirely separating said second impurity region from said substrate region and having a higher impurity concentration than that of said semiconductor substrate region, said third and fourth impurity regions enhancing radiation immunity of said memory device.
6. A semiconductor memory device of claim 5 wherein said impurity region first impurity region and said second impurity region form a switching MOS transistor with said gate insulating film and said gate electrode.
7. A semiconductor memory device of claim 6 wherein said first impurity region and said second capacitance impurity region are adjacent and an impurity concentration of said second capacitance impurity region is higher than that of said first impurity region.
8. A semiconductor memory device of claim 5 wherein a peak impurity concentration of said third impurity region is located deeper from a surface of said device in a direction toward said substrate region than that of said first impurity region.
Patent Citations (5)
Non-Patent Literature (7)
- Rideout, V. L., IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb. 1979 , "Double Polysilicon Dynamic RAM Cell With Increased Charge Stage Capacitance" pp. 3823-3825.
- IBM Technical Disclosure Bulletin, vol. 27, No. 7B, Dec. 1984, pp. 4463; 4464.
- IBM Technical Disclosure Bulletin, vol. 26, No. 5, Oct. 1983, pp. 2597-2599.
- Patents Abstracts of Japan, vol. 5, No. 34 (E-48) [706], Mar. 4, 1981.
- Patents Abstracts of Japan, vol. 7, No. 40 (E-159) [1185], Feb. 17, 1983.
- Patents Abstracts of Japan, vol. 9, No. 266 (E-352) [1989], Oct. 23, 1985.
- The HI-C Ram Cell Concept-Al F. Tasch, Member, IEEE Jr., et al. pp. 33-41.