Data Processing Apparatus

1. Field of the Invention

The present invention relates to a data processing apparatus for coding or decoding or the like of binary data in which binary data sequence is converted to a binary code sequence which is suitable for data processes in an electronic apparatus such as a magnetic disk, optical disk, data transmitting apparatus, or the like.

2. Description of the Prior Art

Hitherto, in electronic apparatuses such as a magnetic disk, optical disk, data transmitting apparatus, or the like, it is necessary to record or transmit a great amount of information. For instance, in recording, it is inevitable to improve recording density upon the recording of binary data on a recording medium.

On one hand, in transmitting, it is inevitable to improve transmission speed. In addition, various kinds of coding and decoding systems have been proposed.

FIG. 1 is a diagram for explaining one example of conventional coding systems. FIG. 1(a) shows an example of a bit pattern of an original binary data sequence, in which numerals 0 and 1 denote bit logics "0" and "1" and T.sub.0 represents a bit interval. FIGS. 1(b) and 1(d) respectively show one example of conventional coding systems, in which the system of FIG. 1(b) is called an MFM system (Modified FM system) and the system of FIG. 1(d) is called a 3PM system (3 Position Modulation system). When the recording technology is described, as an example of the apparatuses to which the foregoing respective systems are applied, the MFM system is used in the magnetic disk apparatuses (models 3330, 3340, 3350, etc.) made by IBM Corporation and the 3PM system is used in the magnetic disk apparatus (Model 8434) made by UNIVAC Corporation. For the algorithm of each system, in case of the MFM system, the original data "1" and "0" are converted to "01" and "X0" in correspondence thereto. However, in the coded sequence after conversion, " X" becomes a plurality of logics (1.fwdarw.0, 0.fwdarw.1) of the code bit immediately before X. On one hand, for the algorithm of the 3PM system, the original data is separated on a 3-bit unit basis and is converted to 6-bit codes as shown in Table 1.

For the coded sequence converted by each of the coding systems, a recording current is produced so as to become a signal such that the magnetization inversion occurs for a bit of "1" and the magnetization inversion does not occur for a bit of "0" and is recorded on the foregoing recording medium. FIGS. 1(c) and 1(e) show waveforms (NRZI signal) of the recording currents of the code systems which were coded by the MFM system of FIG. 1(b) and by the 3PM system of FIG. 1(d).

Generally, in the recording on the magnetic medium,

(a) When the magnetization inversion interval (recording wavelength) becomes short, the magnetic transitions due to the magnetization inversions before and after this interval are mutually interfered, thereby producing a cause for occurrence of errors upon decoding of the reproduction signal.

(b) Even in the case where a demodulation phase margin (TW) (which will be explained later) upon reproduction to the recording wavelength is small, the same errors as mentioned above could be easily caused.

(c) When the recording wavelength is larger as compared with the period of the clock signal for demodulation which is produced from the reproduction signal, the above-mentioned clock cannot be produced accurately from the reproduction signal, so that the same errors as mentioned above could be easily caused.

(d) When a ratio between the maximum value and the minimum value of the magnetization inversion interval becomes large, the waveform interference (called the pattern peak shift) of the reproduction signal increases, so that the same errors as mentioned above could be easily caused.

Thus, in the general coding systems, as the parameters indicative of the capabilities including the foregoing four items (a) to (d), the following variables are given. It is now assumed that in a certain coding system, the m-bit binary data sequence is converted to the binary code sequence of n (n.gtoreq.m) bits, and the minimum value of the number of codes of "0" between the code "1" selected arbitrarily from among the code sequence after conversion and the next code "1" is d and its maximum value is k. From this assumption, we have ##EQU1## where, T.sub.0 is one original data period.

Therefore, from the above description, it is desirable that the values of equations (1) and (4) are larger (from the explanations in the foregoing items (a) and (b)). On one hand, it is preferable that the value of the demodulation clock period in equation (3), the ratio of the maximum magnetization inversion interval (equation (5)) mentioned below and the ratio between the maximum and minimum magnetization inversion intervals (equation (6)) mentioned below are smaller. ##EQU2## The above-mentioned parameters are shown in Table 2 with regard to the foregoing MFM and 3PM coding systems.

In addition, as described above, in the general coding systems, original data is converted to the n-bit code for every m bits and is expressed as (m, n, d, k) codes in which the run length of "0" of the code after conversion is restricted to a value which is not smaller than d and not larger than k. However, the handling number m (m.ltoreq.n) of this data bit affects the hardware of the apparatus. In this case, it is generally desirable that a value of m is small. When the foregoing coding systems are expressed by the (m, n, d, k) parameters, they will become (1, 2, 0, 1) in case of the FM coding system; (1, 2, 1, 3) in case of the MFM coding system; and (3, 6, 2, 11) in case of the 3PM coding system. On one hand, what is called a DC free code of which a variation in DC component of the coded signal is suppressed is also generally desired.

It is an object of the present invention to provide a data processing apparatus in which: the T.sub.min is made as large as possible so as to avoid including the high frequency component and to reduce being subjected to the influence of the band restriction; the T.sub.W is made large so as to permit clear distinction of pulses; the difference between the T.sub.min and the T.sub.max is made small so that synchronization can be easily obtained; and the T.sub.max is made small to reduce the low frequency component in consideration of the foregoing points.

Another object of the invention is to make the magnetization inversion interval long and to prevent mutual interference between the magnetic transitions due to the magnetization inversions before and after that interval and thereby to prevent the occurrence of errors upon reproduction and decoding.

Still another object of the invention is to enlarge the demodulation phase margin (T.sub.W) (which will be explained later) upon reproduction, to a recording wavelength and thereby to prevent the occurrence of the foregoing errors.

Still another object of the invention is to make the recording wavelength small as compared with the period of a clock signal for demodulation which is produced from the reproduction signal and thereby to accurately produce a clock signal from the reproduction signal.

Still another object of the invention is to make the ratio between the maximum value and the minimum value of the magnetization inversion interval small and to also make the waveform interference (called the pattern peak shift) of the reproduction signal small and thereby to prevent the occurrence of the foregoing errors.

Still another object of the invention is to provide a data processing apparatus having a code converter which can be easily constituted by a programmable array logic.

Still another object of the invention is to provide a data processing apparatus which produces a DC-freed code.

Still another object of the invention is to provide a data processing apparatus which produces suitable codes due to a change-over of tables upon coupling of codes in consideration of the code before or after those codes.

Still another object of the invention is to provide a data processing apparatus which produces further DC-freed codes using a programmable array logic.

Still another object of the invention is to provide a data processing apparatus which has the codes corresponding to data in a table and codes the data by respectively performing the coordinating processes.

Still another object of the invention is to provide a data processing apparatus which has the codes corresponding to data in a table and codes the data by respectively performing the coordinating processes and thereby producing the further DC-freed codes.

FIG. 1 is an explanatory diagram of one example of conventional coding systems;

FIG. 2 is an arrangement block diagram of an electronic apparatus such as a magnetic disk, optical disk or the like which performs a digital modulation;

FIG. 3 is an arrangement diagram showing one example of a record-reproduction unit;

FIG. 4 is an explanatory diagram in the case where the limitation of k=2 is broken when two codes are coupled;

FIG. 5-1 is an explanatory diagram of the number of codes in which the limitation of k=2 is not broken;

FIG. 5-2 is a state transition diagram in production of codes;

FIG. 5-3 is a generalized state transition diagram in production of codes;

FIG. 6 is a diagram showing a method of producing the 6-bit k-limitation codes of k=2 of FIG. 5-1(c);

FIG. 7 is an arrangement block diagram for coding;

FIG. 8 is an arrangement block diagram of an NRZI converter;

FIG. 9 is a diagram showing an example of a circuit to generate four flag signals;

FIG. 10 is a diagram showing another arrangement example of the block diagram shown in FIG. 7;

FIG. 11 is a diagram showing the operation timing of the block diagram shown in FIG. 10;

FIG. 12 is an explanatory diagram of the code conversion from 8 bits to 13 bits and corresponds to the portion of a register and ROM table 31 in FIG. 7;

FIG. 13 is a diagram showing another embodiment of the code conversion from 8 bits to 13 bits;

FIG. 14 is an arrangement block diagram with respect to the code conversion from 4 bits to 5 bits;

FIG. 15 is an arrangement block diagram of the code conversion from 4 bits to 5 bits using a PAL;

FIG. 16 is an arrangement block diagram for the decoding which corresponds to the conversion of FIG. 15;

FIG. 17 is an arrangement block diagram of the conversion from 8 bits to 11 bits using the code conversion from 4 bits to 5 bits shown in FIG. 15 mentioned above;

FIG. 18 is an arrangement block diagram of the conversion from 3 bits to 5 bits;

FIG. 19 is an arrangement block diagram of the conversion from 4 bits to 7 bits;

FIG. 20 is an arrangement block diagram of the conversion from 5 bits to 6 bits;

FIG. 21 is an arrangement block diagram of the conversion from 5 bits to 7 bits;

FIG. 22 is an arrangement block diagram of the conversion from 6 bits to 7 bits;

FIG. 23 is an arrangement block diagram of the conversion from 6 bits to 8 bits;

FIG. 24 is an arrangement block diagram of the conversion from 7 bits to 8 bits;

FIG. 25 is an arrangement block diagram of the conversion from 7 bits to 9 bits;

FIG. 26 is an arrangement block diagram of the conversion from 8 bits to 9 bits;

FIG. 27 is an arrangement block diagram of the conversion from 8 bits to 14 bits;

FIG. 28 is an arrangement block diagram of the conversion from 8 bits to 16 bits; and

FIG. 29 is an arrangement block diagram of the conversion from 8 bits to 17 bits.

As already mentioned before, in general, in the coding systems, the original data of m bits is converted to the n-bit codes in which the number of bits of "0" which are included between the adjacent bits of "1" is restricted by d as the minimum number and k as the maximum number, and these codes are NRZI-converted so as to become a recording waveform pattern. Namely, the recording waveform pattern is constituted by the bits in which the code bit "1" is inverted and the code bit "0" is not inverted. Coding systems are generally expressed by four parameters of (m, n, d, k).

The terms using the above-mentioned parameters will then be explained.

T: Data bit interval

T.sub.min =m/n(d+1)T: Minimum inversion interval

T.sub.max =m/n(k+1)T: Maximum inversion interval

T.sub.W =m/nT: Detection window width (Demodulation phase margin)

DSV (Digital Sum Variation; variation in accumulated charges): Integrated value with respect to the recording waveform pattern in the case where the high level of the recording waveform pattern of which the code was NRZI-converted is +1 and the low level is -1.

When there is a possibility such that the DSV infinitely becomes large, its code has the DC component. When a variation range of the DSV is limited, its code is DC-free.

CDS (Codeword Digital Sum): DSV from the first to the last of one code.

The foregoing DC-free code will now be explained. This code is the code of which the accumulated charge variation (DSV: Digital Sum Variation) is limited. Assuming that the i-th digit of the recording pattern which appears as the j-th pattern among the recording pattern sequence of which the code sequence was NRZI-converted is W.sub.ji, the charge Q.sub.j of this recording pattern itself is expressed by ##EQU3## This equation means that the charge +1 is given when the digit W.sub.ji is 1 and the charge -1 is given when the digit W.sub.ji is 0. The accumulated charges until the i-th recording pattern are defined by ##EQU4## When the DSV is limited, it is said that the code is DC-free.

An explanation will be made hereinbelow using the above-mentioned symbols in consideration of the foregoing description.

As the conventional typical coding systems, the following systems can be mentioned.

(1) A. M. Patel, "Encoder and Decoder for a Byte-Oriented (0, 3) 8/9 code", IBM Technical Disclosure Bulletin, Vol. 18, No. 1, June 1975 (p. 248).

(2) A. M. Patel, "Charge-Constrained Byte-Oriented (0, 3) Code", IBM Technical Disclosure Bulletin, Vol. 19, No. 7, December 1976 (p. 2715).

The system (1) is the (8, 9, 0, 3) coding system. In the system (2), after the two (8, 9, 0, 3) codes of the coding system (1) were coupled, two connecting bits are added and thereby producing the DC-free code. As the result, the DC-free (8, 10, 0, 3) code is derived.

According to the system of (1),

According to the system of (2),

At the same time, they are DC-free. However, in this system, the connecting bits to make the code DC-free can be added only after two codes were coupled, namely, only after eighteen bits. Therefore, the variation range of the DSV (DC component of the signal) becomes large although it is limited. Thus, in the actual apparatuses such as a digital VTR or the like in which a high density recording is performed on the magnetic disk or the like, the DC component is cut out but in case of the optical disk, the DC component of the signal is not cut out. However, the reproducing amplifier uses the AC amplification, so that the DC component is cut out. Therefore, there is a problem such that a distortion is caused in the reproduction signal and this results in an increase in error rate upon decoding.

An important point in the coding systems is that the T.sub.min includes no high frequency component and it is better that a value of the T.sub.min is larger so as to reduce subjection to the influence of the band limitation. On the other hand, it is preferable that a value of the T.sub.W is larger so as to permit distinguishing pulses. In addition, it is desirable that a value of the T.sub.max is as small as possible and the difference between the T.sub.min and the T.sub.max is made small in order to make it easy to derive synchronization and to reduce the low frequency component.

The present invention will now be described in detail hereinbelow with reference to the drawings. FIG. 2 is an arrangement block diagram of an electronic apparatus such as a magnetic disk, optical disk or the like which performs the digital modulation. A reference numeral 1 denotes an information source or its input section, and 2 is an information source encoding section to suppress the redundancy of information in the information source 1. In the band compression, the transmission frequency band is analogly compressed. The high efficiency encoding intends to digitally reduce the average bit number per one pixel (sampled value) and is close to the amplitude compression from its meaning. A numeral 3 is a channel encoding section of communication and transmission lines in which error correction, digital modulation and the like are included; 4 is a record-reproduction system of the foregoing magnetic disk, optical disk or the like; 5 and 6 decoding sections to decode the data encoded by the encoding sections 2 and 3; and 7 an output section to output the information derived due to the above-mentioned processes.

FIG. 3 is an arrangement diagram showing one example of the record-reproduction unit 4 and illustrates an example of which the unit 4 is applied to a video disk.

The signal recording unit will be first explained. A light source 9, e.g., a semiconductor laser flickeringly emits a light in response to a drive signal from a signal source 8 on the basis of input data. The signal source 8 includes the encoding sections 2 and 3 in FIG. 2. The light beam emitted from the light source 9 becomes the parallel light beam by a collimator lens 10 and passes through a grating 11, a polarizing plate 12 and an optical device 13 whose transmittance reflectivity has a polarization dependency. Then, a point image is formed on a perpendicular magnetic recording medium 15 through an objective lens 14. The semiconductor laser beam has nearly P polarization to the optical device 13 and the polarizing plate 12 is also arranged so that its polarizing direction is directed in the P direction.

The grating 11 performs the luminous angle separation for allowing a sub-spot for detection of a tracking signal to be formed on the perpendicular magnetic recording medium 15 by the objective lens 14.

In this case, three point images are formed on the recording medium 15 due to the function of the grating 11. Among these three point images, the two point images which are used for detection of a tracking signal upon reproduction are the .+-.1 order diffracted lights of the grating 11 and the remaining one point image is the non-diffracted light (zero order light). By setting the diffraction efficiency due to the grating 11, the signal recording can be easily performed by the point image of only the non-diffracted light without performing the signal recording by the former two point images.

A combination of a cylindrical lens 16 and a quarter dividing detector 17 serves to derive an auto-focus (i.e., automatic focusing) signal for adjustment of the position of the objective lens 14 to allow the point image to be accurately formed in focus.

A signal from the quarter dividing detector 17 is divided into the signals of two systems by a signal distributor 18 and one of them is used for an auto-focus signal and the other is used to output and monitor a recording signal. This output includes the decoding sections 5 and 6 and information output section 7 described in FIG. 2.

On one hand, differential signals from detectors 19 and 20 for detection of a tracking signal are set into the OFF state upon recording.

The signal reproducing unit will then be described.

A signal at a constant level is given from the signal source 8, thereby setting the light source 9 into the light emitting state of a constant quantity of light. In addition, as mentioned before, the quantity of light in this case is adjusted to an amount of light of the order such that the magnetic domain pattern which was recorded as mentioned before is not inverted. The light beam transmitted through the collimator 10, grating 11, polarizing plate 12, and optical device 13 passes through the objective lens 14, so that three point images are formed on the recording medium. The light beam from the recording medium 15 has been subjected to the modulation of the polarization surface due to the Kerr effect and enters the detectors 17, 19 and 20 as the beam in the modulated state of brightness due to the system of the light beam splitting optical device 13 and an analyzer 21. The signal from the detector 17 is distributed into the two systems and one of them is used for the auto-focus signal and the other is used for the reproducing signal.

On the other hand, the signals of the detectors 19 and 20 are differentiated by a differential amplifier (AMP) 22. The objective lens is swung to the right and left in response to a signal of the differential AMP 22, therey performing the tracking.

In the reproducing unit, a brightness pattern with a high contrast can be detected due to the operation of the optical device 13.

As light quantity adjusting means between the recording and reproducing times, a Faraday rotating device may be inserted between the optical device 13 and the recording medium 15.

The Faraday rotating device is formed by, for example, YIG (yttrium, iron, garnet) crystal, glass of which rare earth was doped, or the like. By applying a magnetic field to this rotating device, the polarization surface of the luminous flux can be rotated. This Faraday rotating device is used because of the following reasons.

The polarizing direction of the reflected light from the recording medium 15 upon recording differs from the polarizing direction of the reflected light which was subjected to the Kerr rotation upon reproduction. Therefore, the reflected light beam is separated from the incident light beam by the light splitting optical device 13, so that the quantities of lights which transmit the analyzer 21 differ.

In addition, a quantity of light emission from the light source upon reproduction has to be reduced than that upon recording in order to prevent that the magnetic domain pattern recorded is inverted. Therefore, the quantities of lights which transmit the analyzer 21 upon recording and reproduction also differ due to this reason.

In the case where the quantities of light beams which are led through the cylindrical lens 16 to the quarter dividing detector 17 to detect the recording signal and auto-focus signal remarkably differ, it is necessary to change over the sensitivities of the detector 17 in dependence upon the recording and reproducing modes.

By properly applying a magnetic field to the Faraday rotating device upon recording, the polarization surface of the recording light beam is rotated, thereby adjusting the quantity of light which enters the detector 17 by means of a combination of the optical device 13 and analyzer 21 and thereby solving the foregoing problem.

In the embodiment, the video disk has been described. However, the invention is not limited to this example and can be also applied to the data processes in the network which is constituted by a work station, printer, host computer, disk apparatus, etc.

Next, the coding system (corresponding to the coding systems 1, 2 and 3 in FIG. 2) according to the present invention will be described.

According to D. T. Tang and L. R. Bahl, "Block Codes for a Class of Constrained Noiseless Channels", Information and Control, Vol. 17, 1970, p. 436, it is proved that the number of k-limitation codes having a length of n bits, namely, the number of codes in which d=0 and k is a limited value can be obtained by the following Nk(n). ##EQU5## The results of calculations using these equations are shown in Table 3.

It will be understood from this Table 3 that the number of codes in which k=2 (d=0) when n=10 is 504. However, as shown in FIG. 4, when these codes are coupled, there is a possibility such that the limitation of k=2 is broken in the coupling portion among the codes. Nevertheless, if the 10-bit code can be constituted as shown in FIG. 5-1, the limitation of k=2 is not broken even due to the coupling of the codes.

Practically speaking, FIG. 5-1 (a) shows the code in which the first bit is certainly "1" and the last bit is "1" and the intermediate eight bits are the k-limitation codes of k=2. The number of such codes which exist is 149 from Table 3. FIG. 5-1 (b) shows the code in which the first bit is certainly "1" and the last two bits are "1 0" and the intermediate seven bits are the k-limitation codes of k=2. The number of such codes which exist is 81 from Table 3. FIG. 5-1 (c) shows the code in which the first bit is certainly "1" and the last three bits are "1 0 0" and the intermediate six bits are the k-limitation codes of k=2. The number of such codes which exist is 44 from Table 3.

From the above explanation, the number of k-limitation codes constituted as shown in FIG. 5-1 in which the limitation of k=2 is not broken even if the codes are coupled is 274.

Next, the case where data is separated on an 8-bit unit basis and these are converted to the 10-bit codes will be considered. In this case, 2.sup.8 =256 kinds of 8-bit data exist and this number is smaller than the number of 274 of the 10-bit codes in FIG. 5-1. Therefore, it will be understood that by appropriately selecting 256 codes from among the 274 codes and by making these codes correspond to the 256 8-bit data so as to satisfy the one-to-one corresponding relation, the (m, n, d, k)=(8, 10, 0, 2) code can be realized. In case of converting the data each having eight bits into the 10-bit codes, the codes which are arbitrarily selected from the codes shown in Table 4 or 5 may be made correspond to the 2.sup.8 =256 codes when k=2. Such conversion tables may be provided in a ROM.

A method of producing code tables for the code conversion will then be described. Next, practical embodiments to produce the respective codes in FIGS. 5-1 (a), (b) and (c) will be explained with reference to a state transition diagram of FIG. 5-2. S.sub.1, S.sub.2 and S.sub.3 denote three states and S.sub.1 is the initial state. C represents a code bit. As one example, FIG. 6 shows a method of producing the 6-bit k-limitation code of k=2 shown in FIG. 5-1 (c). This producing method is also similar to the cases with regard to FIGS. 5-1 (a) and (b). FIG. 6 will now be practically explained.

As shown in FIG. 6, codes C.sub.1, C.sub.2, . . . , C.sub.6 are sequentially increased such that they are 000000, 000001, . . . and a check may be made to see if the state transition diagram of FIG. 5-2 is satisfied (the state does not advance to "STOP" in FIG. 5-2) or not. For example, in case of 000000, the state advances in the sequence of S.sub.1 .fwdarw.S.sub.2 .fwdarw.S.sub.3 and in the third state of "0", it advances to "STOP", so that it is found that this code does not satisfy FIG. 5-1 (c). The same shall apply to the other code conversions. FIG. 5-3 shows a state transition diagram for production of codes in the case where there is generally a limitation such that the minimum number of "0" which exists between "1" and "1" of the code is d and the maximum number is k. In other words, k+1 states are provided and in the states from state 1 (S.sub.1) to state d+1 (S.sub.d+1), if there is "1", the state goes out of the transition diagram and becomes "STOP". If the bit is "0", the state sequentially advances to the states S.sub.1, S.sub.2, . . . . In the states from state d+1 to state k+1, if the bit is "0", the state sequentially advances to the next state and when the bit "1" appears, the state is returned to S.sub.1. In the state k+1, if the "0" appears, the state goes out of the transition diagram and becomes "STOP". The code in the case where the state becomes "STOP" is the code which does not satisfy the limitation.

Next, an explanation will be made with respect to the case where the operation to produce the DC-free codes on one-code unit basis, namely, on a 10-bit unit basis is performed and the variation range of the DSV (Digital Sum Variation) is made small and thereby producing the DC-free codes having a large effect of suppression of the DC variation. FIG. 7 is an arrangement block diagram for encoding and shows the portions corresponding to 1, 2 and 3 in FIG. 2. The algorithm for encoding which is performed in the above block diagram will be first explained hereinbelow.

STEP 1: Set DSV=0 and P=0.

STEP 2: Convert the 8-bit data to the 10-bit codes (named W and the head bit (which is certainly 1) of the W is named W.sub.1) by the foregoing coding systems.

STEP 3: Calculate the CDS.

STEP 4:

(i) If P=0 and sign DSV=sign CDS, invert the W.sub.1 and set DSV=DSV-CDS.

(ii) If P=0 and sign DSV.noteq.sign CDS, set DSV=DSV+CDS without inverting the W.sub.1.

(iii) If P=1 and sign DSV=sign CDS, set DSV=DSV-CDS without inverting the W.sub.1.

(iv) If P=1 and sign DSV.noteq.sign CDS, invert the W.sub.1 and set DSV=DSV+CDS.

After completion of the operation in STEP 4, name the code W as W'.

P denotes a flag in which it is 0 when the number of "1" is an even number and it is 1 in case of an odd number. On one hand, it is assumed that the high level (1) of the binary signal of which the code W was NRZI-converted is +1 and the low level (0) is -1 and the value of the sum of them is the CDS (Codeword Digital Sum). It is now assumed in this case that the binary signal of which the code W was NRZI-converted starts from the low level. The sign (+ or -) of the polarity of the sign CDS is + when the CDS is 0.

STEP 5: P=P .sym. (P of W') Where, .sym. indicates an exclusive OR. The W' is outputted as the code.

STEP 6: Jump to STEP 2 in order to perform the next encoding.

FIG. 7 will then be explained on the basis of the description of the foregoing algorithm. Each 8-bit data inputted from an input terminal of .circle.A in FIG. 7 is inputted to a shift register 30. Then, the corresponding 10-bit code is read out from a ROM 31 by way of the foregoing look-up table method and is inputted in parallel to a shift register 32 (STEP 3 in the foregoing algorithm). This ten-bit code is also simultaneously inputted to a shift register 33. The 10-bit code loaded into the register 33 is supplied to an NRZI converter 34 and is NRZI-converted. The number of "1" of this NRZI-converted code is counted by a CDS counter A indicated at 35, while the number of "0" is counted by a CDS counter B indicated at 36. Their respective count values are stored in registers A and B indicated at 37 and 38 (STEP 3 in the foregoing algorithm). The NRZI converter 34 is constituted as shown in FIG. 8. In FIG. 8, .circle.C denotes an input terminal; 39 is an exclusive OR circuit; 40 a 1-bit delay device; and .circle.D is an output terminal. For the calculation of the CDS, it is derived by subtracting the content of the register B at 38 from the content of the register A at 37 by a subtraction unit 41 in FIG. 7. The result of subtraction is stored in a CDS register 42.

Next, in STEP 4 of the foregoing algorithm, the classification of the items (i) to (iv) takes the same value as

and its determination is performed by a logic circuit 43. P represents a value of 44 in FIG. 7 and takes a value of 1 or 0. C.sub.q is the MSB of the CDS register 42 and d.sub.q is the MSB of a DSV register 45. Since the content of the register is expressed by a complementary indication of 2, in case of comparing the signs of the DSV and CDS, c.sub.q and d.sub.q may be merely compared in order to indicate the number which becomes negative when the MSB is 1 and becomes positive when it is 0. .sym. represents the exclusive OR. On the basis of the foregoing four flag signals, when the flag of (i) is set, the logic circuit 43 allows the bit of W.sub.1 indicated at 46 to be inverted and permits the operation of DSV=DSV-CDS to be performed by an addition/subtraction unit 47 and stores the result of operation into the DSV register 45. FIG. 9 shows a practical example of the circuit to generate the foregoing four flag signals, but its details are omitted. As described above, STEP 4 is finished. In the next STEP 5, the code W' is outputted from the shift register 32 and is outputted from an output terminal .circle.E . At the same time, the number of "1" in the W' is checked to see if it is an even or odd number by a P flip flop A indicated at 48. Namely, when the number of "1" is an even number, the value of the flip flop 48 becomes 0 and when it is an odd number, the value becomes 1. This is attained by constituting the flip flop 48 in a manner such that its initial value is preset to 0 and it is inverted whenever "1" is inputted. The content of the flip flop 48 is stored in a buffer 49. In exclusive OR of the content of the buffer 49 and the content of the 44 is obtained by an exclusive OR circuit section 50 and its result is stored in the 44. In this way, STEP 5 is finished and the process routine is returned to STEP 2 and the similar processes are repeated.

As described in detail in the above, according to the (8, 10, 0, 2) code in the system of the invention,

According to the typical code (8, 9, 0, 3) in the conventional system,

For instance, when the conventional system is compared with the system of the invention, according to the present system, the T.sub.max can be remarkably reduced due to a slight decrease in T.sub.min or T.sub.W, so that there is an effect such that the synchronization can be easily obtained and the low frequency component is less. A similar effect is derived even if the present system is compared with other systems. In addition, the DC-free codes are realized using the (8, 10, 0, 2) code. On the other hand, in selection of 256 codes from among the 274 codes shown in FIG. 3, there is an effect such that by selecting 26 codes from the 194 codes in FIG. 5-1 (a), 81 codes in FIG. 5-1 (b) and code in FIG. 5-1 (c), it is possible to minimize the number of cases where the k-limitation is broken in the coupling portions of the codes, so that the coding can be efficiently performed.

Further, since the present system produces the codes on the basis of the (8, 10, 0, 2) code, there is a possibility such that the limitation of k=2 is broken only in the coupling portion of the 10-bit code. Therefore, there is an effect such that it is possible to produce the DC-free codes in which the low frequency component is fewer and the synchronization can be more easily derived as compared with the conventional systems.

In the present system, the operation to produce the DC-free codes on a one-code unit basis, namely, on a 10-bit unit basis (the operation to invert or non-invert the head bit W.sub.1 of the code) is performed; therefore, there is an effect such that it is possible to produce the DC-free codes in which the variation range of the DSV (Digital Sum Variation) is small and an effect of suppression of the DC variation is large. The present invention is not limited to the encoding from 8 bits to 10 bits. But, the invention can be similarly applied to the decoding by using inversely the invention,. Also, the invention is not limited to eight bits but it can be likewise applied to the encoding from four bits to five bits or other encoding, for instance, from three bits to seven bits or the like, or its decoding, respectively. As described above, according to the invention, it is possible to provide an electronic apparatus in which data can be processed very efficiently and with a high degree of accuracy.

FIG. 10 shows another arrangement example of the block diagram shown in FIG. 7, in which the hardware constitution to produce DC-free codes shown in FIG. 7 is constituted as a ROM. A numeral 30 similarly denotes the shift register to convert a serial data sequence 200 from the terminal .circle.A to a parallel data. This shift register is driven by a CLK 201, e.g., 8MbPS. The parallel outputs of the S/P converter 30 are latched by a latch 53 and the parallel outputs of the latch 53 are transferred to a ROM 50 in which the 8-10 conversion table is stored, a ROM 51 to output a word parity, and a ROM 52 to calculate the value of the foregoing CDS. Numeral 55, 56 and 57 indicate latch circuit sections. The outputs of the ROM 52 and latch section 57 are transferred through EX-OR circuits 61-68 to an addition/subtraction unit 54 to output the foregoing DSV. A numeral 58 is also a latch circuit section. The output code from the ROM 50 is transferred through the latch circuit section 55 to a parallelserial converter 59. However, the MSB of the code is inputted from a port Q.sub.10 of the latch circuit section 55 through a signal line 208 and an EX-OR circuit 75 to a port J of the P/S converter 59. A numeral 206 denotes a load signal to instruct the taking-in of those parallel signals (code). The serial data converted in response to a clock 205 is outputted at a port Q.sub.J and an output 204 of the P/S converter 59.

A numeral 203 is a clock input to drive the latch circuit sections 55, 56 and 57; 207 is a clock input to drive a flip flop 60 and a latch circuit section 58; and 69, 71, 73, 74, and 75 are EX-OR circuits. The operation of the block diagram will be explained in detail later.

FIG. 11 is an operation timing chart for the block diagram shown in FIG. 10. First, the (serial) data sequence is inputted to the S/P converter 30 as indicated at 200 by the CLK for data to transfer the data. The CLK 201 for the S/P converter 30 is the clock of which the foregoing CLK for data was inverted. On the basis of the CLK 201, the 8-bit serial data is converted to the 8-bit parallel data by the S/P converter 30. Thereafter, this parallel data is taken into the latch circuit section 53 by a read clock .circle.I of the CLK 53. Then, the data is transferred to the ROMs 50, 51 and 52 and is converted to a predetermined code. This code is latched by the latch circuit sections 55, 56 and 57 on the basis of an input of .circle.O (out clock) of the CLK 203 and is transferred to the P/S converter 59. Then, after an expiration of a predetermined time (after the elapse of three clocks in FIG. 11), the load signal 206 to output the data of the P/S converter 59 is outputted. The head bit of the code 204 is first outputted from 204 on the basis of the CLK 205 for code. At this time, one pulse of CLK to drive the latch 58 and flip flop 60 is generated and a signal for inversion or the like of the head bit of the code (which will be mentioned later) is outputted. Thereafter, the code of total ten bits is outputted from 204 in response to the CLK 205 for code. The above-mentioned inversion is controlled by inverting or non-inverting the W.sub.1 by use of the W.sub.1 which is always "1" because the head bit W.sub.1 is initially set to "1".

In the above-described arrangement, the code conversion from 8 bits to 10 bits and the foregoing algorithm to produce the DC-free codes will then be explained. First in STEP 1, the output of the DSV, namely, ports Q.sub.1 -Q.sub.8 .fwdarw.A.sub.1 -A.sub.8 of the addition/subtraction unit 54 and latch circuit section 58 are set to "0" and the P of the flip flop 60 is set to "0".

In the next STEP 2, the 10-bit code is outputted from the latch 55 due to the 8-10 bit conversion (output from the port Q.sub.10, and the head bit is set to W.sub.1).

In the next STEP 3, the CDS is calculated by the ROM 52 and latch 57.

The process in the next STEP 4 will be described in detail. The condition "(i) If P=0 and sign DSV=sign CDS, invert the W.sub.1 and set DSV=DSV-CDS." will now be described. With respect to the signs of the CDS and DSV, a check may be made to see if each output (0 (the sign is +) or 1 (the sign is -)) of the output port Q.sub.8 of the latch circuit section 57 and of the output port Q.sub.8 of the latch circuit portion 58 coincides or not. This discrimination is performed by the EX-OR circuit 69 to which signal lines 213 and 214 are connected. Namely, an output 215 of the EX-OR 69 becomes "0" when the signs of both of those outputs coincide and becomes "1" when they are not the same. When it is now assumed that the output 215 of the EX-OR circuit 69 is "0" and the parity of the code is an even number and "0", namely, when P=0 and sign DSV=sign CDS, an output of the EX-OR circuit 71 becomes "0" and an output of an inverter 72 becomes "1". Therefore, "1" is inputted to one input of the EX-OR circuit 75 through a signal 209, so that the output bit from the port Q.sub.10 of the latch 55 is inverted in response to an output of the EX-OR 75.

On one hand, since the output 215 is "0", an output 217 of an inverter 70 becomes "1". The outputs Q.sub.1 to Q.sub.8 of the latch circuit section 57 are respectively inputted to one input of each of the EX-OR circuits 61 to 68. In order to set all of the other inputs of the EX-OR circuits 61-68 to "1", the outputs of which those outputs Q.sub.1 -Q.sub.8 were inverted are obtained as the outputs of the EX-OR circuits 61-68 and its code is inputted to the addition/subtraction unit 54. This means that a complementary number of 2 is calculated. For instance, assuming that DSV=00000010 and CDS=00000001, DSV-CDS=00000001. First, all of the respective bits of the CDS are inverted and "1" is further added in response to the output 217 and a carry signal C.sub.0. Thus, CDS=11111111. Now, by adding the DSV and CDS by the addition/subtraction unit 54, we have 00000001 and the new DSV becomes DSV-CDS. As will be apparent from the above description, if P=0 and sign DSV=sign CDS, the W.sub.1 is inverted and DSV=DSV-CDS.

In a similar manner as above, the condition "(ii) If P=0 and sign DSV.noteq.sign CDS, set DSV=DSV+CDS without inverting the W.sub.1." will be explained. In the case where sign DSV.noteq.sign CDS, namely, in the case where the sign of the Q.sub.8 of the latch 58 which is the MSB of the DSV differs from the sign of the Q.sub.8 of the latch 57 which is the MSB of the CDS, that is, when the output 215 of the EX-OR circuit 69 is "1", an output 218 of the EX-OR circuit 71 becomes "1" since an output 216 of the flip flop 60 is "0" because P=0. Thus, an output of the inverter 72 becomes "0" and "0" is inputted to one input of the EX-OR circuit 75, so that the output of the EX-OR circuit 75 is outputted as it is without inverting the sign of the port Q.sub.10 of the latch circuit section 55, namely, without inverting the W.sub.1. On one hand, since the output 215 is "1" as mentioned above, the output 217 of the inverter 70 becomes "0" and the value of the CDS is inputted as it is to the addition/subtraction unit 54 different from the case of the condition (i). Thus, the new DSV is calculated as DSV=DSV+CDS. As will be obvious from the above description, when P=0 and sign CDS.noteq.sign DSV, the new DSV=DSV+CDS.

Next, the condition "(iii) If P=1 and sign DSV=sign CDS, set DSV=DSV-CDS without inverting the W.sub.1." will be explained. Since sign DSV=sign CDS, the output of the EX-OR 69 becomes "0". In addition, since P=1, the output 218 of the EX-OR 71 becomes "1" and the output of the inverter 72 becomes "0", and the W.sub.1 is not inverted as described in the foregoing condition (ii). On one hand, since the output of the inverter 70 becomes "1", all of the respective bits of the CDS are inverted and are further increased by +1 due to the carry signal C.sub.0 and a complementary number of 2 of the CDS is calculated, so that the new DSV=DSV-CDS.

Next, the condition "(iv) If P=1 and sign DSV.noteq.sign CDS, invert the W.sub.1 and set DSV=DSV+CDS." will be explained. Since sign DSV.noteq.sign CDS, the output 215 of the EX-OR 69 becomes "1". In addition, since P=1, the output of the EX-OR 71 is "0" and the output of the inverter 72 is "1", so that the W.sub.1 is inverted by the output of the EX-OR 75. On the other hand, since the output 215 is "1", the output of the inverter 70 becomes "0" and the value of the CDS is transferred as it is to the addition/subtraction unit 54, so that the new DSV=DSV+CDS.

The foregoing conditions will now be further described in detail. First, it is presumed that in the case where the DC component CDS of a word unit and the accumulated DC component DSV have the same sign, the DC component further has a tendency to increase, so that the new DSV is set to be equal to DSV-CDS in order to produce the DC-free codes, thereby reducing the DC component. On the other hand, in the case where both of them have the different signs, they are added as they are, namely, the new DSV is set to be equal to DSV+CDS, thereby reducing the DC component. This means that the sign of the CDS is switched by inverting the head bit W.sub.1 of the actual code. Namely, in the case where ##STR1## the CDS is obviously -2. However, when the head bit W.sub.1 of the W is inverted, ##STR2## because the W.sub.1 becomes "1", so that the value of the CDS becomes apparently +2. Therefore, it will be understood that the sign is inverted. Next, the relation between a parity P and the head bit W.sub.1 will be described. In the foregoing description of the W.sub.1, discrimination was made on the assumption that the first bit of the code is at a low level. However, there is a case where it is at a high level in dependence upon the one-preceding code. Namely, in case of the same W=0011, if the first bit is at a high level, ##STR3## Thus, CDS=+2. The level of this first bit relates to the parity P. In other words, the first level becomes high or low, respectively, in dependence upon whether the parity P before the code of which the value and sign of the CDS is changed over at present is an even or odd number. Namely, when the parity is an even number, the last bit becomes a high level as in the above-mentioned code "0 0 1 1". When it is an odd number, the code becomes, for instance, ##STR4## and the last bit becomes a low level.

The foregoing condition (i) will be further explained here. In the condition (i), since sign DSV=sign CDS, the absolute value of the CDS is subtracted from the value of the DSV to reduce the DC component. Now, since P=0, the value of the CDS is the normal value (the first reference level of the CDS is always set to low and the calculation is made), so that the head bit W.sub.1 is inverted to reverse the sign so as to become opposite to the sign of the DSV, then this inverted W.sub.1 is added to the DSV. The same shall be applied to the condition (iii) as well. However, since P=1, the values of the actual DSV and CDS have the opposite signs, so that the W.sub.1 is added as it is without being inverted. In case of the condition (ii), sign DSV.noteq.sign CDS; therefore, if P=0, the CDS and DSV are added as they are and then the absolute value of the CDS is subtracted from the DSV, thereby reducing the DC component. In the condition (iv), signal DSV.noteq.sign CDS similarly to the condition (ii). However, since P=1, the signs of the DSV and CDS are actually the same when the first level is considered, so that the W.sub.1 is inverted and added. In FIG. 10, the portion to change over from the previous parity to the next parity corresponds to the inversion/non-inversion of the W.sub.1. The output of the value of the next parity is produced when the previous parity output is 216 and the signal output to invert W.sub.1. The portion to make an inversion for the next parity corresponds to EX-OR 73. Refer to Table 8 for details.

Table 6 shows the comparison between the sign DSV and sign CDS described above. Table 7 shows the relation between the inversion and non-inversion of the W.sub.1. Table 8 shows the relation of the parities between the W and W'.

The arrangement described in FIG. 10 is not limited to 8 bits.fwdarw.10 bits but it is apparent that any other combination may be used.

Next, the code conversion from eight bits to thirteen bits will be described. In this case, the portions of the shift registers 30 and 32 and ROM 31 in FIG. 7 are constituted as shown in FIG. 12 and the conversion from 8 bits to 13 bits is performed.

In FIG. 12, a data sequence is inputted from .circle.a . This data sequence is inputted to an 8-bit shift resister 100. CK is an input terminal of a clock to drive the shift register 100. This clock signal is also simultaneously inputted to a counter 101. The counter 101 generates a pulse whenever it counts eight clocks. This pulse is inputted to a chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data of the shift register 100 is taken in a ROM 102, so that the address in the ROM corresponding to the data is designated. The 256 13-bit codes selected arbitrarily from Table 9 which will be shown later are stored in the 0th to 255th addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 13-bit code stored in this address is inputted to a shift register 103 and is outputted from a code output terminal .circle.b .

The 13-bit codes shown in Table 9 are the codes which are controlled in a manner such that the minimum number of bits "0" which exist between the adjacent bits "1" is one and the maximum number is seven. Arbitrary 13-bit codes which are selected from among the codes shown in Table 10 may be made coordinate with those 2.sup.8 =256 codes. There is also an effect such that this limitation is not broken even by the coupling of the 13-bit codes. Therefore,

Thus, the present system has an effect such that the T.sub.w is larger than that in the conventional FM or 3PM system and the T.sub.min is larger and the decoding error rate is smaller than those in the conventional MFM system. In addition, there is also an effect such that the T.sub.max is smaller and the synchronization can be more easily obtained as compared with the 3PM system.

FIG. 13 is an arrangement block diagram showing another embodiment of the code conversion from 8 bits to 13 bits. In FIG. 13, a data sequence is inputted from .circle.a . This data sequence is inputted to the 8-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever it counts the eight clocks and this pulse is inputted to a logic circuit 104.

The last four bits of the 13-bit code are observed and when the last one bit C-13 is "1", a chip selecting terminal CS.sub.1 to select Table 1 in the ROM 102 is set to ON. When the last two bits C-12 and C-13 are "1 0", a chip selecting terminal CS.sub.2 to select Table 2 is set to ON. When the last three bits C-11, C-12 and C-13 are "1 0 0", a chip selecting terminal CS.sub.3 to select Table 3 is set to ON. When the last four bits C-10 to C-13 are "1 0 0 0", a chip selecting terminal CS.sub.4 to select Table 4 is set to ON. The timing when each chip selecting terminal is set to ON is based on the time when the pulse is inputted from the counter 101 to the logic circuit 104. In other words, the chip selecting terminal is set to ON for the next code conversion. It will be obviously understood from the above description that such a logic circuit 104 can be easily realized.

As described above, either one of Tables 1 to 4 is selected and at this time, the 8-bit data in the 8-bit shift register 100 is taken into the ROM 102. The address in the Table corresponding to the data is designated. In Table 1, 256 13-bit codes which were arbitrarily selected from Table 10 are written. In Table 2, 256 13-bit codes which were arbitrarily selected from Table 11 are written. In Table 3, 256 13-bit codes which were arbitrarily selected from Table 12 are written. In Table 4, 256 13-bit codes which were arbitrarily selected from Table 13 are written.

When the address in the Table corresponding to the data is selected, the 13-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b . At this time, the last four bits C-10 to C-13 of the 13-bit code are observed by the logic circuit 104, thereby determining the Table to be selected next. In this way, the conversion from the data to the code, namely, the encoding process is finished. The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the above-mentioned conversion for encoding.

As described above, the coding system of the present invention is the (8, 13, 1, 5) coding system and

Therefore, the present system has effects such that: the T.sub.W is larger than that in the MFM or 3PM system; the T.sub.min is larger than that in the MFM system; the T.sub.max is smaller than that in the 3PM system; the decoding error rate is small; the low frequency component is few; and the synchronization can be more easily obtained as compared with the 3PM system. Consequently, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

In addition, the case where the 8-bit data is converted to the 13-bit code will be described further in detail. When the last one bit of the code which is preceding by one than the 2.sup.8 =256 8-bit data is "1", those 256 data are made coordinate with the 256 13-bit codes in Table 10 so as to satisfy the one-to-one corresponding relation. When the last two bits of the one-preceding code are "1 0", those 256 data are made coordinate with arbitrary 256 13-bit codes among the 402 13-bit codes in Table 11 so as to satisfy the one-to-one corresponding relation. When the last three bits of the one-preceding code are "1 0 0", those 256 data are made coordinate with arbitrary 256 13-bit codes among the 375 13-bit codes in Table 12 so as to satisfy the one-to-one corresponding relation. When the last four bits of the one-preceding code are "1 0 0 0", those 256 data are made coordinate with arbitrary 256 13-bit codes among the 333 13-bit codes in Table 13 so as to satisfy the one-to-one corresponding relation. On one hand, in the initial state in that the codes start, the foregoing one-preceding code does not exist. However, in such a case, it is assumed that the encoding is performed by specifying the state to either one of the conditions such that: the last one bit of the one-proceding code is "1", the last two bits are "1 0"; the last three bits are "1 0 0"; and the last four bits are "1 0 0 0".

The case where the 4-bit data is converted to the 5-bit code will then be described.

For instance, in the case where k=2, sixteen codes among the 17b-bit codes shown in Table 14 are made coordinate with the 2.sup.4 =16 4-bit data.

FIG. 14 is an arrangement block diagram for encoding from 4 bits to 5 bits according to the present invention. In FIG. 14, a data sequence is inputted from .circle.a . This data sequence is inputted to the 4-bit shift resistor 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever the four clocks are counted and this pulse is inputted to a chip selecting (CS) terminal. When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken into the ROM 102 and the address in the ROM corresponding to the data is designated. Sixteen 5-bit codes which were arbitrarily selected from Table 14 are stored in the 0th to 15th addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 5-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished. Upon foregoing encoding or the like, a CPU (not shown) may control the registers or the like. The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the above-mentioned conversion for encoding. The same shall be likewise applied to other bits. As described above, the 5-bit codes shown in Table 14 are the codes which are restricted in a manner such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is two. There is an effect such that this limitation is not broken even by coupling the bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is small as compared with the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily derived as compared with the MFM or 3PM system. Thus, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

Next, still another code conversion from 4 bits to 5 bits will be explained. First, the 4-bit data is expressed by D.sub.1, D.sub.2, D.sub.3, and D.sub.4 and the 5-bit code is represented by P.sub.1, P.sub.2, P.sub.3, P.sub.4, and P.sub.5. Now, assuming that A=D.sub.1 +D.sub.2 and B=D.sub.3 +D.sub.4 (+means OR), the code conversion is performed on the basis of the conversion table in Table 15-1 shown below. For example, in case of the condition AB=1 (AB denotes AND of A and B).

Namely, since (D.sub.1 +D.sub.2).multidot.(D.sub.3 +D.sub.4)=1, either D.sub.1 or D.sub.2 is 1 and either D.sub.3 or D.sub.4 is 1. As will be obvious from Table 15-1, the conversion code (P.sub.1 to P.sub.5) becomes 1, D.sub.1, D.sub.2, D.sub.3, and D.sub.4. In addition, "A" denotes a negation of A.

When Table 15-1 is expressed by logical expressions, it will be as shown in Table 15-2.

For instance, the logical expression to determine the P.sub.2 is

However, when AB=1, A=B=1, so that AB=AB=0 and P.sub.2 =D.sub.1. In addition, when AB=1, A=0 and B=1, so that AB=AB=0 and P.sub.2 =1. In this way, Table 15-2 relates to the operations of only AND, OR and NOT, so that it is apparent that these operations can be constituted by the PAL (Programmable Array Logic) without storing the conversion program into the ROM or the like. On one hand, since either D.sub.1 or D.sub.2 and either D.sub.4 or D.sub.5 may be 1, respectively, it will be obviously understood that the D.sub.2 and D.sub.1 may be substituted for the P.sub.2 and P.sub.3 and the D.sub.4 and D.sub.3 may be substituted for the P.sub.4 and P.sub.5, respectively, in Table 15-1. Similarly, from the condition AB=1, A= 1 and B=1 and either D.sub.3 or D.sub.4 is 1. Therefore, it is enough that the limitation of k=2 is satisfied, so that when AB=1 in Table 15-1, the P.sub.3 may be either 0 or 1. Also, the P.sub.4 and P.sub.5 may be D.sub.4 and D.sub.3, respectively. Likewise, in the case where AB=1, either D.sub.1 or D.sub.2 may be 1, so that the P.sub.3 may be either 0 or 1. The P.sub.4 and P.sub.5 may be D.sub.2 and D.sub.1, respectively. In the condition of AB=1, A=0 and B=0, so that all of the D.sub.1, D.sub.2, D.sub.3, and D.sub.4 are 0. It is enough that the limitation of k=2 is satisfied, so that the P.sub.5 may be 0. The above description can be summarized as shown in Tables 15-3 to 15-7. In these Tables, the blank portions are the same as those in Table 15-1.

FIG. 15 then shows an example of the encoder to realize the code conversion based on the conversion table shown in FIG. 15-1.

Data is inputted from .circle.a to the 4-bit shift register 100. The four-bit data D.sub.1, D.sub.2, D.sub.3, and D.sub.4 inputted to the shift register 100 are subjected to the logic operations shown in Table 15-2 by a PAL circuit 200. Then, the data is inputted in parallel to the 5-bit shift register 103 and is serially outputted as the code from .circle.b .

It is obvious that the code conversions can be also realized with respect to the conversion tables in Tables 15-3 to 15-7 due to the similar idea. Therefore, their descriptions are omitted here.

Next, the decoding system corresponding to the encoding shown in Table 15-1 will be explained. This decoding system can be likewise applied to Tables 15-3 to 15-7. Table 16-1 shows a conversion table for the decoding. Table 16-2 shows logical expressions to execute the conversion table in Table 16-1.

For instance, the logical expression to determine the D.sub.1 in Table 16-2 is

When P.sub.1 (P.sub.2 +P.sub.3)=1, P.sub.1 =1, so that P.sub.1 P.sub.3 =0 and D.sub.1 =P.sub.2. On one hand, when P.sub.1 P.sub.3 =1, P.sub.1 =P.sub.3 =0, so that P.sub.1 (P.sub.2 +P.sub.3)=P.sub.1 P.sub.3 =0 and D.sub.1 =0. As described above, Table 16-2 shows the operations of only AND, OR and NOT; therefore, it is obvious that those operations can be constituted by the PAL (Programmable Array Logic). FIG. 16 shows an embodiment of Table 16-2. A code is inputted from .circle.c into the 5-bit shift register 103. The 5-bit code P.sub.1, P.sub.2, P.sub.3, P.sub.4, and P.sub.5 inputted to the shift register is subjected to the logic operations in Table 16-2 by the PAL circuit 201 and is inputted in parallel to the 4-bit shift register 100 and is serially outputted as the decoded data from .circle.d .

Next, the case where the 8-bit (b bits+4 bits) data is converted to the code of 11 bits (5 bits+5 bits+one coupling bit L indicated at 220) as shown in FIG. 17 by applying the arrangement shown in FIG. 15 will be described.

The data inputted from the input terminal .circle.A in FIG. 17 is inputted to two 4-bit shift registers 202 and 203 and is converted by PALs 204 and 205 due to any of the coding systems shown in Tables 15-3 to 15-7. This code is then inputted in parallel to two 5-bit shift registers 206 and 207. This 10-bit code is also simultaneously inputted to 5-bit shift registers 208 and 209. In this embodiment, the data of two blocks is considered to be one data and the code conversion was performed. However, the number of blocks is not limited to two but may be apparently set to any number. The 10-bit code loaded in the registers 208 and 209 is supplied to the NRZI converter 34, by which it is NRZI-converted. The number of bits "1" of this NRZI-converted code is counted by the CDS counter A indicated at 35, while the number of bits "0" is counted by the CDS counter B at 36. The respective count values are loaded into the registers A and B indicated at 37 and 38.

The above description is substantially the same as the explanation in conjunction with FIG. 7; therefore, its details are omitted here. Now, the algorithm (Table 17) to produce the DC-free codes relative to the coupling bit L indicated at 220 will be explained. Its details have been already described with reference to FIG. 7; therefore, they are omitted here.

A different point from the algorithm relative to FIG. 7 is merely concerned with the W.sub.1 and the code switching to produce the DC-free codes is performed by the coupling bit L in place of the W.sub.1. In STEP 5, the P is determined by the EX-OR of the 11-bit code LW which is constituted by adding the bit L to the 10-bit code W and the previous P.

As described in detail above, when the examples of the coding systems shown in Tables 15-3 to 15-7 are compared with the encoding by the conventional MFM or

3PM system, they will become as shown in Table 18.

It will be appreciated from Table 18 that although the T.sub.W is too smaller than the T.sub.min in the conventional systems, the present system has an effect such that the T.sub.W is so large to be 0.8T.sub.0 and the error rate can be reduced as compared with the conventional systems and that the ratios of T.sub.max /C.sub.LK and T.sub.max /T.sub.min are together so small to be 3 and the synchronization can be extremely easily obtained. In addition, the conversion from the 4-bit data to the 5-bit code can be realized by a simple logic circuit, so that the present invention has also a large advantage such that it is suitable to realize an LSI. Further, the absolute value of the DSV can be suppressed to a value within a limited range by inserting only one coupling bit L so as to allow the next code W to be coupled in order to reduce an increase in DSV in STEP 4 in the encoding algorithm in Table 17 or to invert its sign, so that there is an effect such that the DC-free codes can be realized. On the other hand, there is an effect such that by setting l in STEP 2 to a large value, almost of the parameters (Table 18) of the coding systems shown in Tables 15-3 to 15-7 can be held.

As described above, according to the invention, it is possible to provide a data processing apparatus in which the data processes can be performed very efficiently with a high degree of accuracy.

[3.fwdarw.5]

Next, the case where three-bit data of a binary data sequence is converted to the code consisting of five bits will be described.

In case of converting the 3-bit data to the 5-bit code, for instance, assuming that k=1, eight 5-bit codds may be made coordinate with the 2.sup.3 =8 3-bit data as shown in Table 19.

FIG. 18 is an arrangement block diagram for encoding of the present invention.

In the diagram, a data sequence is inputted from .circle.a . This data sequence is inputted to the 3-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever the three clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Eight 5-bit codes which were arbitrarily selected from Table 19 are stored in the 0th to 7th addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 5-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished. Upon the foregoing encoding or the like, a CPU (not shown) may control the registers or the like. In addition, the conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 5-bit codes shown in Table 19 are the codes which were restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is one. There is an effect such that this limitation is not broken even by coupling the 5-bit codes.

Therefore,

Consequently, the present system has effects such that: The T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide a data processing system in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[4.fwdarw.7]

Next, the case of converting the four-bit data of the binary data sequence to the code consisting of seven bits will be described.

In case of converting the 4-bit data to the 7-bit code, when k=1, codes which were arbitrarily selected from the 7-bit codes shown in Table 20 may be made coordinate with the 2.sup.4 =16 data.

FIG. 19 is an arrangement block diagram for encoding of the present invention. In FIG. 19, a data sequence is inputted from .circle.a . This data sequence is inputted to the 4-bit register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever four clocks are counted and this pulse is inputted to the chip selecting (CS) terminal. When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Sixteen 7-bit codes which were arbitrarily selected from Table 20 are stored in the 0th to 15th addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 7-bit code stored in that address is inputted t the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 7-bit codes shown in Table 20 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is one. There is an effect such that this limitation is not broken even by coupling the 7-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

FIG. 20 is an arrangement block diagram for encoding of the present invention. In FIG. 20, a data sequence is inputted from .circle.a . This data sequence is inputted to the 5-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever five clocks are counted and this pulse is inputted to the chip selecting (CS) terminal. When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Thirty-two 6-bit codes which are arbitrarily selected from Table 21 are stored in the 0th to 31st addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 6-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 6-bit codes shown in Table 21 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is three. There is an effect such that this limitation is not broken even by coupling the 6-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[5.fwdarw.6]

In case of converting the 5-bit data to the 6-bit code, for instance, when k=3, thirty-two codes which are arbitrarily selected from the 41 6-bit codes as shown in Table 21 may be made coordinate with the 2.sup.5 =32 5-bit data.

[5.fwdarw.7]

In case of converting the 5-bit data to the 7-bit code, for instance, when k=2, thirty-two 7-bit codes which are arbitrarily selected from the 7-bit codes shown in Table 22 or 23 may be made coordinate with the 2.sup.5 =32 5-bit data.

FIG. 21 is an arrangement block diagram for encoding of the present invention. In FIG. 21, a data sequence is inputted from .circle.a . This data sequence is inputted to the 5-bit shift register 100, CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever five clocks are counted and this pulse is inputted to the chip selecting (CS) terminal. When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 103 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Thirty-two 7-bit codes which were arbitrarily selected from Table 22 or 23 are stored in the 0th to 31st addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 7-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 7-bit codes shown in Tables 22 and 23 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is two. There is an effect such that this limitation is not broken even by coupling the 7-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[6.fwdarw.7]

In case of converting the 6-bit data to the 7-bit code, when k=3, sixty-four 7-bit codes which are arbitrarily selected from the 7-bit codes shown in Table 24 may be made to coordinate with the 2.sup.6 =64 6-bit data.

FIG. 22 is an arrangement block diagram for encoding of the present invention.

In FIG. 22, a data sequence is inputted from .circle.a . This data sequence is inputted to the 6-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever six clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Sixty-four 7-bit codes which were arbitrarily selected from Table 24 are stored in the 0th to 63rd addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 7-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 7-bit codes shown in Table 24 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is three. There is an effect such that this limitation is not broken even by coupling the 7-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[6.fwdarw.8]

In case of converting the 6-bit data to the 8-bit code, when k=2, sixty-four 8-bit codes which are arbitrarily selected from the 8-bit codes shown in Table 25 or 26 may be made coordinate with the 2.sup.6 =64 6-bit data.

FIG. 23 is an arrangement block diagram for encoding of the present invention. In FIG. 23, a data sequence is inputted from .circle.a . This data sequence is inputted to the 6-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever six clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. Thirty-two 8-bit codes which were arbitrarily selected from Table 25 or 26 are stored in the 0th to 63rd addresses in the ROM. When the address in the ROM corresponding to the data is designated, the 8-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 8-bit codes shown in Tables 25 and 26 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is two. There is an effect such that this limitation is not broken even by coupling the 8-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[7.fwdarw.8]

In case of converting the 7-bit data to the 8-bit code, when k=3, 128 8-bit codes which are arbitrarily selected from the 8-bit codes shown in Table 27 may be made coordinate with the 2.sup.7 =128 data.

FIG. 24 is an arrangement block diagram for encoding of the present invention.

In FIG. 24, a data sequence is inputted from .circle.a . This data sequence is inputted to the 7-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever seven clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. In the 0th to 127th addresses in the ROM, 128 8-bit codes which were arbitrarily selected from Table 27 are stored. When the address in the ROM corresponding to the data is designated, the 8-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 8-bit codes shown in Table 27 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is three. There is an effect such that this limitation is not broken even by coupling the 8-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[7.fwdarw.9]

In case of converting the 7-bit data to the 9-bit code, when k=2, 128 9-bit codes which are arbitrarily selected from the 9-bit codes shown in Table 28 or 29 may be made coordinate with the 2.sup.7 =128 data.

FIG. 25 is an arrangement block diagram for encoding of the present invention. In FIG. 25, a data sequence is inputted from .circle.a . This data sequence is inputted to the 7-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever seven clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. In the 0th to 127th addresses in the ROM, 128 9-bit codes which were arbitrarily selected from Table 28 or 29 are stored. When the address in the ROM corresponding to the data is designated, the 9-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 9-bit codes shown in Tables 28 and 29 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is two. There is an effect such that this limitation is not broken even by coupling the 9-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[8.fwdarw.9]

In case of converting the 8-bit data to the 9-bit code, when k=3, 256 9-bit codes which are arbitrarily selected from the 9-bit codes shown in Table 30 may be made coordinate with the 2.sup.8 =256 data.

FIG. 26 is an arrangement block diagram for encoding of the present invention. In FIG. 26, a data sequence is inputted from .circle.a . This data sequence is inputted to the 8-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever eight clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. In the 0th to 255th addresses in the ROM, 256 9-bit codes which are arbitrarily selected from Table 30 are stored. When the address in the ROM corresponding to the data is designated, the 9-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 9-bit codes shown in Table 30 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is zero and the maximum number is three. There is an effect such that this limitation is not broken even by coupling the 9-bit codes.

Therefore,

Consequently, the present system has effects such that: the T.sub.min and T.sub.W are larger and the decoding error rate is smaller than those in the conventional FM system; the low frequency component of the recording waveform is few; and the synchronization can be more easily obtained as compared with the MFM or 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[8.fwdarw.14]

In case of converting the 8-bit data to the 14-bit code, when the last one bit of the code which is preceding by one than the 2.sup.8 =256 8-bit data is "1", 275 14-bit codes shown in Table 31 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last two bits of the one-preceding code are "1 0", arbitrary 256 14-bit codes among the 426 14-bit codes shown in Table 32 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last three bits of the one-preceding code are "1 0 0", arbitrary 256 14-bit codes among the 376 14-bit codes shown in Table 33 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. On the other hand, in the initial state in that the codes start, the abovementioned one-preceding code does not exist. However, in this case, it is assumed that the encoding is performed by specifying the state to either one of the conditions whereby: the last one bit of the one-preceding code is "1"; the last two bits are "1 0"; and the last three bits are "1 0 0".

FIG. 27 is an arrangement block diagram for encoding of the present invention. In FIG. 27, a data sequence is inputted from .circle.a . This data sequence is inputted to the 8-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever eight clocks are counted and this pulse is inputted (CS) to the logic circuit 104. The last three bits of the 14-bit code are observed. When the last one bit C-14 is "1", the chip selecting terminal CS.sub.1 to select Table 1 in the ROM 102 is set to ON. When the last two bits C-13 and C-14 are "1 0", the chip selecting terminal CS.sub.2 to select Table 2 is set to ON. When the last three bits C-12, C-13 and C-14 are "1 0 0", the chip selecting terminal CS.sub.3 to select Table 3 is set to ON. The timing when each chip selecting terminal is set to ON is based on the time when the pulse is inputted from the counter 101 to the logic circuit 104. It is obvious that such a logic circuit 104 can be easily realized.

As described above, either one of Table 1 to 3 is selected and at this time, the 8-bit data in the 8-bit shift register 100 is taken in the ROM 102. The address in the table corresponding to the data is designated. In Table 1, 256 14-bit codes which were arbitrarily selected from Table 31 are stored. In Table 2, 256 14-bit codes which were arbitrarily selected from Table 32 are stored. In Table 3, 256 14-bit codes which were arbitrarily selected from Table 33 are stored. When the address in the table corresponding to the data is designated, the 14-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b . In this case, the last three bits, i.e., C-12, C-13 and C-14 of the 14-bit code are observed by the logic circuit 104, thereby determining the table to be selected next. In this way, the conversion from the data to the code, namely, the encoding is finished. The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the coding system of the invention is the (8, 14, 14) coding system and

Consequently, the present system has effects such that: the T.sub.W is larger than that of the MFM or 3PM system; the T.sub.max is smaller and the decoding error rate is smaller than those in the 3PM system; the low frequency component is small; and the synchronization can be more easily obtained as compared with the 3PM system. Therefore, it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.

[8.fwdarw.16]

In case of converting the 8-bit data to the 16-bit code, when the last one bit of the one-preceding code is "1", 256 16-bit codes shown in Table 34 are made coordinate with the 2.sup.8 =256 8-bit data so as to satisfy the one-to-one corresponding relation. When the last two bits of the one-preceding code are "1 0", arbitrary 256 16-bit codes among the 375 16-bit codes shown in Table 35 are made coordinate with those 256 data so as to satisfy the one-to one corresponding relation. When the last three bits of the one-preceding code are "1 0 0", arbitrary 256 16-bit codes among the 546 16-bit codes shown in Table 36 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last four bits of the one-preceding code are "1 0 0 0", arbitrary 256 16-bit among the 537 16-bit codes shown in Table 37 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. On one hand, when the last five bits of the one-preceding code are "1 0 0 0 0 0", arbitrary 256 16-bit codes among the 524 16-bit codes shown in Table 38 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last six bits are "1 0 0 0 0 0", arbitrary 256 16-bit codes among the 506 16-bit codes shown in Table 39 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last seven bits are "1 0 0 0 0 0 0", arbitrary 256 16-bit codes among the 479 16-bit codes shown in Table 40 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. Further, when the last eight bits of the one-preceding code are "1 0 0 0 0 0 0 0", arbitrary 256 16-bit codes among the 439 16-bit codes shown in Table 41 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation. When the last nine bits are "1 0 0 0 0 0 0 0 0", arbitrary 256 16-bit codes among the 382 16-bit codes shown in Table 42 are made coordinate with those 256 data so as to satisfy the one-to-one corresponding relation.

in the initial state in that the codes start, the above-mentioned one-preceding code does not exist. However, in this case, it is assumed that the encoding is performed by specifying the state to either one of the conditions whereby: the last one bit of the one-preceding code is "1"; the last two bits are "1 0"; the last three bits are "1 0 0"; the last four bits are "1 0 0 0"; the last five bits are "1 0 0 0 0 "; the last six bits are "1 0 0 0 0 0: the last seven bits are "1 0 0 0 0 0 0"; the last eight bits are "1 0 0 0 0 0 0 0"; and the last nine bits are "1 0 0 0 0 0 0 0 0".

FIG. 28 is an arrangement block diagram for encoding of the present invention. In FIG. 28, a data sequence is inputted from .circle.a . This data sequence is inputted to the 8-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever eight clocks are counted and this pulse is inputted to the logic circuit 104.

The last nine bits of the 16-bit code are observed. When the last one bit C-16 is "1", the chip selecting terminal CS.sub.1 to select Table 1 in the ROM 102 is set to ON. When the last two bits C-15 and C-16 are "1 0", the chip selecting terminal CS.sub.2 to select Table 2 is set to ON. When the last three bits C-14, C-15 and C-16 are "1 0 0", the chip selecting terminal CS.sub.3 to select Table 3 is set to ON. Although the descriptions with respect to intermediate Tables 4 to 8 are omitted here, when the last nine bits C-8 to C-16 are "1 0 0 0 0 0 0 0 0", the chip selecting terminal CS.sub.9 to select Table 9 is similarly set to ON. In this case, the timing when each chip selecting terminal is set to ON is based on the time when the pulse is inputted from the counter 101 to the logic circuit 104. It is obvious that such a logic circuit 104 can be easily realized.

As described above, either one of Tables 1 to 9 is selected and at this time, the 8-bit data in the 8-bit shift register 100 is taken in the ROM 102. The address in the table corresponding to the data is designated. In Table 1, 256 16-bit codes which were arbitrarily selected from Table 34 are stored. In Table 2, 256 16-bit data which were arbitrarily selected from Table 35 are stored. In Table 3, 256 16-bit codes which were arbitrarily selected from Table 36 are stored. In a similar manner as above, 256 16-bit codes which were arbitrarily selected from Table 42 are stored in Table 9.

When the address in the table corresponding to the data is designated, the 16-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b . In this case, the last nine bits of the 16-bit code, namely, C-8 to C-16 are observed by the logic circuit 104, thereby determining the table to be selected next. In this way, the conversion from the data to the code, namely, the encoding is finished. The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion encoding.

As described above, the coding system of the present invention is the (8, 16, 2, 10) coding system and

Consequently, the present system has an effect such that the T.sub.W and T.sub.min are larger than those in the MFM system. Therefore, it is possible to provide an electronic apparatus in which the reciording and/or reproduction can be performed with a high density and a high degree of accuracy.

[8.fwdarw.17]

In case of converting the 8-bit data to the 17-bit code, arbitrary 17-bit codes which are selected from the 17-bit codes shown in Tables 43, 44, 45, 46, and 47 may be made coordinate with the 2.sup.8 =256 data.

FIG. 29 is an arrangement block diagram for encoding of the present invention. In FIG. 29, a data sequence is inputted from .circle.a . This data sequence is inputted to the 8-bit shift register 100. CK is the input terminal of the clock to drive the shift register 100. This clock signal is also simultaneously inputted to the counter 101. The counter 101 generates a pulse whenever eight clocks are counted and this pulse is inputted to the chip selecting (CS) terminal.

When the pulse is inputted to the chip selecting (CS) terminal, the data in the shift register 100 is taken in the ROM 102, so that the address in the ROM corresponding to the data is designated. in the 0th to 255th addresses in the ROM, 256 17-bit codes which were arbitrarily selected from Tables 43 to 47 are stored. When the address in the ROM corresponding to the data is designated, the 17-bit code stored in that address is inputted to the shift register 103 and is outputted from the code output terminal .circle.b .

In this way, the conversion from the data to the code, namely, the encoding is finished.

The conversion from the code to the data which is performed on the reproducing side, namely, the decoding may be attained by performing the conversion opposite to the foregoing conversion for encoding.

As described above, the 17-bit codes shown in Tables 43 to 47 are the codes which are restricted such that the minimum number of bits "0" which exist between the adjacent bits "1" is two and the maximum number is ten. There is an effect such that this limitation is not broken even by coupling the 17-bit codes.

Therefore,

On the other hand, there is an EFM system which has been developed cooperatively by Sony Corporation and Phillips Co., Ltd. and this EFM system has been adopted to a compact disc or digital audio. The system of the present invention is much simpler than this (8, 17, 2, 10) system and it is possible to provide an electronic apparatus in which the recording and/or reproduction can be performed with a high density and a high degree of accuracy.