System Structure Recognition Method for a Multiloop Transmission System

This invention relates to a system structure recognition method for a multiloop transmission system consisting of a plurality of loop transmission groups and more in detail to a method for recognizing the structure of devices connected to form a plurality of interconnected transmission loops by means of messages circulating through the loops.

Japanese Patent Application Kokai (un-examined publication) No. Shoo 57-166756 has disclosed a multiloop transmission system, where a plurality of loops are connected to each other, and where message transmission between different loops is effected, depending on the content of data, without knowing the structure of the loops and the address of the receiver. Although this method has an advantage easily controlling which messages are to be transferred between different loops depending on circumstances and another advantage that it is not necessary to provide network control processors for the relay operation, it has a problematical point with respect to maintenance of the system, because there are no measures for recognizing at any time with what system structure this multiloop system is operated. Message transmission between different transmission control devices connected to a single loop transmission system is described in U.S. Pat. No. 4,366,479.

The object of this invention is to provide a method which makes it possible to resolve the problem of the prior art techniques described above and to recognize the system structure of a multiloop system at an arbitrary point of time.

According to this invention, when each of the network control processors (hereinbelow abbreviated to NCP) connected to each of the loops receives a message for recognizing the system structure called a loop train, it adds its own address to a message and makes it flow to other loops. Further, a relay processor connected between two loops adds a flag representing a relay to each of the loop train messages coming from an NCP connected with the relay processor itself and sends it to other loops. The structure of the multiloop system is recognized by using the message returning after having circulated through all of the loop transmission lines.

FIG. 1 is a scheme for explaining a system, to which this invention is applied;

FIG. 2 shows the format for the messages sent to the transmission loops;

FIG. 3a is a scheme illustrating the path of the messages flowing through the system indicated in FIG. 1;

FIG. 3b illustrates address series data obtained after a circulation of the train message through the

FIGS. 4a-4e illustrate data analysis areas in a system tester;

FIG. 5 indicates steps for the treatment of the address series analysis;

FIG. 6a illustrates address series data obtained after a circulation of the train message through the system;

FIGS. 6b and 6c illustrate data areas indicating the process of the address series analysis;

FIG. 7 indicates steps for displaying a result of the analysis; and

FIG. 8 is a scheme for explaining a system, to which this invention is applied.

Hereinbelow this invention will be explained more in detail by using some embodiments.

FIG. 1 is a scheme illustrating an overall configuration of a system, in which the system structure recognition method according to this invention is brought into operation. Four loops (transmission lines) 1, 2, 3, 4 are connected through NCPs and relay processors with each other. The loops 1 and 2 are connected through NCPs 10, 20 and a relay processor 1020; the loops 2 and 3 through NCPs 21, 30 and a relay processor 2130; and the loops 1 and 4 through NCPs 12, 40 and a relay processor 1240 with each other. Two NCPs (e.g. 21 and 30) and a relay processor connected therebetween (e.g. 2130) can be brought together so as to be a relay processing device 2130', as indicated by a broken line. In the loops 1, 2, 3 and 4 are connected NCPs 10-15, 20-23, 30-32 and 40-42, respectively, each of which forms a node on the loop to which it belongs. To the NCPs 11, 13, 14, 15, 22, 23, 31, 32, 41 and 42 are connected processors 110, 130, 140, 150, 220, 230, 310, 320, 410 and 420, respectively. To the NCPs 10 and 20, 21 and 30, and 12 and 40 are connected relay processors 1020, 2130 and 1240, respectively, each of which is common to the two loops with which it is connected. All the NCPs 10-15, 20-23, 30-32 and 40-41 are identical and thus the NCPs 10, 20, 21, 30, 12 and 40 need not have any special function, which is different from that of the other NCPs. Further, in this embodiment, it is supposed that the processor 130 is a system tester, which should recognize the multiloop system structure. However, it can be arbitrarily determined in what location of which loop the system tester is disposed. To the system tester is connected a CRT display device 1300 for displaying the system structure which has been recognized. Instead, a printer outputting the recognized system structure can be used. FIG. 2 shows an example of messages to be transmitted. FC indicates a content code, i.e. a function code, which corresponds to the content or the function of the message. SA indicates the address of the NCP, which has written out and transmitted the message (source address) and CC a serial number, which is necessary for distinguishing it from the others, when the same message should be again transmitted. Further, "Data" represents information to be transmitted or treated. FCS shows data for detecting errors. F is a flag indicating the beginning and the ending of a message and each of them is e.g. a binary number of 8 bits 11111111. Each of the NCPs judges whether the same function code as that stored in its register is contained in each of the messages flowing through the loop, to which it belongs, or not, and takes-in the messages necessary for it, which are sent to its processor.

The function code, which the processor connected to each of the NCPs requires, is previously registered in each of the NCPs, as follows. Each of the processors sends the function codes of messages, which are necessary for itself, to the Data portion indicated in FIG. 2, and registered data, whose function code indicates a function code registration (FC.sub.r) is set in the FC portion in FIG. 2, to the NCP connected to it, at the starting moment at the node, i.e. at the place of connection, that is, when the processor is connected at first or again after an interruption for some reason (e.g. change of the loop structure or trouble). In the case where the function code portion of the registered data is an FC.sub.r indicating a function code registration, the NCP, which has received the registered data from the processor, stores the content of the Data portion, i.e. the function code necessary for a device treating the connection, in its register, and at the same time sends it along the loop in the direction indicated by arrows after having rearranged the message in the format indicated in FIG. 2. Furthermore, when a message, which an NCP has transmitted as a transmitter, returns thereto after having made a circulation through the loop to which it belongs, the NCP removes the message, supposing that the function of the loop is normal and that the source address SA is unique. If the message doesn't return in a determined period of time, the NCP repeats the transmission a predetermined number of times, until the message returns.

Further, the relay processor 1020 sends data where the function code indicating a function code registration (FC.sub.r) is set in the Data portion and the FC portion, to the NCPs 10 and 20; the relay processor 2130 sends them to the NCPs 21 and 30; and the relay processor 1240 sends them to the NCPs 12 and 40 at the starting moment at their places of connection. The following treatment at each of the NCPs is identical to that described above. By the treatment described above the function code, which is required by the processor connected with each of the NCPs 11, 13-15, 21-23, 31-32, and 41-42, is registered therein and the function code of the message to be transmitted between different loops is registered in the NCPs 10, 20, 21, 30, 12, and 40. The explanation of the function code registration method and the data transmission/reception method for a multiloop system in detail will be omitted, because an example of them is described in detail in the above mentioned U.S. Pat. No. 4,366,479, entitled "Control Information Communication Method and System through a Common Signal Transmission Line", or Japanese Patent Application "Transmission Control Method", un-examined publication No. Shoo 57-166756.

Hereinbelow the system structure recognition method for the multiloop transmission system described above will be explained, referring to FIGS. 3-7.

The processor or system tester 130 indicated in FIG. 1 registers the function code FC.sub.l indicating the loop train for recognizing the system structure, i.e. information indicating in what loop and in what order what sort of address processor is connected, in the register of the NCP 13 at its starting moment or when it is necessary. In addition, the relay processors 1020, 2130 and 1240 register not only the function code (FC.sub.r) indicating the function code registration in the NCP connected with each of them but also the function code (FC.sub.l) indicating the loop train.

The processor 130 sends data to the NCP 13 connected with it, in which data a function code (FC.sub.l) indicating the loop train is set in the FC portion in FIG. 2, in order to recognize the system structure, and the Data portion is empty. The NCP 13, which has received the loop train data for the recognition from the processor 130, shapes the message in the format indicated in FIG. 2, after having added its own address of the NCP (cf. the beginning of FIG. 3b) to the Data portion (indicated in FIG. 2), and sends the data to the loop 1, after having set its own address of the NCP in the SA portion indicated in FIG. 2 for showing that the NCP itself is the source of the transmission in the loop 1. Then, the NCP 12 (N.sub.1 in FIG. 3a), which has received this message from the loop 1, recognizes from the function code FC.sub.l that it is not a function code FC indicating that is a message to be transmitted but it is a loop train, and sends it to the loop 1, after having added its own address of the NCP to the Data portion of the message. When the received message is a message to be transmitted, which is usually transmitted and received, the message is sent to the succeeding NCP with the Data portion unchanged. At the NCP 12, since the function code (FC.sub.l) of the loop train is registered therein the received message is sent not only to the NCP 11 but also to the relay processor 1240. The NCP 11, which has received this message from the loop, adds its own address of the NCP to its Data portion and sends it to the loop 1, but doesn't send it to the processor 110, because the function code FC.sub.l is not registered therein. The other NCPs perform in a manner similar to that described above in the loop train.

Further, the relay processor 1240, which has received the loop train from the NCP 12, sends the function code FC.sub.l and the Data portion to the NCP 40, after having added a value obtained by multiplying its own address by "-1" (negative value) as a flag for indicating a message relay to its Data portion, only when the number of relay flags added by itself in the Data portion is not greater than 2. The NCP 40, which has received the loop train data from the relay processor 1240, effects the treatment similar to that for the NCP 13. That is, it shapes the message in the format indicated in FIG. 2, after having added the own address of the NCP to its Data portion, and sets its own address in the SA portion indicated in FIG. 2, i.e. it becomes then a source for the transmission in the loop 4 to send the message to the loop 4. The other relay portions perform in a completely identical manner. In addition, each of the NCPs sends the message to the processors or to the relay processors connected to itself, even if the message includes data produced by itself, in the case where the function code FC.sub.l is registered in it.

By the function of each of the NCPs and that of each of the relay processors described above, the loop train produced by the processor 130, which is the system tester, returns finally to the processor 130, following the path indicated by a heavy line in FIG. 3a, where SA, N.sub.1, N.sub.2, N.sub.3, N.sub.4, N.sub.5 and N.sub.6 are the addresses of the NCPs 13, 12, 40, 10, 20, 21 and 30 in FIG. 1. In the source address portion SA of the loop train message, which has returned to the first loop 1 is inscribed the address N.sub.3 of the NCP connected to the relay processor. When this message has circulated through the loop 1 and returned again to the NCP 10, whose address is N.sub.3, the NCP 10 judges that the message has returned thereto and eliminates it. The content of the Data portion of the loop train, which has passed through the path indicated in FIG. 3a, starting from the processor 130, and returning thereto, is the series of addresses indicated in FIG. 6a. Here all the relay flags (negative values), which are added by every relay processor, are represented by CF. If there is another loop tester 130' (not shown in the figure) in the loop 3, which has transmitted a recognition demand message similar to that of the NCP 13, when the message transmitted by the NCP 13 is taken -in by the processor connected with the loop tester 130', it is ignored, owing to the fact that the address at the beginning and that at the end in the data portion disagree with each other. When it is not necessary to count the number of relay flags, a one-bit flag (601'.about.606') representing such relay may be added as shown in FIG. 3b (400').

The treatment performed in the system tester having received the loop train, which has circulated through the multiloop system and returned thereto, will be explained, referring to FIGS. 4a-7. FIGS. 4a-4e show data areas in the system tester. An address series area 400 is an area, in which the Data portion (FIG. 6a) of the received loop train is stored as it is. A loop area 401 is an area, in which the NCP addresses representing the result obtained by analyzing the address series in the Data portion of the loop train are stored and each of the lines corresponds to one loop. A relay pointer area 402 is an area, in which the pointers representing the position of the NCPs connected to the other loops are stored for every loop and the lines in this area correspond to the lines of the loop area 401. A back pointer area 403 and a forward pointer area 404 are work areas for performing address series analysis treatments. Next the address series analysis treatments by means of each of the areas will be explained, referring to FIGS. 5, 6a, 6b and 6c. FIG. 6a shows the content of the address series area 400 to be analyzed. FIGS. 6b and 6c show the content of the loop area 401 and that of the relay pointer area 402, respectively, after the termination of the treatment indicated in FIG. 5. Hereinbelow the treatments will be explained, referring to FIG. 5.

At first it is judged whether the first address of the address series area 400 is in accordance with the last address or not (Step 501). In the case where they are not in accordance with each other, which means that the loop train data is not produced by the NCP itself, "1" is set in the return code (RTN) and the treatment is terminated. In the case where they are in accordance with each other, which means that the loop train is produced by the NCP itself, the treatment proceeds to Step 503, where an initial value is set. Next, by repeating Steps from 504 to 507, SA of the address series to the first N.sub.1 are set in the first line of the loop area 401 (FIG. 6b). After that, in Step 505, a relay flag CF 601 (FIG. 6a) is detected and the treatment proceeds to the judgment in Step 512. K1 is set in E.sub.1 (1) of the relay pointer area (Step 513), owing to the fact that SA and N.sub.1 in the first line of the loop area are not in accordance with each other in Step 512. Here K1 indicates the number of the line succeeding N.sub.1 stored in the first line of the loop area (FIG. 6b). Further, in Step 514, the pointer i indicating the line of the loop area is changed from 1 to 2 and "1" is set in the back pointer area BP.sub.2. In addition, a subtraction operation needed when the process returns from a loop area Lij written out later to the present loop (at the beginning of Step 515), is prepared. After that, by repeating Steps from 504 to 507 an address series N.sub.2 . . . N.sub.2 (between CF 601 and CF 602 in FIG. 6a) is set in the second line (FIG. 6b) of the loop area 401 (FIG. 6b). Then, in Step 505, CF 602 is detected and the process proceeds to the judgment in Step 512. Since the first and the last address of the second line of the loop area are in accordance with each other in Step 512, the process proceeds to Step 515. In Step 515, owing to the fact that the loop of the second line of the loop area is closed, the line pointer i of the loop area is returned from 2 to 1 and K1 is set in the pointer j indicating the row of the loop area. In addition the value of the forward pointer FP.sub.1 is increased by 1 to 2 and the formation of a new loop area Lij is memorized. Next, by repeating Steps 504 to 507 the addresses up to N.sub.3 before CF 603 of the address area are set in the first line of the loop area. Then, after the judgments in Steps 505 and 512, K2, which is the number of the row succeeding N.sub.3 stored in the first line of the loop area, is set in E.sub.1 (2) in Step 513. Further, in Step 514, the line pointer i of the loop area is changed from 1 to 3 and 2 is set in the back pointer area BP.sub.3. Next, by repeating again Steps 504-507, an address series N.sub.4 -N.sub.5 is set in the third line of the loop area. Further, after the judgments in Steps 505 and 512, K3, which is the number of the row succeeding N.sub.5 stored in the third line of the loop area, is set in E.sub.3 (1) in Step 513. Then, after the change treatment in Step 514, by repeating Steps 504-507, the addresses N.sub.6 -N.sub.6 of the NCPs of the loop 3 is set in the fourth line of the loop area. Then, after the judgments in Steps 505 and 512, 3 and K3 are set in the line pointer i and the row pointer j of the loop area, respectively. Further, by repeating Steps 504-507, the addresses N.sub.4 . . . N.sub.4 of the NCPs of the loop 2 is set in the third line of the loop area. Next, after the judgements in Steps 505 and 512, 1 and K2 are set in the line pointer i and the row pointer j of the loop area in Step 515. Further, by repeating Steps 504-507, the addresses SA . . . SA of the NCPs of the loop 1 are set in the first line of the loop area. Then, in Step 504, since the address series area is empty, after the judgements in Steps 508 and 509 "0" is set in the return code RTN in Step 510 and the analysis treatment is terminated. Whether any of the loops registered in the area Lij has a common NCP address series is checked so as to recognize it as the same loop as the other.

After the address series analysis treatment described above has terminated, by using the content of the loop area and that of the relay pointer area indicated in FIGS. 6b and 6c, respectively, the relation of the connections between different loops is recognized according to the flow indicated in FIG. 7 and outputted to a display device 1300. Hereinbelow the treatment indicated in FIG. 7 will be explained. At first, it is judged by using the RTN whether the address series area analysis is successfully terminated (Step 700). Only when RTN=0, the loop of the first line of the loop area is displayed (Step 701) and the initialization is effected. Then, after the judgment in Step 703, it is recognized and displayed in Step 704 that the loop of the second line of the loop area is connected with an NCP of the (K1-1)-th row in the loop of the first line of the loop area. Further, after having passed through Steps 705 and 703, it is recognized and displayed in Step 704 that the loop of the third line of the loop area is connected with an NCP of the (K2-1)-th row in the loop of the first line of the loop area. Next, after having repeated twice the treatments in Steps 703, 706 and 707, it is recognized and displayed in Step 704 that the loop of the fourth line in the loop area is connected with an NCP of the (K3-1)-th row of the loop of the third line in the loop area. Then, after having repeated the treatments in Steps 703-707, it is recognized by the judgment in Step 707 that the loop area is empty and the treatment is terminated.

According to the method described above, by analyzing the Data portion of the loop train, which has circulated through the system, it is possible to recognize the multiloop system structure. In addition, although the system structure is recognized in the processor 30 belonging to the loop 1 in this embodiment, according to this invention, the system structure can be recognized by an arbitrary processor belonging to an arbitrary loop and further not by only one processor but by a plurality of processors.

This method is useful not only in the case where a plurality of loops are connected with each of the loops of this embodiment and further a plurality of loops are connected with each of the first plurality of loops but also in the case where the system has no multiloop structure, but it has a single loop structure.

Furthermore, although each of the loops is onefold in this embodiment, even when each of the loops is twofold, having two transmission directions different from each other, where a detour structure is possible, the structure can be recognized, as indicated in FIG. 8, at first by recognizing the relation of the connection of each of the loops and also between them according to this invention and then by applying the system structure recognition method for a loop transmission line, which this applicant has previously applied (Japanese Patent Application No. Shoo 59-125139), to each of the loops.

In FIG. 8, two twofold loops 80 and 90, each of which consists of an inner and an outer loop, are connected with each other through a relay processor 87. The message on the inner loops 82, 92 and that on the outer loops 81, 91 advance in the directions indicated by arrows. For example, when either one of the inner and the outer loops 91 and 92 connected with NCPs 97 and 96, respectively, is broken, messages can reach all the NCPs on the twofold loops 80 and 90 except for the NCPs 96 and 97, by flowing through two detours 89.fwdarw.93.fwdarw.94.fwdarw.88 and 88.fwdarw.100.fwdarw.99.fwdarw.89, as indicated by broken lines 102 and 103. Consequently it can be known that also in a twofold loop transmission system it is possible for an arbitrary processor to demand the system structure recognition and for the relay processor to add a flag representing a passage therethrough to the data portion of the message by attaching an address to each of the NCPs.