Low-Cost, High-Accuracy Digitizer Signal Acquisition Apparatus and Method

FIG. 1 is a simplified drawing of the grid of wires employed in a digitizer when employing the prior art approach of strobing the wires with a signal to induce a voltage in a coil in the cursor.

FIG. 2 is an enlarged drawing of a portion of the coil of FIG. 1 showing the manner in which the current is induced into the coil.

FIG. 3 is a block diagram of some of the components of a digitizer operating in the manner depicted in FIGS. 1 and 2.

FIG. 4 is a drawing in the manner of FIG. 1 wherein the signal induced into the wires of the grid are read sequentially.

FIG. 5 is a drawing in the manner of FIG. 2 showing how the driven coil induces a signal into the wires of the grid.

FIG. 6 is a drawing in the manner of FIG. 3 showing the components employed when operating a digitizer in the manner of FIGS. 4 and 5.

FIGS. 7a-7e show the development of a signal in a wire as an energized coil is moved across the wire from one side to the other.

FIG. 8 shows the characteristic relationship of AC wire voltage versus wire position relative to an energized coil wherein the voltage changes phase and passes through zero at the midline of the coil.

FIG. 9 shows a prior art apparatus for developing the digital signal value employed to determine coil position.

FIG. 10 is a simplified block diagram of apparatus according to the present invention.

FIGS. 11a and 11b are drawings of the wave forms developed in the apparatus of FIG. 10.

FIG. 12 is a representation of a single voltage wave showing the way the present invention integrates the entire wave to produce an equivalent value of high accuracy.

FIG. 13 is a block diagram of apparatus according to a tested embodiment of the present invention.

According to the present invention as depicted in FIG. 10, the output 49 containing the full-wave demodulated signal of FIG. 9 is biased at 51 so as to always be a negative voltage and is input to a summing junction 58 which is the input to an integrator 60 which, due to its circuit configuration, has a negative gain. The output of the integrator 60 is connected as the input to a threshold detector 62. The output of the threshold detector 62, in turn, is connected to the input of a one- shot multi-vibrator 64. The output of the one-shot multi-vibrator 64 is connected as an input to a digital counter 66 whose output is the digitized integrated value of the signal on line 46. The output from the one-shot multi-vibrator 64 is also connected to an input of the summing junction 58. The operation of the foregoing components can be understood best with reference to FIG. 11. The summing junction 58, integrator 60, threshold detector 62, and one-shot multi-vibrator 64 act as a voltage-to-frequency converter, generally indicated as 68, which drives the counter 66. Since the voltage is converted to frequency, the count value within the counter 66 for each sample period is a digital value directly related to the voltage which produced it. Moreover, it is a function of the area under the signal 52 as depicted in FIG. 12, i.e., the integral of the signal for that period. As those skilled in the art will recognize, this allows data rate/resolution tradeoff that was desired as an object of the present invention as well as the utilization of the signal for the greatest possible fraction of the time for which it is available. If the sampling (integration) time is increased for each wire 12, 14, the data rate will go down; however, the quantization of the values produced will increase allowing greater resolution because the integration goes on for a longer period of time and, therefore, more precisely represents the area under the signal 52. Correspondingly, if the sample time at each wire 12, 14, is reduced, the data rate will increase with a corresponding reduction in the integration time and, therefore, the resolution.

FIG. 11a represents the output of the integrator 60 as a function of time while FIG. 11b represents the output of the one-shot multi-vibrator 64. The voltage rate of the integrator 60 is proportional to the input voltage applied thereto. The greater the voltage, the steeper the slope. When the voltage from the integrator 60 reaches the value of the threshold detector, the one-shot multi-vibrator 64 produces a single square wave pulse. As will be recalled, the output of the one-shot multi-vibrator 64 is summed with the input (i.e., the voltage) on line 49 which has been driving the integrator 60 in a positive direction. This negative feedback drives the output of the integrator 60 in a negative direction until the termination of the single square wave pulse from the one-shot multi-vibrator 64, at which time the voltage on line 49 once again causes the integrator 60 to integrate in a positive direction at a rate determined by the voltage value. The result is a series of square wave pulses as shown in FIG. 11b at a frequency proportional to the voltage on line 49 by virtue of the integration loop's necessity for an average voltage of zero at the integrator input. Thus, as will be readily recognized by those skilled in the art, a less negative voltage on line 49 will produce a lower slope on the signal out of integrator 60 producing outputs from the one-shot multi-vibrator 64 at greater intervals and, therefore, a lesser frequency to produce a lower count within the counter 66. Correspondingly, a greater voltage produces a steeper slope which, in turn, produces the square wave pulses at a higher frequency resulting in a higher count in the counter 66. The HC4538 monostable multivibrator used in this embodiment has a Schmitt trigger input making it rise time insensitive. The threshold detector and the monostable multivibrator reside in the same IC in the preferred embodiment.

The way the foregoing method and apparatus has been implemented in a commercial embodiment of the assignee of the present invention is shown in simplified form in FIG. 13. The counter 66 is contained within a micro-controller 70 which performs various functions within the associated digitizer including the calculations of the cursor position. The micro-controller 70 contains logic 72 which controls the micro-controller 70 to perform its necessary functions. As depicted in FIG. 13, the demodulated, biased grid wire voltage on line 49 is input to the voltage-to-frequency converter 68 previously described with respect to FIG. 10. The entire apparatus is driven by a 10.47 KHz clock frequency appearing as an input at 74. The logic 72 in the microcontroller 70 is capable of enabling the V to F converter 68 for any length of time desired; but, cannot enable the V to F converter 68 for exactly the same length of time for every sample. By sampling the 10.47 KHz clock and changing the state of enable line 76, the logic, in combination with flip-flop 80, causes the V to F converter 68 to be enabled for an exact multiple of the period of the 10.47 KHz clock, with the number of periods being completely controlled by the logic. As a particular wire 12, 14 is to be sampled, the logic 72 sends an enable signal on line 76 to flip-flop 78 which, in turn, enables the voltage-to-frequency converter 68 via line 80. The output from the one-shot multi-vibrator 64 within the voltage-to-frequency converter 68 appearing on line 82 is input to a counter 81 which produces three outputs of 1/2, 1/4, and 1/8 the frequency of line 82. The 1/8 frequency output is applied to the counter 66 contained within the micro-controller 70 as described above. The counter 81 is required in the commercial embodiment only because the microprocessor counter employed cannot count at a rate higher than 460 KHz while the frequency on line 82 can be as high as 2 MHz. The counters 81 and 66 are reset by the logic 72 via line 84. The output of the counter 66 is connected to a bus buffer 86 whose output is the data bus 88 containing the data which are employed in the calculation process by the logic 72. The output of the counter 81 is also available to the data bus 88. Note that the overflow indicator from the counter 66 is fed to the logic 72 such that reduced data rates producing high resolution with corresponding high count values within the counter 66, which can produce an overflow thereof, can be easily and automatically compensated for by the logic 72 without the necessity of providing additional apparatus for the purpose.

The resultant count in the counter will tend toward zero as the analog signal 49 becomes more positive. The count tends toward the maximum value as the analog signal 49 becomes more negative. The count produced by zero input is obtained by selecting any wire 12, turning off the oscillator 26 which drives the cursor coil 20, and acquiring the resulting count for that wire.

Thus, it can be seen from the foregoing description that the present invention has achieved its desired objectives by providing an improved method and apparatus for producing a digital equivalent value to the voltage signal produced in a digitizer which can be made highly quantized at the sacrifice of data rate or of a high data rate at the sacrifice of resolution.

The invention should not be considered as being limited to the specific embodiment described in detail above by way of example. For example, improved voltage to frequency linearity has been achieved by the inventor herein using synchronous voltage to frequency conversion which, instead of using a time reference based on the pulse width of a monostable multivibrator, uses the period of a relatively high frequency (approximately 2 MHz system clock) to establish the pulse width. In this alternate embodiment, the integrator output is connected to a flip-flop D input and the microcontroller ALE output is connected to the flip-flop clock input. In this alternate configuration, the counter input is connected to the output of an OR gate whose inputs are ALE and the Q.sup.* output of the D flip-flop. Voltage to frequency converter IC's are also available as an alternate to the discrete component V to F described hereinbefore. These and other improvements modifications to the present invention which would be readily apparent to those skilled in the art are intended to fall within the scope and spirit of the invention with respect to this enabling disclosure and the claims appended hereto.