Semiconductor Memory Device Having Improved Precharge Scheme

The present invention relates to a semiconductor memory device in which a pair of bit lines are precharged prior to a read or write operation.

As is well known, a semiconductor memory is structured in that a plurality of memory cells are provided in rows and columns, and word lines and bit line pairs are arranged in rows and columns, respectively. Each of the bit line pairs is composed of a pair of bit lines, and each of the pair of bit lines are equally precharged to a predetermined potential prior to a read or write operation. This precharge of bit lines is conducted by providing precharge transistors between bit lines and a voltage source of the predetermined potential and rendering the precharge transistors conductive.

However, accompanied by the increase in memory capacity, the number of bit lines pairs has been remarkably increased, and this increase in memory capacity has also caused the increase in the number of the precharge transistors for precharging bit lines in each bit line pair. The precharge transistors are simultaneously rendered conductive by a precharge control signal commonly applied to gates of the precharge transistors. Therefore, effective capacitance of the gates of the precharge transistors has inevitably become large. In other words, a load capacitance of the precharge control signal has become large. Accordingly, it has been difficult to drive the precharge transistors at a high speed in response to the precharge control signal and therefore, a time period required to complete the precharge has become large, resulting in low speed operation of memories.

It is one object of the present invention to provide a semiconductor memory device operable at a high speed.

It is another object of the present invention to provide a semiconductor memory device provided with a high speed precharging scheme.

The semiconductor memory device according to the present invention comprises a plurality of memory cells provided in rows and columns, word lines and a plurality pairs of bit lines arranged in rows and columns, respectively, a plurality of precharge transistors coupled between the respective bit lines and a precharge potential source and a control circuit for operatively generating a precharge control signal for rendering the precharge transistors conductive, and is featured in that the plurality pairs of bit lines are divided into a plurality bit of line groups, and the precharge control signal is selectively applied only to the precharge transistors belonging to selected one of the bit line groups while the precharge control signal is not applied to the precharge transistors belonging to the remaining non-selected bit line group.

According to the present invention, the precharge control signal is applied to only a part of the whole precharge transistors and therefore, effective capacitance load on the precharge control signal can be remarkably reduced. As a result, the selected group of bit lines can be precharged at a high speed.

FIG. 1 is a schematic block diagram showing a memory device according to the prior art;

FIG. 2 is a schematic block diagram according to a first embodiment of the present invention;

FIG. 3 is a timing diagram showing operations of the memory of FIG. 2;

FIG. 4 is a schematic circuit diagram showing an example of memory cells employed in the memory of FIG. 2;

FIG. 5 is a schematic circuit diagram of a bit line selection circuit;

FIG. 6 is a schematic circuit diagram of group selection circuits in FIG. 2;

FIG. 7 is a schematic circuit diagram of an address transistor detection circuit in FIG. 2; and

FIG. 8 is a block diagram showing a memory device according to a second embodiment of the present invention.

FIG. 1 shows the memory device according to a prior art. A plurality of word lines WL.sub.l to WL.sub.m are arranged in rows while a plurality of pairs of bit lines (D.sub.l, D.sub.l) to (D.sub.n, D.sub.n) are arranged in columns. A plurality of static type memory cells MC are provided in a matrix form of rows and columns in a known way. A row decoder 3 receives row address signals AR and selects one of the word lines in response to a control signal .phi..sub.1. Each pair of bit lines are provided with precharge transistors Q.sub.1, Q.sub.2 and Q.sub.3. Also, the pairs of bit lines are connected to a pair of bus lines DB and DB through transfer gate transistors (Q.sub.51, Q.sub.51 ') to (Q.sub.5n, Q.sub.5n '), respectively, which are controlled by a column decoder 4 receiving column address signals AC and a control signal .phi..sub.2. The bus lines DB and DB are connected to a buffer circuit 5 connected to an input/output terminal I/O.

An address transistor detection circuit 1 receives both the row address signals AR and the column address signals AC and generates a detection signal .phi.A when at least one of the row and column address signals has changed. All the precharge transistors Q.sub.1 to Q.sub.3 for the respective bit lines are controlled by a precharge control signal .phi..sub.p. A timing signal generating circuit 2 generates the precharge control signal .phi..sub.p, and the timing signals .phi..sub.1 and .phi..sub.2 in a predetermined sequence in response to the detection signal .phi..sub.A.

When at least one of the address signals has changed and a new access operation is about to start, the detection signal .phi..sub.A is generated and the precharge signal .phi..sub.P is generated immediately after the generation of .phi..sub.A. Therefore, all the precharge transistors Q.sub.1 to Q.sub.3 are rendered conductive so that all the bit lines are equally precharged to a power voltage V.sub.CC. After disappearance of .phi..sub.P, the signals .phi..sub.1 and .phi..sub.2 are sequentially generated so that the row decoder 3 selects one word line and the column decoder 4 selects one pair of bit lines by conducting one pair of transfer gates e.g. Q.sub.51, Q.sub.51 '. Thus, true and complementary read signals are transmitted to the bus lines DB and DB for reading out.

However, the precharge signal .phi..sub.P is commonly applied to gates of all the precharge transistors Q.sub.1 to Q.sub.3 in the respective columns and therefore load capacitance associated to the signal .phi..sub.P is very large. Accordingly, it is difficult to switch all the precharge transistors at a high speed by the signal .phi..sub.P, resulting in low speed operation. Referring to FIGS. 2 to 7, a memory device according to one embodiment of the present invention is explained below.

FIG. 2 shows a major structure of the memory according to the embodiment.

A plurality pairs of bit lines are divided into a plurality of bit line groups 10-l to 10-n. As being represented by the group 10-l, each of the groups 10-l to 10-n includes a plurality of pairs of bit lines D.sub.l, D.sub.l to D.sub.L, D.sub.L, a plurality sets of precharge (P-channel type) transistors Q.sub.1 to Q.sub.3 provided for the respective bit line pairs, a plurality of word lines WL.sub.l to WL.sub.m extending over all the bit line groups, and a plurality of static type memory cells MC. Each of memory cells MC is composed of P-channel transistors Q.sub.4 and Q.sub.5, N-channel transistors Q.sub.6 to Q.sub.9, as shown in FIG. 4. A row decoder 13 selects one of the word lines in response to now address signals AR when a timing signal .phi..sub.3 is activated.

Bit line selection circuits 16-l to 16-n are provided for the bit line groups 10-l to 10-n respectively. Each of the bit line selection circuits 16-l to 16-n receives first column decoder signals YD (YD.sub.l. . . YD.sub.L) generated by a first column decoder 14-2 receiving a first part AC1 of column address signals in response to .phi..sub.3 and selects one pair of bit lines and outputs data on the selected pair of bit lines to each of outputs GB.sub.l to GB.sub.n. Group selection circuits 17-l to 17-n receive second column decoder signals Y.sub.l to Y.sub.n, respectively and one of them is selected by Y.sub.l to Y.sub.n so that data on the selected outputs GB.sub.l to GB.sub.n is transmitted to a bus line DB connected to an output buffer 15. The bit selection circuit 16-l is composed of a plurality of gate differential amplifiers SA.sub.l to SA.sub.n provided for the pairs of bit lines D.sub.l, D.sub.l to D.sub.n, D.sub.n, each composed of N-channel field effect transistors Q.sub.10, Q.sub.12 and Q.sub.13, a pair of N-channel load transistors Q.sub.16 and Q.sub.17 controlled by .phi..sub.4 and a P-channel reset transistor Q.sub.18 controlled by .phi..sub.1. When the pair of bit lines D.sub.l, D.sub.l are selected, the decoder signal Y.sub.l assumes a high level so that the sense amplifier SA1 is enabled. As a result, data on the selected pair of bit lines D.sub.l and D.sub.l are transmitted to GB.sub.l and GB.sub.l. Each of the group selection circuits 17-l to 17-n is composed of a gated differential amplifier made of N-channel transistors Q.sub.26 to Q.sub.27. A pair of N-channel load transistors Q.sub.24 and Q.sub.25 and a P-channel reset transistor Q.sub.19 are commonly provided for the circuits 17-l to 17-n.

The decoder signal Y.sub.l to Y.sub.n are generated by a second column decoder 14-l receiving a second remaining part AC2 of the column address signals in response to a timing signal .phi..sub.2. An address transistor detection circuit 11 receives all the row address signals AR and the column address signals AC1 and AC2 and generates a detection signal .phi..sub.A when at least one address signal has changed. One example of circuit structure of the detection circuit 11 is shown in FIG. 7. For all the row address signals AR.sub.l. . . AR.sub.m and all the column address signals AC.sub.1. . . , delay circuits 21-l to 21-m and exclusive OR gates 20-l to 20-m are provided. Outputs of the exclusive OR gates 20-l to 20-m are inputted to an OR circuit 23 from which the detection signal .phi..sub.A is generated. For example, the exclusive OR circuit 20-l receives a row address signal AR1 and its delayed signal from the delay circuit 21-l. When the signal AR1 has changed the signal AR1 itself becomes different from its delayed signal, the circuit 20-l generates a pulse which is then outputted as .phi..sub.A via the OR gate 23. A timing signal generating circuit 12 generates a precharge control signal .phi..sub.1, timing signals .phi..sub.2, .phi..sub.3, .phi..sub.4 and .phi..sub.5, as illustrated in FIG. 3. The precharge control .phi..sub.1 is applied to inputs of NOR gates NG.sub.l to NG.sub.n which receive inverted column decoder signals Y.sub.l to Y.sub.n, respectively. The signal .phi..sub.1 and Y.sub.l to Y.sub.n are low active signals. Namely, when they assume low levels when they are energized or selected. The outputs of the NOR gates NG.sub.l to NG.sub.n are inputted to inverters IV.sub.l to IV.sub.n, respectively, and outputs .phi..sub.Pl to .phi..sub.Pn of the inverters IV.sub.l to IV.sub.n are supplied to the precharge transistors Q.sub.1 to Q.sub.3 of the bit line groups 10-l to 10-n, respectively. Therefore, when the bit line group 10-l is about to be selected for reading therefrom or writing thereto in response to a high level of Y.sub.l (a low level of Y.sub.l), the circuit 11 generates .phi..sub.A and thereafter the circuit 12 generates a low level of .phi..sub.1. Since among the inverted decoder signal Y.sub.l to Y.sub.n, only Y.sub.l is rendered low in level with others high in level, so that only the NOR gate NG.sub.l generates a high level output and the inverter IV.sub.l generates a low level of .phi..sub.Pl. As a result, the precharge transistors Q.sub.1 to Q.sub.3 for the respective bit line pairs only in the bit line group 10-l are rendered conductive and the bit lines in the group 10-l are precharged to V.sub.CC. While other inverted decoder signals Y.sub.2 to Y.sub.n are high in level and the signals .phi..sub.P2 to .phi..sub.Pn are high. Therefore, the precharge transistors (Q.sub.1 to Q.sub.3) of the non-selected bit line groups 10-2 to 10-n are non-conductive and precharge is not achieved in the non-selected bit line groups 10-2 to 10-n. Referring to FIG. 3, a typical read operation is explained.

At a time point t.sub.1, at least one of the row and column address signals AR, AC1 and AC2 has changed. This means that new access cycle is about to commence. In response to this change in address signals, the detection signal .phi..sub.A is generated and thereafter the signals .phi..sub.1, .phi..sub.2 to .phi..sub.5 are generated as illustrated. Namely, .phi..sub.1 is first rendered low and .phi..sub.2 is changed to a high level. Therefore, the decoder signal Y.sub.l to Y.sub.n and their inverted signals Y.sub.l to Y.sub.n are developed. In response to this, the states of the signals .phi..sub.Pl to .phi..sub.Pn are also developed. Accordingly, the precharge transistors Q.sub.1 to Q.sub.3 in the selected bit line group are rendered conductive so that the bit lines in the selected bit line group are precharged to V.sub.CC, as representatively illustrated by waveforms of Dl and Dl. Then, in response to .phi..sub.3, the row decoder 13 selects one of the word lines WL.sub.l to WL.sub.m and the first column decoder 14-2 selects one of the bit line pair in the respective bit line groups. Therefore, the pair of bit lines Dl, Dl are changed in level according to stored data of a selected memory cell and a potential change is amplified if selected. Through the selected one of the selection circutis 17-l to 17-n, the data from the selected bit line group are outputted to I/O.

According to the present invention, precharge of the bit lines is performed only in the selected bit line group, and the precharge control signal .phi..sub.1 is applied only to the precharge transistors in the selected bit line group, and therefore, an effective capacitance loaded on the precharge control signal .phi..sub.1 is made small to enable a high speed precharge operation. Furthermore, a power consumption caused by the precharge is remarkably reduced.

FIG. 8 shows another embodiment of the invention.

This embodiment is featured in that the bit line groups 10-l to 10-n include separate word lines (WL.sub.l-l to WL.sub.l-m) to (WL.sub.n-l to WL.sub.n-m), respectively. The word decoder signals W.sub.l to W.sub.m are applied to the word lines of the bit line groups 10-l to 10-n through a plurality sets of AND gates (AG.sub.ll --AG.sub.lm) to (AG.sub.nl --AG.sub.nm), as illustrated. In other words, the word lines in the selected bit line group are subjected to a word line selection. For example, when the bit line group 10-l is to be selected, the AND gates AG.sub.ll to AG.sub.lm are conditioned by a high level of Y.sub.l so that one of the word lines WL.sub.l-l to WL.sub.l-m is selected by the decoder signals W.sub.l to W.sub.m.

According to this embodiment, each of the word lines is made far shorter than the case of FIG. 2, the effective capacitance associated to the respective word lines is remarkably reduced. Thus, a high speed operation can be further enhanced.

The present invention has been explained by way of examples of static type memory device. However, the present invention is also applicable to any type memories in which bit lines are precharged.