Safety Gate Limit Switch Using Hall Effect Transducer

The invention relates to safety gate limit switches used as safety devices for moving machinery, and more particularly to the use of magnets and Hall effect transducers in safety gate limit switches.

In the control of machine tools, it is important for operator safety to activate the machine tool only when a safety gate is in place to protect the operator from physical harm. The operator may be injured by the machine tool moving and inadvertently striking the operator. A limit switch is often used to prevent the machine tool from moving before the safety gate is in place. A number of limit switches have been devised in the past for the control of a machine tool. Many attempts in the past have been made to adapt a mechanically operated toggle switch to sense the presence of a closed safety gate. A disadvantage of a mechanically operated toggle switch is that is can be defeated by operator action. For example, a toggle switch may be taped closed, or may be wired closed. The machine tool can then be operated with the safety gate in an unsafe position.

A problem addressed by the present invention is to make a safety gate limit switch which is difficult to defeat by action of the operator. Akehurst, U.S. Pat. No. 4,349,814, issued on Sept. 14, 1982, shows the use of Hall effect magnetic field sensors to make a safety gate limit switch. Akehurst uses Hall effect transducers arranged to require magnetic poles of opposite polarity to activate his limit switch. A disadvantage with this arrangement is that a short bar magnet having a north pole and a south pole at opposite ends could be placed in proximity to the magnetic field detector and thereby expose the two Hall effect transducers to the proper magnetic fields for activating the switch. A further problem addressed by the present invention is to provide a magnetic field sensing arrangement which provides greater safety against being overridden by any simple action of the operator, and also to provide a detector system and logic circuit for the invention.

The invention solves the problem of making a proximity switch which is difficult for an operator to defeat by using at least two magnets and three Hall effect magnetic field sensing transducers. The invention is a proximity switch comprising at least three magnetic field sensitive transducers mounted in a transducer housing and having a first conductive state in the presence of a magnetic field of predetermined magnitude and predetermined direction and a second conductive state in the absence of a magnetic field having the predetermined magnitude and direction. At least two magnets are mounted in a magnet housing and each is capable of putting the transducers into the first conductive state when placed near the transducers, and are positioned in the magnet housing so that when the magnet housing is located at a predetermined position relative to the transducer housing at least two of the transducers are in a magnetic field capable of putting the transducers into the first conductive state and at least one of the transducers is in a magnetic field not capable of putting the transducers into the first conductive state. A logic circuit responds to the conductive states of the at least three transducers and is capable of generating an output signal having a first value when the at least two of the transducers are in the first conductive state and at least one of the transducers in the second conductive state and has a second value when the transducers have any other combination of conductive states, and an electronic switch responds to the output signal of the logic circuit and is capable of closing when the output signal has the first value and is capable of opening when the output signal has the second value so that the electronic switch is closed when the magnet housing is in the first predetermined position relative to the transducer housing, and is open for other relative positions of the magnet housing and the transducer housing.

Other and further aspects of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings.

Referring now to the drawings, in which like numerals represent like parts in the several views:

FIG. 1 is a perspective view of a safety gate limit switch.

FIG. 2 is a perspective view of an electronic circuit board.

FIG. 3 is a bottom perspective view of a magnet housing.

FIG. 4 is a top view showing magnets and magnetic field lines.

FIG. 5 shows prior art.

FIG. 6 is a schematic diagram of a detector and logic circuit.

FIG. 7 is a schematic diagram of a power supply and additional logic circuit for use with a plurality of safety gate limit switches.

FIG. 8 is a schematic diagram of a logic circuit.

FIG. 1 shows a safety gate limit switch having a magnet housing 100 and a transducer housing 102. Magnets 104 and 106 are contained within magnet housing 100. Hall effect magnetic field detectors 110, 112 and 114 are located within transducer housing 102. Magnet housing 100 is named the "key". The transducer housing 102 containing the Hall effect magnetic field sensors is named the "switch".

Hall effect magnetic field sensors 110, 112, 114 are capable of producing an electric logic signal indicative of the presence of a magnetic field above a threshold value. For example, it has been found satisfactory in the present invention to use Sprague Electric Company, Semiconductor Division, located at Pembrook Road, Concord, New Hampshire, product model No. UGN-3040U Solid State Hall Effect Digital Switches for magnetic field detectors 110, 112, 114. For example, the Sprague product model No. UGN-3040U has a logical "1" output in a magnetic field less than about 200 gauss, and has a logical "0" output for a magnetic field exceeding about 200 gauss, so long as the magnetic field is directed toward a predetermined side of the product.

FIG. 2 is a perspective view of an electronic circuit board 116 showing magnetic field detectors 110, 112, 114 mounted thereupon. Also, mounted upon electronic circuit board 116 are integrated circuits, resistors, capacitors, transistors, and indicating lights. Light emitting diodes (LED's) may be used for indicating lights.

FIG. 3 is a perspective drawing showing magnetic housing 100 turned so that the magnets mounted therein are visible. FIG. 4 is a top view showing magnets 104 and 106 mounted in magnet housing 100, and magnetic field detectors 110, 112, 114 mounted in transducer housing 102. Both magnets 104 and 106 are shown with their south pole oriented toward their respective magnetic field detectors 110, 114. Magnetic field lines are drawn leaving magnets 104, 106 from the north pole and circling around lines of constant field strength to the south pole. Thus, the magnetic field penetrates magnetic field detectors 110 and 114 from sides 110A and 114A respectively. In contrast, weaker magnetic fields penetrate magnetic field detector 112 from side 112B. The magnetic field detectors are capable of responding to the direction of a magnetic field applied to them. Magnetic field detectors 110, 112, 114 are oriented similarly in transducer housing 102 so that they produce an output logic signal indicating the presence of a magnetic field when the magnetic field both penetrates the detectors from side 110A, 114A as it does in FIG. 4 for detectors 110 and 114 and has a magnitude exceeding a threshold value, for example, exceeding 100 gauss. The detectors produce a logic signal indicating the absence of an appropriate magnetic field when the field penetrates a detector such as is shown in FIG. 4 for detector 112 by entering the detector through side 112B.

A logic circuit which measures the output of magnetic field detectors 110, 112, 114 detects the output of the magnetic field detectors and produces a final output logic signal which has a first value if the magnets in the magnet housing have their south poles adjacent to detectors 110 and 114. The logic circuit produces an output indicative of the absence of appropriate magnetic fields if no magnetic field penetrates detectors 110 and 114 from sides 110A, 114A as shown in FIG. 4, or if a magnetic field penetrates magnetic field detector 112 from side 112A. Thus, the magnet housing 100 must be properly positioned with respect to transducer housing 102 in order for the logic signal to produce the output indicating the presence of appropriate magnetic fields at the locations of magnetic field detectors 110, 112, and 114.

The apparatus of the invention is used as a safety gate limit switch by having magnet housing 100 mounted on, for example, a safety gate surrounding moving parts of a machine tool. Transducer housing 102 may be mounted, for example, on a stationary part of the machine tool. When the safety gate is closed, for example, thereby preventing an operator from having his hands in a position where the machine tool could harm his hands, the south poles of the magnets will be aligned as shown in FIG. 4 with magnetic field detectors 110, 112, 114. The output of the logic circuit will then indicate that the safety gate is closed, and enable operation of the machine tool.

An arrangement of magnets and magnetic field detectors shown by Akehurst, U.S. Pat. No. 4,349,814 issued Sept. 14, 1982, is shown in FIG. 5.

FIG. 6 shows a schematic diagram of the detector logic circuit. Magnetic field detectors 110, 112, and 114 are shown connected to logic circuits. Logic circuits are designated by the reference numerals L1, L2, L2B, L3, L4, L5, L6, L7, L8, L9, and L10. Transistors are designated by the reference numerals Q1, Q2, Q3, Q4, Q5, and Q6.

The output voltage of the logic circuit is indicated by the reference numeral V.sub.0. Magnetic field detector 110 is represented by integrated circuit IC1, magnetic field detector 112 is represented by IC2, and magnetic field detector 114 is represented by IC3. When magnetic south poles are adjacent to magnetic field detectors 110 and 114, and no magnetic field is applied to magnetic field detector 112, then IC1 output has a logical level 0, IC2 oputput has a logical level 1, and IC3 output has a logical level 0. Logic circuit L1 thus has two inputs of logic level 1, and therefore generates an output of logic level 0 which is applied to logic circuit L2B. IC1 output has a logical level 0 resulting from the presence of a south magnetic pole, and this output is applied to logic circuits L2, L3, and L4. IC3 output has a logical level 0 as a result of the presence of a south magnetic pole, and this output is fed to logic circuits L2, L3, and L4. L2 then has an output 0, L3 has an output 0, and L4 has an output 1. Logic circuit L2B has an output 1. The output of logic circuit L2B goes through a diode to capacitor C4 and resistor R9. The time constant of capacitor C4 and resistor R9 is approximately 1.8 seconds. When the logic level output from logic circuit L2B changes, it takes approximately 1.8 seconds for the input at pin 1 of logic circuit L8 to correspondingly change as a result of the time constant of capacitor C4 and resistor R9. The 1.8 seconds time constant permits the magnet housing to slide across the transducer housing without triggering a fault condition if the housing slides quickly relative to 1.8 seconds. Logic circuit L7 has an output 1, and logic circuit L8 has an output 0. Thus, a logic signal 1 is applied to Q3 turning it on and turning on transistor Q5. Fault indicator lamp DS2 is turned off. Logic circuit L9 has a logical 1 input from logic circuit L4 and a logical 0 input from its grounded input. Logic circuit L9 therefore has a logical 1 output which turns transistor Q4 on, which in turn turns transistor Q6 on. Transistors Q5 and Q6 are therefore both on, and an electric current flows from the power supply VSS to ground through transistors Q5 and Q6 and through current regulator VR2. Thus, voltage V.sub.0 has a logic 1 value. The logic 1 value of voltage V.sub.0 activates a control unit (shown in FIG. 7) in order to activate a machine as a result of south magnetic poles being presented simultaneously to magnetic field detector integrated circuits IC1 and IC3 in the absence of a south magnetic pole being applied to integrated circuit IC2. Also, when voltage V.sub.0 has a logic 1 value, the load indicator LED DS3 is illuminated. Zener diode CR5 clamps the corresponding input to L10 to 7.5 volts when V.sub.0 is at logic value 1. Voltage V.sub.0 goes to nearly the power supply voltage VSS, which may be between 10 to 30 volts, when at logic value 1. Transorb RV2 attenuates transients on the output voltage V.sub.0.

Logic circuits L7 and L8 establish proper levels at the time that power is applied to the circuit. After power is applied to the circuit, the state of the NAND flip-flop comprising L7 and L8 is such that the output of L7 is a logic 1 and the output of L8 is a logic 0. This is effected by the time constant R5 C2 being 10 times the value of the time constant of R8 C4.

The flip-flop comprising L7 and L8 changes states if the output of L2B should change to and remain at a logic 0 for approximately 1.8 seconds. This will occur if the magnetic field detectors 110, 112 and 114 sense for approximately 1.8 sconds a magnetic field pattern other than that produced by the correct key, (as shown in FIG. 4) or if the output Vo of the device is shorted to ground for about 1.8 seconds when the device is in the "on" state.

Both L5 and L6 form an oscillator that activates the flashing fault LED DS2 by way of transistor Q2. The oscillator L5 and L6 is activated in response to the output of L7 having a logic value 0.

The logic level Vo at the output is monitored by logic circuit L10. If Q6 were to fail by short circuiting when the safety gate limit switch is in the off state (that is Vo has logic level 0), then this condition will be detected by L10 and Q5 will be turned off in response to logic circuit L2B after about 1.8 seconds.

Thermistor R19 increases in resistance in response to an overload current or in response to high temperature. Thermistor R19 is in thermal contact with transistor Q6. If transistor Q6 should overheat, then thermistor R19 will limit the load current thereby protecting Q5 and Q6.

In the event that south magnetic poles are applied to integrated circuit IC2 as well as integrated circuits IC1 and IC3, then integrated circuit IC2 has a logic 0 output. This output is fed to logic circuit L1 which then has an output of logic 1. This logic 1 output is connected to logic circuit L2B, thereby producing an output logical 0 from L2B. The logical 0 output from L2B causes a logical 1 output from logic circuit L8 and a logical 0 output from logic circuit L7. The logical 0 output from logic circuit L7 turns off transistor Q3 which in turn turns off transistor Q5. Also, logic circuit L4 has a logical 0 output which causes logic circuit L9 to have a logical 0 output. The output of logic circuit L9 turns off transistor Q4 which in turn turns off transistor Q6. With transistors Q5 and Q6 turned off, no current flow occurs from the power supply VSS through current regulator VR2, thereby driving output voltage V.sub.0 to ground, which is a logic value of 0. The logical 0 value for output voltage V.sub.0 then deactivates a control unit (shown in FIG. 7) for the machine controlled by the invention. Other combinations of south magnetic poles or no presentation of south magnetic poles to integrated circuits IC1, IC2, and IC3 are shown in Table 1. In all cases, the output voltage V.sub.0 has a value of logic 0.

In Table 1 the columns M1, M2, M3 refer to the placement of a magnetic pole adjacent to IC1, IC2, IC3, respectively. The column L1-L10 give the logical output of the respective logic circuits with the arrangement of magnetic poles shown in columns M1, M2 and M3. The column "FAULT LED" shows whether LED diode DS2 is on or off. The columns Q5, Q6 show whether transistor Q5 and Q6 are turned on or off. The column V.sub.0 shows the logical level of the output voltage V.sub.0. Under columns L5 and L6 the word "OSC" means that L5 and L6 are oscillating.

FIG. 7 shows a power supply for a plurality of safety gate limit switches and a final logic circuit L11. Output voltage V.sub.0 from a single safety gate limit switch is attached to any of contacts C1, C2 or C3. Logic circuit L11 can be adjusted to produce an output if any of the selected inputs has a logic value 1. Alternatively, logic circuit L11 can have safety gate limit switches connected to each of its inputs or to a lesser number of its inputs. Logic circuit L11 can be adjusted to produce an output signal only if all of its inputs connected to safety gate limit switches have their respective input voltages V.sub.0 set to logic value 1. Logic circuit L11 output turns transistor Q7 on, and transistor Q7 in turn turns transistor Q8 on. Current flow through transistor Q8 energizes relay R1, thereby causing armature A to move from position closing terminal T1 to the position closing terminal T2. Thus, when relay R1 is energized a complete circuit is produced between armature A and terminal T2. When relay R1 is not energized an electric circuit exists between armature A and terminal T1. Relay R1 can be used to control a machine, for example a machine tool. A circuit exists from armature A to terminal T2 only when the safety gate protecting the machine is in a protective position.

The circuit as set forth in FIG. 6 has two substantially independent interconnected logic paths. The first logic path actuates transistor Q6 in response to logical states of the Hall effect transducers 110, 112 and 114. The first logical path uses logical circuits L3, L4 and L9, and these logical circuits drive transistors Q5 and Q6.

The second logical path provides self-checking of fault conditions and turns transistor Q5 off if a fault condition is indicated. The second logical path uses logical circuits L1, L2, L2B, L7 and L8, and these logical circuits drive transistors Q3 and Q5. Also, they drive the oscillator made up of logical circuits L5 and L6 to provide a flashing signal to fault diode LED DS2. Logical circuits L7 and L8 are a flip-flop which has two functions, the first as noted above is to establish proper logical levels at the time that power is applied to the circuit. The second purpose of flip-flop L7 and L8 is to lock transistors Q5 in an "off" state in the event that a fault condition is sensed by the second logical path. The fault conditions that the second logical path responds to include failure of any of the Hall effect transducers to operate in response to the key, an attempt by a person to over-ride the transducers by application of inappropriate magnetic fields, a stray magnetic field operating on all tansducers with the same polarity, a short of V0 to ground when the first logical circuit requires V0 to be at logical level 1, and the converse where output voltage V0 is in logical state 1 when the output of the first logical circuit requires that Q6 be turned "off".

FIG. 8 shows the logical connection within logical circuit L11. Inputs 120, 122 and 124 (shown in FIG. 7) connect to inputs 120A, 122A, 124A. Output 130 drives transistor 7. Logical unit 132 is not used.

It is to be understood that the above-described embodiments are simply illustrative of the principles of the invention. Various other modifications and changes may be made by those skilled in the art which will embody the principles of the invention and fall within the spirit and scope thereof.