Hierarchical Data Transmission System

(1) Field of the invention

The present invention relates to a hierarchical data transmission system in which a plurality of data trains are multiplexed and transmitted from a transmitter side thereof and the thus transmitted data trains are received at a receiver side thereof and demultiplexed therein to reproduce the original data trains.

A hierarchical data transmission system basically comprises a side for dealing with data of a low order group and a side for dealing with data of a high order group. The high order group of data is produced by summing at least two low order groups of data, so that the high order group of data provides a very high transmission rate, and accordingly, the high order group contains a great amount of data.

(2) Description of the related art

A current optical fiber data transmission system has realized such ultra-high speed data transmission as 405 Mbps or 810 Mbps and a multiplexing apparatus is put into practical use in order to obtain such ultra-high speed data at the high order group signals.

In such a multiplexing apparatus, a plurality of low order group data trains are multiplexed into a plurality of intermediate speed data trains. Thereafter, these intermediate speed data trains are further multiplexed into high order group data trains. This procedure is also employed for demultiplexing the high order group data train. Such multiplexing apparatus can be mounted into an LSI unit of the function corresponding to the data transmission rate.

In such a case, an LSI for processing high order group data trains operates with a high speed clock signal, an LSI for processing intermediate data trains operates with an intermediate speed clock signal, and an LSI for processing low order group data trains operates with a low speed clock signal.

The low speed clock signal in the LSI for processing low order group data trains can be formed by the frequency division of the intermediate speed clock signal in the LSI for processing the intermediate data trains, and this intermediate speed clock signal can be formed by the frequency division of the high speed clock signal in the LSI for processing the high order group data trains.

FIG. 1 is a block diagram illustrating the structure of the multiplexing apparatus described above, while FIG. 2 is a timechart which indicates operation timings of respective portions.

The multiplexing apparatus of FIG. 1 multiplexes the 9-channel low order group data trains of 45 Mbps and outputs high order group signals of 405 Mbps. For multiplexing, the low order group data train of each channel, as the main signal, is synchronized to form a frame. Moreover, a frame synchronization signal and service channels for monitor and control which form subsignal must be inserted. These processings cannot be realized easily for the ultra-high speed data train as high as 405 Mpbs. Therefore, as shown in FIG. 1, the three intermediate speed data trains of 135 Mbps are respectively generated by multiplexing the 3-channel low order group data trains the synchronization signal of each channel and service channels are inserted at this stage, and thereafter the three intermediate speed data trains are interleaved to output the high order group data train of 405 Mbps.

In FIG. 1, the high speed operation clock of 405 Mbps is supplied, from the oscillator 4, to the multiplexing circuit MUX2 which generates the high order group data trains of 405 Mbps, and the intermediate speed operation clock of 135 Mbps which as been obtained by dividing the high speed clock sent from OSC 4 into 1/3 with a frequency divider F-DIV5 is supplied to the multiplex circuit MUX1 which generates the intermediate speed data trains of 135 Mbps. Moreover, the intermediate speed clock sent from F-DIV5 and a low speed operation clock of 45 Mbps which is obtained by dividing said intermediate speed clock into 1/3 with the frequency divider F-DIV6 is supplied to the interface circuits 11.about.19 for the low order group data trains of CH1.about.CH9. The data train service channels (for monitoring and controlling the transmitting lines and repeaters of 405 Mbps) to be multiplexed together with the low order group data trains (CH1.about.CH9) is 710 kbps, in this case, and this data train for service channels can be generated by multiplexing the low order group data trains of 11 channels of 64 kbps by the multiplexing circuit for service channel S-CHMUX3. The low speed operation clock for S-CHMUX3 can be obtained by dividing the low speed clock sent from F-DIV6 into 1/64 with the frequency-divider F-DIV7.

Interface 11.about.19 and S-CHMUX3 output a bit position information (timing signal) which is required for multiplexing at MUX1, MUX2 and this bit position information is input to MUX1 and MUX2. Namely, the multiplexing circuits MUX1, MUX2, S-CHMUX3 and interface circuits 11.about.19 are operating under the synchronized condition and the clock signal supplied from OSC4, F-DIV5, 6, 7 is the reference signal for such synchronization.

Here, as explained above, MUX1, MUX2, S-CHMUX3, interface circuits 11.about.19 are respectively mounted to LSI's and the clock signal is supplied from an external circuit. Since respective LSI's must be operated synchronously, although the operation speeds of LSI's are quite different, the clock obtained by sequentially dividing the reference clock of OSC4 is used as the clock signal.

However, the structure illustrated in FIG. 1 is accompanied by the following problems.

In case the high speed reference clock output from OSC4 like FIG. 1(1) is divided by F-DIV5, it is affected by the delay in signal propagation and operation of F-DIV5, so that an output of F-DIV5 is delayed by "a" in the phase (the rise timing of clock) in comparison with an output of OSC4 as shown in FIG. 2(2). Moreover, an output of F-DIV6 obtained by dividing an output of F-DIV5 is delayed, as shown in FIG. 2(3), by a+b in the phase in comparison with an output of OSC4, because delay (b) is accumulated. A delay in signal propagation and operation of interface circuit 11 is further accumulated in the CH1 timing signal 111 which is generated based on the clock signal sent from F-DIV6, so that the output of interface circuit 11 is delayed by "a+b+c" in the phase in comparison with an output of OSC4 as shown in FIG. 2(4). Similarly, the delay (b') is accumulated on an output of F-DIV7 obtained by dividing an output of F-DIV6 as shown in FIG. 2(5) and the delay (c') is also accumulated on the service channel timing signal 133 generated based on the clock sent from F-DIV7 and is output from S-CHMUX3 as shown in FIG. 2(6). Furthermore, in the timing signal based on the timing signals 111, 133 generated by MUX1, the delay (d) in propagation of signal and operation of MUX1 is accumulated to the delay (a+b"+c"), as shown in FIG. 2(7), which includes the influence of both delay (a+b+c) of an output of interface circuit 11 and delay (a+b+b'+c') of an output of S-CHMUX3. Finally, further the delay (e) is accumulated, as shown in FIG. 2(8), to the timing signal used within MUX2 which generates the high order group data train.

Therefore, as shown in FIG. 2(9), the timing signal used by MUX2 allows accumulation of a delay of (a+b"+c"+d+e) in comparison with the phase of reference high speed clock of OSC4. As shown in FIG. 2(9), MUX2 outputs the high order group data train 1 , 2 , 3 . . . in synchronization with the high speed clock (output of OSC4), but as shown in FIG. 2(8), when the timing signal used within MUX2 is delayed by (a+b"+c"+d+e) in comparison with the phase of high speed clock and when (a+b"+c"+d+e)>T (T is a period of high speed clock), the signal 1' is output in the timing where the signal 2 should be output. Therefore, the normal multiplex processing cannot be realized within MUX2.

In the case of demultiplexing the high order group data train into a plurality of low order group data trains, only the transmission direction of the high order group data train of 405 Mbps, intermediate speed data trains of 135 Mbps, low order group data train of 45 Mbps and service channel data train of 0.7 Mbps is reversed in FIG. 1 and the same structure is employed for the clock signal and timing signal. Therefore, this structure has a problem similar to that of the foregoing multiplex apparatus.

Above problems are generated, in the multiplex apparatus for ultra-high speed data train which sequentially multiplexes the low order group data trains in a plurality of stages, because the delay times are accumulated by sequentially dividing the reference high speed clocks for the LSI having a plurality of processing speeds.

Therefore, it is an object of the present invention to eliminate influence of delay by frequency division of the reference high speed clock and realize operation of the multiplexing circuits at the normal timing in the multiplexing apparatus providing a plurality of the multiplexing circuits having a plurality of processing speeds.

The present invention provides a hierarchical data transmission system which obtains a high speed second data train step-by-step multiplexing a plurality of first data trains, comprising;

a first signal processing part which operates at the processing speed corresponding to the first data train,

a third signal processing part which operates at the processing speed corresponding to the second data train,

a second signal processing part which operates at the processing speed corresponding to the intermediate speed of the first data train and second data train,

a first clock signal generating means which outputs a first clock signal of the speed corresponding to the processing speed of the third signal processing part,

a second clock signal generating means which generates a second clock signal of the speed corresponding to the processing speed of the second signal processing part by dividing the first clock signal, and

a third clock signal generating means which generates a third clock signal of the speed corresponding to the processing speed of the third signal processing part, when the first signal processing part operates in association with the third signal processing part, by dividing the second clock signal after the phase adjustment with reference to the phase information of the first clock signal.

FIG. 1 is a block diagram of a multiplexing apparatus which multiplexes low order group data trains in a plurality of steps,

FIG. 2 is a timing chart indicating signal waveforms at respective poins in FIG. 1,

FIG. 3 is a block diagram of an embodiment of the present invention,

FIG. 4 is a timing chart indicating signal waveforms at respective points in FIG. 3,

FIG. 5 is a circuit diagram of a frequency dividing circuit in FIG. 3,

FIG. 6 is a timing chart indicating signal waveforms at respective points in FIG. 5,

FIG. 7 is a block diagram of another embodiment of the present invention.

The like parts are given the like reference numerals throughout the drawings.

As is explained in detail with reference to FIGS. 1 and 2, delay time is accumulated because the intermediate and low speed clock signals are generated by sequentially dividing the reference high speed clock signal. Therefore, in the present invention, phase (rise timing) of clock signal is adjusted in the dividing circuit which generates a low speed clock, based on the reference high speed clock.

FIG. 3 is a block diagram of a multiplexing apparatus of the present invention and FIG. 4 is a timing chart indicating signal waveforms at respective points in FIG. 3. Since a method for multiplexing the low order group data trains of CH1.about.CH9 and service channel signal (0.7 Mbps) is the same as that explained for FIG. 1 it is not explained here.

The reference high speed clock signal is output from the oscillator OSC4. (FIG. 4(1)) The high speed clock signal output from OSC4 is supplied to the multiplexing circuit MUX2, and is also input to the frequency-divider F-DIV 5 which generates the intermediate speed clock, a clock generating part 100 which generates the low speed clock of 45 Mbps and a clock generating part 200 which generatates the low speed clock of 0.7 Mbps.

The clock generating part 100 adjusts the phase of the intermediate speed clock signal input from F-DIV5 by the phase adjust circuit 9, based on the high speed clock sent from OSC4. In this embodiment, as shown in FIG. 4(2), the phase of intermediate clock is advanced by the phase adjust circuit 9 so that the phase of intermediate speed clock including the delay (a) in propagation of signal and operation of F-DIV5 is matched with the phase of high speed clock. (FIG. 4(3))

Operations of the phase correction circuit 10 of clock generating part 200 which generated the clock of 0.7 Mbps are similar to that explained above. Therefore the low speed clock signal supplied from F-DIV6 to respective interface circuits INTF8 of CH1.about.CH9 allows addition of only delay (a') in operation of F-DIV6 and it becomes the clock having almost the same condition as the intermediate speed clock signal output from F-DIV5, namely being delayed when it passes a single circuit.

Therefore, MUX1 and interface circuits 8 can operate based on clock signals having almost the same condition, namely including a delay time added when such signals pass a single circuit, and accumulation of delay can be prevented. Phase of the low speed clock signal output from the clock generating part 200 can also be adjusted in the same way. (FIG. 4(5))

As explained with reference to FIG. 3, the low speed clock is genenerated after the phase of intermediate speed clock output from F-DIV5 is matched to the phase of high speed clock signal because it is required that S-CHMUX3 and interface circuits 8 are operated based on clock signals which are delayed almost in the same degree.

For example, if delay in propagation and delay in operation of timing signals 111.about.119, 133 to MUX1, MUX2 output from interface circuits 8, S-CHMUX3 are large in comparison with MUV1 and adjustment of delay time is insufficient even when the phase of the intermediate clock signal is matched with the high speed clock signal, it can be covered by leading the phase of intermediate clock signal by 1/2 period or one period than the phase of high speed clock signal.

Next, a practical circuit structure of the clock generating part 100 is illustrated in FIG. 5.

The circuit of FIG. 5 is explained with reference to the timing chart of FIG. 6 which indicates operation waveforms at respective points of FIG. 5.

A phase adjust circuit 9 is formed by three stages of cascade-connected flip-flops (FF). The intermediate speed clock signal (FIG. 6(2)) is input to the D input of the first stage FF91 from F-DIV5 and the reference high speed clock signal (FIG. 6(1)) is input to the C input from OSC4. Therefore, the Q output of FF91 becomes the intermediate speed clock signal which is delayed in the phase by one period T from the high speed clock signal as indicated by FIG. 6(3). The Q output of FF91 is then input to the D input of FF92, the Q output of FF92 is then input sequentially to the D input of FF93 and respective outputs are as shown in FIGS. 6 (4),(5). The phase of intermediate speed clock signal output from FF93 is finally delayed by three periods 3T from the phase of high speed clock signal, namely this intermediate speed clock signal is matched in the phase with the high speed clock signal.

The phase-adjusted intermediate speed clock signal output from FF93 is input to a 3 frequency-divider F-DIV6. As shown in FIG. 5, F-DIV6 is a ternary ring counter and FF61, 62, 63 respectively, output the signals in different phases and duty ratio of 1/3 obtained by dividing the intermediate speed clock signal into 1/3. (FIGS. 6(7),(8)) The AND gate 66 and OR gate 67 are provided for setting a duty ratio to 1/2. As shown in FIG. 6(9), the low speed clock signal obtained by dividing the high speed clock signal into 1/9 can be output from the OR gate 67. The low speed clock signal indicated as FIG. 6 (9) is described neglecting delay in operation of ring counter 6 (F-DIV6). As shown in FIG. 6(10), the low speed clock signal output from the OR gate 67 actually includes delay (a') in operation of the ring counter 6 (F-DIV6).

In the above explanation, the phase adjust circuit 9 matches the phase of intermediate speed clock signal with that of the high speed clock signal, but the Q output of FF91 is used as the intermediate speed clock signal in FIG. 5 on the occasion of obtaining the intermediate speed clock signal which is leading the phase of the high speed clock signal by 1/2 period (FIG. 6(3)) and moreover, the Q output of FF92 is used as the intermediate speed clock signal on the occasion of obtaining the intermediate speed clock signal which is leading the phase of the high speed clock signal by one period. (FIG. 6(4))

FIG. 7 illustrates a block diagram of multiplexing apparatus in accordance with another embodiment of the present invention. The multiplexing apparatus shown in FIG. 7 further multiplexes the high order group data trains of 405 Mbps output from the multiplexing apparatuses A, B (having the same structure as the multiplexing apparatus shown in FIG. 3) for two channels and thereby generates the high order group data train of 810 Mbps. The multiplexing circuit 22 which multiplexes the 405 Mbps of two channels output from the multiplexing apparatuses A, B is formed by a parallel/series converter which converts the 2-channel 405 Mbps data trains input in parallel into the series data train to be output alternately bit by bit. The operation clock of 810 Mbps of the multiplexing circuit 22 is output from the oscillator OSC4'. The operation clock of 405 Mbps of the multiplexing circuit MUX2 of the multiplexing apparatuses A, B is obtained by dividing the ultra-high speed clock signal of 810 Mbps output from OSC4' into 1/2. Structures of the other multiplexing apparatuses A, B are same as that of FIG. 3.

In the structure of FIG. 7, only the timing signal 122 sent from MUX2 is input to the multiplexing circuit 22 and the timing signals 111.about.119, 133 sent from interface circuits 8, S-CHMUX3 are input to MUX1, MUX2 as in the case of the structure of FIG. 3. Therefore, operation clock of MUX2 is generated with reference to the phase of clock signal of OSC4', while the operation clock of interface circuits 8, S-CHMUX3, MUX1 is generated with reference to the phase of high speed clock signal output from F-DIV21 as the operation clock of MUX2.

Namely, on the occasion of generating the operation clock of respective signal processing parts (interface circuits 8, S-CHMUX3, MUX1, MUX2), the reference clock signal for phase adjustment is the operation clock of the high speed signal processing part among those to which respective signal processing parts supply the timing signals. In other words, in the structure of FIG. 7, delay time of the timing signals 111.about.119, 133 output from INTF8, S-CHMUX3 does not apply any influence to operations of the multiplex part 22.