Clock Injector Circuit

This invention relates to time sequenced electronic circuitry such as digital logic circuitry. The invention has particular application for circuits such as Very Large Scale Integrated (VLSI) circuits which must process multiple signals which are not synchronized with one another. In a more general sense, this invention relates to techniques for modifying existing circuitry architecture without modifying the circuit itself.

With the advent of very large scale integrated (VLSI) circuits, new levels of performance have been achieved and new types of problems have arisen. One of the most pressing concerns is design modification. If the testing of a new VLSI device reveals a performance deficit, the conventional remedy is a redesign of the device. However, successive iterations of a VLSI device incur significant cost and time liabilities. Clearly, a method of altering performance by the addition of a small, efficient external circuit would be highly preferable.

Consider the typical avionics system shown in FIG. 1. In one specific mode of operation, remote terminal VLSI (RT VLSI) device 13, after servicing Bus A 15, is commanded to service Bus B 17. The logic internal to the RT VLSI 13 device creates an "enable channel" request pulse whose duration is nearly equal to the period of a clock sampling the pulse. This often occurs in systems where a response to given stimuli must take place within a limited time. For "enable Channel A" pulses, a Channel A clock is used to sample and for "enable Channel B" pulses, a Channel B clock is used. Therefore, for successive Channel A or for successive Channel B operations, the respective pulses and clocks are synchronous. For the cases where it is desired to switch channels from A to B or B to A, the "enable channel" pulse must be latched by the clock of the presently served channel. Since the Channel A and Channel B clocks may be inherently asynchronous, it is statistically possible for the rising edges of the clock to occur close to the rising and falling edges of the "enable channel" pulse generated by the other channel. When this happens, a "set-up" or "hold" time violation of the internal logic can cause the pulse to be "missed" and the requesting channel will not be served.

Accordingly, it is desired to modify the architecture embodied in an existing circuit without changing the circuit itself. It is further desired to improve the ability of a circuit to communicate with two different communication sources in which data from the two communication sources may not be synchronous with respect to one another. It is further desired to provide data transfer and enable functions between a single circuit and two disparate data communication lines.

Since the faulty operation results from a difference in the phase between two clocks, the invention "forces" the internal logic to "see" the clock edge it needs to successfully switch channels. In one aspect of this invention, signals present at the time channel switching occurs are employed to multiplex Channel A and Channel B clocks. When a signal from a first channel is present, implying selection of Channel A, the Channel B clock is "forced" to assume the same phase as the Channel A clock. Injection of an identically phased clock ensures that the "enable channel" request will be captured and serviced since the timing relationships are the same as those for successive servicing on one channel.

Another aspect of the invention employs a synchronous approach using oth a signal present at the time of the "enable channel" request and a master clock. A short pulse is generated (one cycle of the master clock) which causes the clock on each channel to reverse phase for the duration of that pulse. After the pulse, the clocks revert to their previous phases. This double phase reversal also ensures injection of the correct clock edge or transition needed to capture and service an .revreaction.enable channel" request.

FIG. 1 is a schematic block diagram showing a prior art system in which two communication buses are connected to a single signal processor;

FIG. 2 shows a clock injector circuit constructed in accordance with one embodiment of the invention;

FIG. 3 shows a clock injector circuit constructed in accordance with a second embodiment of the invention;

FIG. 4 is a timing diagram showing the timing sequence of the circuits of FIGS. 2 and 3;

FIG. 5 shows another embodiment of the invention, in which a master clock is used; and

FIG. 6 is an imaging diagram showing the timing sequence of the circuit of FIG. 5.

FIG. 1 shows a typical prior art system, in which a pair of data buses A,B are connected to a system through a serial communication and memory processing circuit 13, sometimes referred to as a RT VLSI circuit (remote terminal very large scale integrated circuit). Information on each bus is transferred through bus transceivers 25, 27, with Manchester decoder/encoders 31, 33 translating the information from Manchester encoded data in a format acceptable for transmittal to the data buses A, B and which appear at the transceivers 25, 27. This Manchester encoded data is translated by the Manchester encoders 31, 33 to and from nonreturn to 0 data, acceptable to the RT VLSI 13.

In order to avoid ambiguities in the transmission of data from buses A and B to the RT VLSI, the present invention provides an interface circuit which modifies the input to the RT VLSI and is inserted in place of input connections 15, 17. Referring to FIG. 2, one type of interface circuit 41 uses AND logic. Clock signals from channels A and B are provided to AND gates 51-54, and control signals are provided to the AND gates 51-54 in inverted and non-inverted form. The Channel A clock is provided to one AND gate 51 with an inverted signal from bus B. The Channel A clock is also provided to AND gate 54 with the non-inverted signal from bus A. The Channel B clock is matched with the non-inverted signal from bus B at AND gate 52 and with the inverted signal from bus A at AND gate 53. The outputs from AND gates 51 and 52 represent a delayed version of the Channel A clock and is provided as a clock signal for Channel A to the RT VLSI 13. The outputs of AND gates 53 and 54 provide a Channel B clock signal to RT VLSI 13. Resistors 57, 59 are used to match the bipolar circuitry of the AND gates with a complementary oxide semiconductor (CMOS) device which may be used as the RT VLSI 13. The AND gates 51-54 may be found on integrated circuit SN 54S09, available from National Semiconductor, shown as 61.

FIG. 3 shows an AND-OR-INVERT circuit which can be used in place of the circuit of FIG. 2. The circuit of FIG. 2 uses open collector devices, and the circuit of FIG. 3 uses separate gating elements 71,73 to achieve combinational logic.

In FIG. 3, the Channel A and Channel B clocks and signals are inverted and provided to AND gates 51'-54' in a manner similar to the signals provided to AND gates 51-54 in FIG. 2. The outputs of AND gates 51'-54' are provided to inverting OR (NOR) gates 71, 73. The outputs of these NOR gates 71, 73 are provided as clock signals to the RT VLSI 13. These gates, including inverters 81-84 used for inverting the clock and control signals, may be part of integrated circuit PAL 16R6A, available from Harris Semiconductor. This chip is a programmable array logic (PAL) device and is believed to simplify the implementation of this invention.

Refering to FIG. 4, whenever a data bit is received from one of the data buses, the AND gates 51-54 or 51-54 will delay the clock signals from the clocks until the clock signals are synchronized with the receipt of the data bit. As a practical matter, signal from the data bus associated with that data bit is relatively unaffected. This delay is maintained, usually over several clock cycles, for the duration of the data bit.

FIG. 5 shows a synchronous approach, for systems in which a master clock signal is available. In this system, an inject signal present at the time of the "enable channel" signal causes a clock signal from each bus to reverse phase for a period equal to the duration of the master clock pulse. A series of D flip flops 91-93 receives the "enable channel" signal as an inject signal, and receives a master clock signal. After a minimum time of one cycle of the master clock, a negative going inject signal causes the flip flop 92 Q bar output to go to a logic "one" state at the rising edge of the master clock. Until the next rising edge of the master clock, the flip flop 92 Q bar output and the flip flop 93 Q bar output are both a logic "one" and being applied to the inputs of AND gate 95, cause the "reverse phase" signal is applied as a logic "one" to one input of each of the two EXCLUSIVE OR gates 97, 95. When the "reverse phase" signal is a logic "zero", the output of each EXCLUSIVE OR gate 97, 98 is the Channel A or Channel B clock without inversion. When the "reverse phase" signal is a logic "one", the output of each EXCLUSIVE OR gate is the Channel A or Channel B clock inverted. Therefore, the channel clocks reverse phase when the "reverse phase" becomes a logic "one" and revert to their previous phases when it becomes a logic "zero". This creates a double phase reversal which also ensures injection of a correct clock edge or transition needed to capture and service each "enable channel" request.

Referring to FIG. 6, the master clock preferrably has a clock rate which is greater than that of either the Channel A or Channel B clocks. This is shown on the first three curves of FIG. 6. In the preferred embodiment, the master clock rate is at least twice that of either Channel A or Channel B. Whenever an "inject" signal is received, the flip flops 91-93 and EX OR gates 97,98 provide a pulse which is substantially shorter in duration than the duration of the clock signals. This pulse, shown in FIG. 6 as "Rev. Phase", is the result of ANDing the Q and Q outputs of flip flops 92 and 93. The delayed clock signals then are caused to be modified in accordance with the outputs of the AND gate 95, as shown on the bottom two curves of FIG. 6.