Fast Voltage Reference Stabilization Circuit

The present invention relates to a voltage reference stabilization circuit for supplying a reference voltage at a reference node and, more particularly, to a circuit for stabilizing this reference voltage.

Voltage references are used in analog type MOS circuitry to bias the circuits at a given operating point. Voltage references are commonly used with sense amplifiers and high impedance loads. Typically, voltage reference generation is accomplished through a voltage divider network. The reference voltage is then taken off a node of the voltage divider.

In CMOS circuits that have voltage referenced analog circuitry, the dc current path of the reference must be shut off when the part is in standby mode. Disabling the current path through the voltage divider allows the reference node to pull to VCC or VSS, or will tri-state the reference node.

However, a problem arises with this gating technique. When the reference is first enabled, the reference node must be pulled from VCC or VSS (or somewhere in between) to the normal reference voltage. The amount of time required for the reference node to be pulled to its normal reference level and stabilized at this level can be considerable, especially if the reference node is heavily loaded. Since in CMOS memory applications, the circuitry which uses the reference voltage partially determines the overall speed of the device, it is important to establish and stabilize a reference voltage as quickly as possible. In any event, the reference voltage must be established and stabilized before the circuitry using the reference voltage can be utilized. Thus, reducing the stabilization time will increase the overall speed of the device.

Therefore, an object of the invention is to provide a circuit which will stabilize the reference node near its normal operating point when the reference is disabled.

Another object of the invention is to provide a voltage reference stabilization circuit which improves the overall speed of the memory device by reducing the time required for the reference node to be pulled to its normal reference level.

A further object of the invention is to provide a voltage reference stabilization circuit which ensures that the circuitry which uses the reference voltage will function properly, by establishing the proper reference voltage before the circuitry is utilized.

These and other objects are obtained in the present invention by providing a voltage reference stabilization circuit having a reference voltage generator for supplying a reference voltage at a reference node. The reference voltage generator is enabled and disabled by enable circuit, while a clamping circuit clamps the reference node at a clamp voltage approximately equal to the reference voltage whenever the reference voltage generator is disabled by the enable means.

An advantage of the voltage reference stabilization circuit provided by the present invention is the elimination of a large part of the delay in establishing a reference voltage. By substantially eliminating the delay, the proper functioning and the speed performance of the analog circuitry that uses the voltage reference is increased. This increases the overall speed of the memory device.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

The FIGURE is a partial schematic and block diagram of a preferred embodiment of the present invention.

In the drawing figure, a reference generation circuit 10, shown as a block, is typically a voltage divider network through which current is passed. The reference voltage is produced by the reference generation circuit 10 at the reference node 11. The analog circuitry using this voltage at the reference node as a reference, which includes sense amplifiers, and other loads, are not shown.

In most CMOS circuits that contain voltage referenced analogs circuitry, the reference generation circuit must be turned off periodically. The enable circuit in the present invention includes an enable reference generator 12 (shown in block diagram form) which produces an enable signal that controls the turning on and off of the reference generation circuit 10. The enable reference generator 12 supplies the signal through inverter 16 to a transistor 18 which is connected between VCC and the reference generation circuit 10. The enable reference generator 12 is also connected to the gate of transistor 14 which is connected between the reference generation circuit 10 and ground. The transistor 18 is shown in FIG. 1 as a P-channel device, while transistor 14 is an N-channel device. Thus, a high signal generated by the enable reference generator will turn on both transistors 14 and 18 and the reference generation circuit 10 is enabled.

A low signal from the enable reference generator 12 produces a high at transistor 18 and a low at the gate of transistor 14, thereby turning both devices off and tri-stating the reference generation circuit 10 and the reference node 11. This prevents current flow from the reference node 11 through the reference generation circuit 10.

The inverted enable reference signal received at the gate of transistor 18 is also received by the transistor 24 of the voltage reference clamp indicated in dashed lines as reference numeral 22. Transistor 24 is shown in FIG. 1 as an an N-channel device. Because transistor 24 is an N-channel device and transistor 18 is a P-channel device, when the same enable or disable signal is present at both gates, they will assume opposite on/off states with respect to one another. The drain of transistor 24 is connected to VCC while the source of transistor 24 is connected to both the drain and the gate of transistor 26 of the voltage reference clamp 22. The source of transistor 26 is connected to the reference node 11. Like transistor 24, the transistor 26 is an N-channel device.

By providing that transistor 18 is turned off when transistor 24 is turned on and vice versa, it is assured that the reference generation circuit 10 is turned on when the voltage reference clamp 22 is turned off, and vice versa.

The two N-channel transistors 24, 26 connected between VCC and the reference node act to supply a voltage that is approximately equal to the reference voltage supplied by the reference generation circuit 10 when it is enabled. Although two transistors 24, 26 are shown, it is contemplated to provide any number of transistors or at least one transistor and any number of voltage dropping loads in the voltage reference clamp 22 that would give a certain voltage drop from VCC to the reference nodal, which would approximate the reference voltage.

In operation, the reference generation circuit 10 is enabled by a high enable reference signal from the enable reference generator 12, while this same signal disables the voltage reference clamp 22. The reference generation circuit 10 produces a reference voltage at reference node 11. The circuitry not shown in FIG. 1 that uses this reference voltage can then be enabled.

The enable reference generator 12 then outputs a low enable signal which disables N-channel device 14 and the inverted low enable signal turns off the P-channel device 18, thereby tri-stating the reference generation circuit 10. The tri-stating of the reference generation circuit 10 when the voltage reference circuit is disabled prevents any current flow from the reference node through the reference generation circuit 10.

At the same time the reference generation circuit 10 is disabled, the voltage reference clamp 22 is enabled by the low enable reference signal which is inverted by inverter 16 and received at the gate of N-channel device 24. The devices 24 and 26 of the voltage reference clamp 22 are turned on and a voltage is produced at the reference node 11 which is the voltage VCC minus the V.sub.t drops introduced by the devices 24 and 26. This voltage (VCC-2V.sub.t) is approximately equal to the reference voltage. Thus, the reference node 11 is clamped to a voltage close to the reference voltage when the reference generation circuit is disabled.

When once again the reference generation circuit 10 is enabled and the voltage reference clamp 22 is disabled, the voltage at the reference node 11 has to pulled only slightly, since it was at a voltage approximately equal to the reference voltage. As noted earlier, this increases the speed of stabilization of the reference node 11 at the proper reference voltage, and allows the voltage referenced analog circuitry to be turned on sooner, and thereby increases the overall speed of the device.

Although the preferred embodiment described shows a specific configuration of P and N-channel devices and supply voltages, this is not to be taken by way of limitation, as the specific polarities of the supply voltages and the P and N-channel devices can be changed accordingly without departing from the scope of the invention. Similarly, other types of switching devices are contemplated, instead of the channel devices described above.

Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. The spirit and scope of the present invention are to be limited only by the terms of the appended claims.