US 4,801,892 AGrant
Current Mirror Circuit
Issue Date:1989-01-31
•5 Claims
•1 Drawing Sheets
Abstract
A current mirror circuit of the present invention has the structure that the diode-connected second transistor is connected in series to the first transistor, the third and fourth transistors have bases which are respectively connected to the bases of the first and second transistors which are connected in series, and the collector of the fifth transitors, whose emitter and base are connected between the base and collector of the first transistor, is connected to the collector of the fourth transistor.
Metadata
Assignee
- Seikosha Co., Ltd.
Inventors
- Akira Yamakoshi
- Toyohiko Fujita
- Kunihiko Tsukakoshi
- Shinji Anraku
Application Information
Application Number:US 0943754
Filing Date:1987-09-09
Priority Date:1986-09-11
Art Unit:252
Classifications
IPC:
H03F 304
Field of Search:
330323257;288315;316
Patent Drawings (1 sheets)
Description
Field of the Invention
The present invention relates to a current Miller circuit.
Background of the Invention
A current mirror circuit used generally has the structure indicated in FIG. 2. A current flows as indicated in the figure by connecting a current source I to the diode-connected transistor T.sub.6. Namely, when a base current of the transistors T.sub.6, T.sub.7 is considered as I.sub.B, a current (I-2I.sub.B) flows into the transistors T.sub.6 and T.sub.7.
The circuit explained above has a disadvantage that a current in the mirror side is lowered by 2I.sub.B.
In addition, a collector current of transistor T.sub.7 is varied due to current modulation by the Early effect depending on a collector potential of the mirror side.
Summary of the Invention
It is an object of the present invention to lower the reduction of current in the mirror side and suppress the influence by the Early effect.
Brief Description of the Drawings
FIG. 1 is an electric circuit indicating an embodiment of the present invention, and
FIG. 2 is an electric circuit indicating an example of a current mirror circuit of the prior art.
Detailed Description of the Invention
In FIG. 1, a diode-connected second transistor T.sub.4 is connected in series to the first transistor T.sub.1 and the bases of the third and fourth transistors T.sub.2, T.sub.5 are respectively connected to the bases of the transistors T.sub.1, T.sub.4. Moreover, the emitter and base of the fifth transistor T.sub.3 are respectively connected to the base and collector of transistor T.sub.1 and the collector is connected to the collector of transistor T.sub.5.
In the above structure, when a current source I is connected, a collector current I.sub.CT4 of transistor T.sub.4 can be expressed as follow,
and an emitter current I.sub.ET4 is expressed as follows with relation to base current I.sub.B2.
In this case, a collector current I.sub.CT1 of transistor T.sub.1 is reduced only by the base curent 2I.sub.B1 /h.sub.FE of transistor T.sub.3 and can be expressed as follows.
Since a collector current I.sub.CT2 of transistor T.sub.2 becomes equal to that of transistor T.sub.1,
A collector current I.sub.CT5 of transistor T.sub.5 is lowered by I.sub.B2 from the above value and can be expressed as follows.
Since the collector current 2I.sub.B1 of the transistor T.sub.3 is finally added to the collector current of transistor T.sub.5,
Here, when I.sub.B1 =I.sub.B2 =I.sub.B,
and the influence of I.sub.B on the Miller side becomes 1/h.sub.FE in comparison with that of the circuit of the prior art.
Since the collector voltage of transistor T.sub.2 is set to the same voltage as that of terminal P, namely 2V.sub.BE when the base-emitter voltage of transistors T.sub.1 .about.T.sub.3 is set to V.sub.BE by cascade-connecting the transistor T.sub.5, the influence of the Early effect can also be suppressed.
According to the present invention, reduction of current in the mirror current side can be set to 1/h.sub.FE and the Early effect of the transistor in the mirror current output side can also be supressed, and thereby the current mirror circuit just suited to integration can be obtained.
Claims
What is claimed is:
1. A current mirror circuit comprising a first transistor, a second diode-connected transistor connected in series to said first transistor and having a collector receptive of an input current, a third transistor having a base which is connected to a base of said first transistor, a fourth transistor connected in series to the third transistor with a base connected to a base of said second transistor and a collector from which an output current is obtained, and a fifth transistor having an emitter which is connected to the base of said first transistor a base connected to a collector of said first transistor and a collector directly connected to the collector of said fourth transistor.
2. A current mirror circuit comprising a first transistor, a diode-connected second transistor connected in series to said first transistor, a third transistor having a base which is connected to a base of said first transistor, a fourth transistor connected in series to the third transistor with a base connected to a base of said second transistor, and a fifth transistor having an emitter which is connected to the base of said first transistor, a base connected to a collector of said first transistor and a collector directly connected to a collector of said fourth transistor, an output for an output signal current I-2I.sub.B /h.sub.FE at the collector of the fifth transistor, an input for an input signal current I to a collector of said second transistor, wherein I.sub.B is the base current of said first and third transistors and h.sub.FE is the grounded emitter current amplification of the first, second, third, fourth and fifth transistors.
3. A current circuit comprising: a first transistor having an emitter, a base and a collector; a second transistor having an emitter connected to the collector of the first transistor, a collector and a base connected together, wherein the collector is receptive of an input current applied thereto; a third transistor having a base connected to the base of the first transistor, an emitter connected to the emitter of the first transistor and a collector; a fourth transistor having an emitter connected to the collector of the third transistor, a base connected to the base of the second transistor and a collector from which an output is obtained; and a fifth transistor having an emitter connected to the base of the first transistor, a base connected to the collector of the first transistor and a collector directly connected to the collector of the fourth transistor.
4. The circuit according to claim 3, wherein all of the transistors have the same polarity.
5. The circuit according to claim 3, wherein the transistors are of the pnp type.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3936725 | 1976-02-01 | Schneider |