Integrated Circuit With Improved Monitoring Function by Use of Built-in Elements

The present invention relates to a semiconductor integrated circuit having a function of monitoring circuit elements formed therein by use of built-in monitoring elements.

Recent improvement in semiconductor integrated circuits has been remarkable and the integrating scale of integrated circuits has become large due to reduction in size of elements fabricated in integrated circuits and by fine lithographic technology. Accompanied by such integration density, however, deviation in manufacturing parameters such as concentration of impurities has become comparatively large and it has been required to reduce such deviation. Moreover, in order to reduce manufacturing cost, large-sized wafers such as 5 inch wafers are widely employed in place of 3 inch wafers. However, it is difficult to uniformly fabricate each chip included in the same wafer in case of such large-sized wafers. For example, impurity concentration of a center portion of a wafer is different from that of a peripheral portion of the wafer, and hence deviation in functional parameters is inevitably present among chips formed on the same wafer.

Under such circumstance, it has been practiced that reference elements, or monitoring elements are built-in each chip which are fabricated through the same sequence of manufacturing processes as that for fabrication of the circuit elements (functional elements) of the integrated circuit. The characteristics or parameters of the functional elements are determined by checking the reference elements. For example, in order to check parameters of transistors fabricated in each chip, a reference transistor is additionally fabricated in each chip through the same process. Since there is similarity in parameters between the reference transistor and the functional transistors, parameters of the functional transistors can be predicted from the parameters of the reference transistor. Heretofore, such reference elements are fabricated with independent conductive pads solely connected thereto. In order to contact testing probes with the conductive pads, the conductive pads are required to have a sufficient area which facilitates contact between the testing probes and the conductive pads. Accordingly, the area occupied by the conductive pads for the reference elements shares a large portion in each chip. Thus, according to the prior art, there has been limitation in promoting the integration scale of integrated circuits.

In order to avoid the above problem, it may be conceivable that the size of the conductive pads are reduced. However, in such case, it is difficult to contact testing probes with the conductive pads of reduced-size, and automated testing of the reference elements becomes impractical.

It is an object of the present invention to provide a semiconductor integrated circuit with improved arrangement of the reference element.

It is another object of the present invention to provide a semiconductor integrated circuit of the type having a function of monitoring circuit elements thereof by use of built-in reference elements in a highly integrated structure.

The semiconductor integrated circuit according to the present invention is of the type having at least one reference element fabricated simultaneously with functional elements on the same semiconductor chip, and featured in that the reference element is connected through a switching element to the same bonding pad to which a part of the functional elements is electrically connected and the switching element assumes a conductive state only when a voltage outside the normal operating voltages of the functional elements is applied to the bonding pad to which the switching element is connected.

According to the present invention, the same bonding pads are shared by the functional elements and the reference element according to the range of voltage applied thereto. Therefore, any independent conductive pads only for the reference elements are no more necessary.

Therefore, the integrated circuit can be fabricated in highly integrated structures.

FIG. 1 is a block diagram showing an example of integrated circuits according to a prior art;

FIG. 2 is a block diagram showing another example of integrated circuits according to a prior art;

FIG. 3 is a block diagram showing an integrated circuit according to the present invention;

FIG. 4 is a diagram explaining operations of the integrated circuit of FIG. 3;

FIG. 5 is a circuit diagram of an input circuit employed in the circuit of FIG. 3;

FIG. 6 is a circuit diagram of an output circuit employed in the circuit of FIG. 3; and

FIG. 7 is a sectional diagram of the zener diode employed in the invention:

Referring to FIG. 1, a prior art integrated circuit of the type having reference elements is explained.

A functional circuit 10 is formed on a center portion of a semiconductor chip 1. Bonding pads P.sub.1 to P.sub.10 are formed on the periphery of the chip 1 and electrically connected to the functional circuit 10. The functional circuit 10 includes NPN transistors such as Q.sub.1, PNP transistors such as Q.sub.2, resistors such as R.sub.1 and aluminum wirings such as WL.sub.1 as functional elements. On the periphery of the chip 1 outside the boundary of the functional circuit 10, there are formed a reference NPN transistor QR.sub.1 which is fabricated simultaneously with the NPN transistors in the functional circuit 10, a reference PNP transistor QR.sub.2 which is fabricated simultaneously with the PNP transistors in the functional circuit 10, a reference resistor RR.sub.1 which is fabricated simultaneously with the resistors in the functional circuit 10, and a reference wiring WLR.sub.1 fabricated at the same time as WL.sub.1. Conductive pads Pd.sub.1 to Pd.sub.8 are connected to these reference elements as illustrative. For example, the conductive pads Pd.sub.1 and Pd.sub.2 are connected to a collector and a base of the reference NPN transistor QR.sub.1, respectively. In this arrangement, the conductive pads Pd.sub.1 to Pd.sub.8 have substantially the same size as the bonding pads P.sub.1 to Pd.sub.10. Thus, parameters of the elements in the functional circuit 10 are predicted by measuring parameters of the reference elements. Such measuring of the reference elements is conducted by contacting testing probes to the conductive pads Pd.sub.1 to Pd.sub.2. For example, parameters of NPN transistors Q.sub.1 are predicted by measuring electrical parameters of the reference NPN transistor QR.sub.1 through the conductive pads.

However, according to this circuit, the conductive pads Pd.sub.1 to Pd.sub.8 occupy a large area of the semiconductor chip 1 and hence, the reduction in the chip size has been prevented.

FIG. 2 shows another prior art integrated circuit. In this figure, portions or elements corresponding to those in FIG. 1 are designated by the same references. In this circuit, in place of the conductive pads Pd.sub.1 to Pd.sub.8 of FIG. 1, mini-pads Pm 1 to Pm 8 are employed. As is clear from FIG. 2, the size of the mini-pads Pm 1 to Pm 8 is small as compared with the boding pads P.sub.1 to P.sub.10 and the conductive pads Pd.sub.1 to Pd.sub.8.

Accordingly, the area occupied by the mini-pads Pm 1 to Pm 8 on the chip 1 is remarkably reduced as compared to the circuit of FIG. 1. However, since the size of each mini-pad is small, it is difficult to contact a testing probe with the mini-pad. Thus, efficiency in manufacturing, especially in testing, is deteriorated.

Referring to FIG. 3, a semiconductor inregrated circuit according to an embodiment of the invention is explained. In this figure, the same or similar portions and elements as those in FIG. 1 are indicated by the same reference characters.

A functional circuit 10 is connected to bonding pads P.sub.1 to P.sub.10 to which external leads (not shown) are electrically connected. The functional circuit 10 includes input circuits IB.sub.1, IB.sub.2 and IB.sub.3 and an output circuit OB.sub.1. An NPN transistor Q.sub.1, a PNP transistor Q.sub.2, a resistor R.sub.1 and a wiring WL.sub.1 may be located within the input or output circuits IB.sub.1, IB.sub.2, IB.sub.3, OB.sub.1 or outside them. The pads P.sub.2, P.sub.3 and P.sub.4 are connected to inputs of the input circuits IB.sub.1, IB.sub.2 and IB.sub.3, respectively. The pad P.sub.8 is connected to an output of the output circuit OB.sub.1. The pads P.sub.1 and P.sub.10 are connected to the functional circuit 10 to supply a power voltage V.sub.CC and a ground potential GND. Other pads P.sub.5, P.sub.6, P.sub.7 and P.sub.9 are connected to the functional circuit 10 in a conventional manner. A reference NPN transistor QR.sub.1, a reference resistor RR.sub.1, a reference PNP transistor QR.sub.2, and a reference wiring WLR.sub.1 are provided along the periphery of the chip 1. These reference elements are fabricated at the same time with elements forming the functional circuit 10. According to the invention, these reference elements are connected to the bonding pads P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.7, P.sub.8 and P.sub.9 through zener diodes Z.sub.1 to Z.sub.8 as voltage switching elements. Namely, a collector and a base of the reference NPN transistor QR.sub.1 is coupled to the pad P.sub.2 via the zener diode Z.sub.1 and to the pad P.sub.3 via the zener diod Z.sub.2, respectively. The zener diodes Z.sub.1 and Z.sub.2 are connected in the reverse direction from the pads P.sub.2 and P.sub.3 towards the transistor QR.sub.1. The both ends of the reference resistor RR.sub.1 is connected to the pads P.sub.3 and P.sub.4 through the zener diodes Z.sub.3 and Z.sub.4, respectively. The emitter and base of the reference PNP transistor QR.sub.2 are connected to the pads P.sub.8 and P.sub.7 via the zener diodes, respectively. Similarly, the ends of the reference wiring WLR.sub.1 are connected to the pads P.sub.9 and P.sub.8 via the zener diodes Z.sub.8 and Z.sub.7, respectively. All the zener diodes Z.sub.1 to Z.sub.8 are inserted between the pads and the reference elements in the reverse direction viewing from the respective pads. Each of the zener diodes Z.sub.1 to Z.sub.8 assumes conductive state when a high voltage such as 10 volts or more is impressed across itself in the direction reverse to its PN junction while assumes non-conductive when the voltage across the diode is less than the above high voltage in the reverse direction. The value of the power voltage V.sub.CC for the functional circuit 10 is less than 7 volts and the voltage range of the signal applied to or output from the pads is within the range of -0.5 to 5.5 volts in the normal function mode of the circuit 10.

Accordingly, in the normal function mode, each of the zener diodes Z.sub.1 to Z.sub.8 are non-conducting so that all the reference elements are electrically isolated from the pads because voltages applied to the pads are less than the above high voltage and the reference elements do not affect the operation of the function circuit 10.

With the reference to FIG. 4, an explanation of the operation is given with respect to the reference NPN transistor QR.sub.1 by way of example.

FIG. 4 shows relationship between a collector current IP.sub.2 of the reference transistor QR.sub.1 and a voltage VP.sub.2 applied at the pad P.sub.2 with a base current IP.sub.3 applied from the pad P.sub.3 to the reference transistor QR.sub.1 being employed as parameter. When the voltage VP.sub.2 is smaller than the zener voltage VZ.sub.1 of the zener diode Z.sub.1, the diode Z.sub.1 is non-conducting. When the voltage applied to the pad P.sub.3 is lower than the zener voltage of the diode Z.sub.2, the diode Z.sub.2 assumes non-conducting state thereby to isolate the reference transistor QR.sub.1 from the pad P.sub.2 and from the input circuit IB.sub.1. When the voltage VP.sub.2 takes a value of the zener voltage VZ.sub.1 or more, the diode Z.sub.1 is turned to the conducting state so that the collector of the transistor QR.sub.1 is electrically connected to the pad P.sub.2. Under this condition of VP.sub.2, when the voltage applied to the pad P.sub.3 exceeds the zener voltage of the diode Z.sub.2, a base current IP.sub.3 is applied to the base of the transistor QR.sub.1 and the collector current IP.sub.2 is caused in accordance with the amount of the base currents IP.sub.3, 2IP.sub.3 . . . 4IP.sub.3 as illustrated. Thus, the characteristics of the reference transistor QR.sub.1 can be detected through the pads P.sub.2 and P.sub.3. Similarly, the characteristics of the reference PNP transistor QR.sub.2 can be measured by applying voltages higher than the zener voltages of the diodes Z.sub.6 and Z.sub.5 to the pads P.sub.7 and P.sub.8, respectively.

In case where the reference resistor RR.sub.1 is measured, a high voltage more than the sum of the zener voltage VZ.sub.3 of the zener voltage Z.sub.3 and a forward voltage VF.sub.4 of the diode Z.sub.4 should be applied between the pads P.sub.3 and P.sub.4 to render the two diodes Z.sub.3 and Z.sub.4 conductive. The value of the voltages (V.sub.Z3 +V.sub.F4) is almost the same as V.sub.Z3 because the V.sub.F4 is less than 1 volt. Also, the reference wiring WLR.sub.1 is measured in the same way.

FIG. 5 shows an example of the input circuit IB.sub.1, IB.sub.2 and IB.sub.3. This example is composed of an input stage of a diode D.sub.11, a pull-up resistor R.sub.11, an inverting transistor Q.sub.11, a collector resistor R.sub.12, an emitter resistor R.sub.13 and a diode D.sub.12, and an output stage of a transistor Q.sub.12 having a collector IO.sub.1 from which an output is derived. This circuit is basically a so-called DTL circuit. An input terminal IN is connected to the pad P.sub.2, P.sub.3 or P.sub.4. Between the input IN and the ground GND, the diode D.sub.11, a base-emitter junction of Q.sub.11 and the diode D.sub.12 are present in series. Therefore, even when the voltage above the zener voltage such as 10 to 15 volts is applied to the pad P.sub.2, P.sub.3 or P.sub.4, no current path occurs between the input IN and the ground GND. Therefore, this type of input circuit is suitable for the invention because the input circuit does not affect the measuring of the reference element.

FIG. 6 shows an example of the output circuit OB.sub.1. The circuit is composed of a transistor Q.sub.13 receiving an internal signal 2I.sub.1 and a push-pull connection of transistors Q.sub.14 and Q.sub.15. The pad P.sub.8 is connected to a collector of the transistor Q.sub.15. A diode D.sub.13 is formed of a base-collector junction of a vertical transistor and therefore a high breakdown voltage. Also, the collector - base junction of the transistor Q.sub.15 has a high breakdown voltage. Accordingly, even when the high voltage above the zener voltage is applied to the pad P.sub.8, no breakdown occurs in the output circuit OB.sub.1 and the output circuit OB.sub.1 does not affect the reference element.

FIG. 7 shows an example of the zener diodes Z.sub.1 to Z.sub.8. Each of the zener diodes employes a vertical transistor structure composed of a P type substrate 50, an N type collector 51, a P type base 53, an N type emitter 54 and a P type isolation region 5 L. The substrate 50 and the N type epitaxial layer 51 are common with those of the reference elements and the functional elements in the circuit 10. The base - emitter junction of this transistor is employed as the zener diode in which an emitter electrode 56 and a base electrode 55 are used as an anode and a cathode of the zener diode. In this case, the zener voltage of about 7 to 9 volts is obtained.

In the above-mentioned testing mode, it is favorable that the pad P.sub.1 for V.sub.CC supply is kept open or at ground potential in order to avoid unnecessary current flow in the functional circuit.

As has been described above, the present invention provides the improved semiconductor integrated circuit having reference elements. It is apparent that the present invention is not limited by the above embodiment, but applicable to any type of integrated circuits.