Voltage to Frequency Conversion Circuit With a Pulse Width to Period Ratio Proportional to Input Voltage

This invention relates to a voltage to frequency conversion circuits, and particularly to a circuit which can be used effectively in applications in which operation over a very wide temperature range is desirable. Such applications include analog multiplication systems, optically-coupled isolation amplifier system, fibre optic transmission systems, two-wire transmission systems, and analog to digital conversion systems.

In these applications, it is essential that the pulse width to period ratio depend only on the input voltage and a reference voltage and not on other components in the system. This specification describes a voltage to frequency conversion circuit which makes this possible by using a single resistor to charge and discharge a capacitor in a sequence which brings the charge on the capacitor back to the same value once each cycle of operation. As a consequence, neither the value of the resistor nor the value of the capacitor is critical in determining the pulse width to period ratio of the output waveform.

Further, the circuit of this invention uses an integrator-gated latch configuration to provide a controlled capacitor charging-discharging function. Prior art voltage to frequency conversion circuits using the charging-discharging principle are shown in the patents to Chapman U.S. Pat. No. 3,970,943, Honig U.S. Pat. No. 4,410,812, and Mizumoto et al U.S. Pat. No. 4,446,439. These references disclose conversion circuits which are complex circuits as contrasted with that of the subject invention, in which the pulse width to period ratio of the output waveform is keyed to the ratio of the input voltage to a reference voltage, and is independent of the values of the resistor and the capacitor of the integrating circuit.

Accordingly, this invention contemplates the provision of an improved voltage to frequency conversion circuit which includes an integrator circuit and a pulse generating circuit wherein only the input voltage and a reference voltage are instrumental in determining the pulse width to period ratio of the output waveform.

FIG. 1 shows a preferred embodiment of the voltage to frequency converter of the subject invention.

FIG. 2a shows output voltage signals for the circuit of FIG. 1 when the input voltage is substantially less than half the value of the reference voltage.

FIG. 2b shows output voltage signals for the circuits of FIG. 1 when the input voltage is half the reference voltage.

FIG. 2c shows output voltages for the circuit of FIG. 1 in which the input voltage is greater than half the reference voltage.

Referring particularly to FIG. 1, the voltage to frequency conversion circuit includes an integrating circuit consisting of an operational amplifier 10 having a signal input line 12 to which the input signal V.sub.t is applied. The output line 14 from the amplifier is connected to the operational amplifier control lead 16 through feed back line 18.

The output of the operational amplifier 10 is applied along line 14 to the pulse generating circuit generally indicated at 20 through integrator output circuit terminal 22 which is connected through lines 23 and 24 to second operational amplifier 34 and third operational amplifier 36.

The reference voltage line 26 is grounded at 25, with the reference voltage being applied to terminal 30 from which its value is successively and equally reduced through the three equal resistors, generally indicated as R at 31, 32 and 33. The voltage applied to the negative signal input terminal of amplifier 34 is two thirds the value of the reference voltage. The voltage applied to the positive signal input terminal of operational amplifier 36 is one third the value of the reference voltage, since the resistors 31 and 32 reduce such value at this input point to one third the reference voltage.

The reference voltage line and operational amplifiers 34 and 36 form a gating circuit.

A set-reset latch circuit is formed by the cross-connected NOR gates 37 and 38 which act as a flip-flop circuit, with output line 27 providing a zero voltage at Q when the latch is set and a high voltage equal to V.sub.ref when the latch is reset and with output terminal 28 and output waveform terminal 40, generally indicated by V.sub.2 and Q, providing a high voltage equal to V.sub.ref when the latch is set and a zero voltage when the latch is reset. A signal return line 42 containing resistor 44 (integrating resistor R.sub.4) is connected to control lead 16 of operational amplifier 10 and is connected at that point to feed back line 18 which contains the integrator capacitor 46, generally designated C.sub.4.

The integrator circuit consists of the operational amplifier 10 and the resistor 44 and charging capacitor 46. When a positive input signal voltage is applied to input line 12 and the voltage at Q of the pulse generating circuit generally indicated at 20 is at zero volts, a current flow will be produced along line 42 which will charge the capacitor 46. The output terminal 22 of the integrator will increase in voltage from a lower fixed voltage equal to one third of the reference voltage V.sub.ref to a fixed voltage equal to two thirds of the reference voltage V.sub.ref. This is accomplished by the manner in which the operational amplifiers 34 and 36 are biased. The increasing voltage value at output 22 of the integrator will be applied along lead line 23 to the positive signal input terminal of operational amplifier 34 and when the voltage at 34 exceeds two thirds of the reference voltage V.sub.ref, the voltage applied to the negative input terminal of operational amplifier 34, the set-reset flip flop will be set and the voltage at Q will go to a high value equal to V.sub.ref. This will result in a current flow along line 42 which will discharge the cpacitor 46 so that the output 22 of the integrator will decrease in voltage from the high fixed voltage level of two thirds of the reference voltage V.sub.ref, downwardly to the one third reference voltage level applied to the positive input terminal of amplifier 36. When the voltage at output 22 of the integrator falls below the one third reference voltage level applied to the positive signal input lead of operational amplifier 36, the flip flop will be reset, the voltage at Q will go to zero volts, and the cycle will repeat itself. The set-reset circuit 37, 38 will produce a high voltage output at terminal 28 which is generally indicated at V.sub.2 and has a high output pulse value equal to the reference voltage during the discharge phase of the charging capacitor 46.

This can be seen by an inspection of the pulses shown in FIGS. 2a, 2b and 2c. In FIG. 2a in which the input voltage V.sub.t is substantially less than half the reference voltage, the output at terminal 22 showing the voltage V.sub.1 at the output of the integrating circuit is shown in which the successive discharge-charging cycle between the one third reference voltage and two third reference voltage levels are illustrated by the curve generally indicated at 50 in which the discharging segment 52 is followed by charging slope 53, discharging slope 54 and second charging slope 55. The discharging of the capacitor through the latch circuit along the output line Q provides a voltage V.sub.2 pulse shown at 56 which has a duration M. The complete period for the charge-discharge cycle is indicated as T at 58. The charge balance for the charging capacitor 46 would be as follows : ##EQU1## where V.sub.t is the input voltage, R.sub.4 is resistor 44, T is the period, V.sub.ref is the reference voltage, and M is the pulse duration.

This equation can be reduced to: ##EQU2## showing that the ratio of the input voltage to the reference voltage equals the pulse duration divided by the period. Note that the resistive and capacitive value are not a factor in this relationship and that the average value of the output waveform 40 is exactly equal to V.sub.t.

FIG. 2b shows the charge-discharge curve 60, and pulse pattern, when the input voltage V.sub.t is equal to half the reference voltage. The voltage output at integrator output terminal V.sub.1 is shown by the successive discharge and charge slopes 62, 63, 64 and 65 of curve 60 which alternately charge between the upper and lower fixed voltage levels of one third and two thirds of the reference voltage.

In this instance, the pulse 66 appears at the latch output line Q and terminal 28 an 40, note the pulse width M of 66 is half of the period duration T, as indicated at 68. Succeeding output pulse 69 is of similar duration as output pulse 66.

FIG. 2c shows a third set of voltage versus time plot for V.sub.1 terminal voltage and V.sub.2 terminal voltage, where the input signal voltage V.sub.t is greater than half the reference voltage. In this instance, the discharge-charge curve generally indicated at 70 has long discharge voltage slope sections 72 and 74 and abrupt charging slope sections 73 and 75. The pulse duration M for pulses 76 and 79 are a very high percentage of the period duration T as indicated at 78. These curves for FIG. 2a, FIG. 2b, and FIG. 2c illustrate the relationship of equation 2 indicated above, in which the proportion of input signal voltage to reference voltage is equal to the pulse duration divided by the period duration and the average value of the output waveform 40 is exactly equal to V.sub.t.

The output frequency f.sub.0 which appears at the output terminal 40 of FIG. 1, can be calculated as follows: ##EQU3## where .gamma.=1/3 for the circuit of FIG. 1.

Transposing of this equation gives: ##EQU4## and then ##EQU5##

Frequency f.sub.0 increases from 0 when the input signal voltage V.sub.t is equal to zero to a maximum of one quarter of the reciprocal of the product of gamma and the resistive and capacitive values, R.sub.4 and C.sub.4, when the input signal voltage V.sub.t is one half of the reference voltage. It then decreases to 0 as the input signal voltage V.sub.t increases from half the reference voltage to the full reference voltage. The maximum output frequency is therefore: ##EQU6## and this is equal to ##EQU7## for FIG. 1.

The simplicity of the circuits can be more fully appreciated when it is noted that in FIG. 1 the pulse generating circuit generally indicated at 20 is a CMOS 555 timer circuit with appropriate pin connections followed by an inverter. The integrator circuit includes an operational amplifier chip, and the integrator resistor and the charging capacitor. This simple five element circuit is much less complex than previous circuits.

The circuit of FIG. 1 can also be operated in a bipolar mode by connecting 25 to -V.sub.ref rather than to ground and powering the NOR gates so that Q is equal to V.sub.ref when the latch is set and Q is equal to -V.sub.ref when the latch is reset. In such a case, ##EQU8## and ##EQU9## This modification extends the range of the input signal voltage V.sub.t to -V.sub.ref .ltoreq.V.sub.t .ltoreq.+V.sub.ref.

While this invention has been described as having preferred design, it is understood that it is capable of further modification, uses and/or adaptations of the invention following in general the principle of the invention and including such departures from the present disclosure as come within known or customary practice in the art to which the invention pertains, and as may be applied to the essential features set forth, and fall within the scope of the invention of the limits of the appended claims.