Image Pickup Apparatus

The present invention relates to an image pickup apparatus in which blooming can be effectively suppressed and an interlacing effect can be obtained.

Conventionally, as disclosed in the Official Gazette of Japanese Laid-open Patent Application No. 138371/1981, in a solid state image sensor such as a CCD or the like, there has been considered a method whereby excessive carriers are extinguished using surface recombination for prevention of blooming in place of providing overflow drains in the light receiving surface.

This method has advantages such that sensitivity is high since the opening ratio of the light receiving surface is not sacrificed and horizontal resolution power is raised since the degree of integration can be improved, and the like.

FIGS. 1 to 3 are diagrams for explaining such a blooming preventing method due using surface recombination, in which FIG. 1 is a front view showing an ordinary frame transfer type CCD.

In the diagram, a light receiving part 1 consists of a plurality of vertical transfer registers having photosensitivity.

A storage part 2 consists of a plurality of vertical transfer registers which are shielded against the light.

A reference numeral 3 denotes a horizontal transfer register. The information in each vertical transfer register in the storage part 2 can be stored in this horizontal transfer register by simultaneously shifting it by one bit. Then, by allowing the register 3 to perform the horizontal transfer operation, a video signal can be derived from an output amplifier 4.

In general, the information formed in each vertical transfer register in the light receiving part 1 is transferred vertically to the storage part 2 within a vertical blanking interval based on the standard television system and is sequentially read out line by line by the horizontal transfer register 3 within the next vertical scan interval.

It is now assumed that the light receiving part 1, storage part 2 and horizontal transfer register 3 are each two-phase driven and respective transfer electrodes are indicated by P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, and P.sub.6, and respective transfer clocks are represented by (.phi..sub.p1, .phi..sub.p2), (.phi..sub.p3, .phi..sub.p4) and (.phi..sub.p5, .phi..sub.p6).

FIG. 2 is a diagram showing a potential profile below such transfer electrodes P.sub.1 to P.sub.6. For example, a low-potential portion and a high-potential portion (as seen by electrons) are formed by means of ion implantation or the like below each electrode which is provided over a P-type silicon substrate 6 and separated thereform by an insulation layer 5. For instance, when a voltage -V.sub.1 at a low level is applied to the electrodes P.sub.12, P.sub.4 and P.sub.6 and a voltage V.sub.2 at a high level is applied to the electrodes P.sub.1, P.sub.3 and P.sub.5, potentials as indicated by a solid line in the diagram are formed. On the other hand, when a low-level voltage V.sub.1 is applied to the electrodes P.sub.1, P.sub.3 and P.sub.5 and the high-level voltage V.sub.2 is applied to the electrodes P.sub.2, P.sub.4 and P.sub.6, potentials as indicated by a broken line in the diagram are formed.

Therefore, by applying alternating voltages having mutually opposite phases to the electrodes P.sub.1, P.sub.3, P.sub.5 and the electrodes P.sub.2, P.sub.4 and P.sub.6, the carrier is sequentially transferred in one direction (to the right in the diagram).

On one hand, an alternate-long-and-short dash line in FIG. 2 indicates potentials in the case where a large positive voltage V.sub.3 is applied to the electrodes. These potential wells are in the reversed state, so that excessive carriers over a predetermined amount will have been extinguished by recombining with the majority carriers.

FIG. 3 is a diagram showing the relation between the voltage applied to the electrodes and the shape of the internal potential as mentioned above with respect to the direction of thickness of the semiconductor substrate 6. It will be understood from the diagram that the potential wells are shallow for the electrode voltage V.sub.3 and the excessive carrier enters the second state in that it can recombine with the majority carrier at the interface with the insulation layer.

On the other hand, the accumulation state as the first state occurs at the electrode voltage -V.sub.1, so that the majority carrier can be easily collected around the interface and, for instance, this majority carrier can be supplied from a channel stopper area (not shown).

Therefore, for instance, by alternately applying the voltages -V.sub.1 and V.sub.3 to the electrode P.sub.1 while a barrier is formed and maintained by applying the voltage -V.sub.1 to the electrode P.sub.2, the minority carrier which is accumulated below the electrode P.sub.1 is limited to less than a predetermined amount.

However, such an arrangement as shown in FIG. 2 has the drawback that its efficiency in removal of the excessive charges is low. Namely, in transfer electrodes, transfer efficiency is generally improved by preventing the surface recombination of charges upon storage and transfer of charges. For this purpose, the potential well below the transfer electrode has to be sufficiently deep and the area of the bottom surface of the well has to be wide.

On the other hand, the opposite conditions are needed to efficiently recombine the charges.

That is, it is desirable that the area of the bottom surface of the potential well below the electrode be narrow to a certain extent so that the charges efficiently overflow and are recombined.

Consequently, in the conventional technology, there occurs a problem that an increase in transfer efficiency causes the efficiency in recombination to be deteriorated and, contrarily, an increase in recombination efficiency results in a decrease in transfer efficiency.

In addition, in such a CCD using charge recombination, there is a problem that the clock for recombination is mixed with the output signal and becomes noise of a fixed pattern. Therefore, a onventional apparatus is arranged such that the recombination clock is supplied only during the horizontal blanking interval.

In such a CCD of the conventional type, the frame transfer is started within the vertical blanking interval; therefore, the generation of the recombination clock is stopped during the interval of, e.g., about 1/2 H (horizontal interval) immediately before that interval. Thus, a charge transfer is started in the state in which a great amount of charges has been stored which may cause a smear phenomenon or blooming phenomenon. Therefore, a method whereby the device is driven even during the vertical blanking interval is also considered. However, this method is undesirable because of the problem of a large electric power consumption or the like.

It is an object of the present invention to eliminate the foregoing drawbacks in the conventional technology and to provide an image pickup apparatus in which transfer efficiency and recombination efficiency are high and an interlacing effect is derived.

It is another object of the present invention to provide an image pickup apparatus in which the blooming or smear can be prevented by performing the recombining operation for a predetermined interval immediately before the frame transfer without an increase in electric power consumption and which is also effective even in the case where the charge transfer is exceptionally performed in other intervals than the vertical blanking interval.

It is still another object of the invention to provide an image pickup apparatus with less noise and less electric power consumption.

To accomplish the above objects, an image pickup apparatus of an embodiment according to the present invention comprises: first and second areas for converting incident light to charges; recombining means for allowing a portion of charges in the second area to be recombined with the majority carrier; and control means for allowing charges to be respectively stored in the first and second areas and also making the recombining means operative, and for controlling the first and second areas and the recombining means in a manner such that an amount A.sub.INT of charges stored in the first area and an amount D.sub.INT of charges which remain in the second area without being recombined satisfy the relation of A.sub.INT <D.sub.INT. Therefore, a blooming preventing capability can be raised and an interlacing effect can be also obtained.

An image pickup apparatus of another embodiment according to the present invention comprises: first and second areas for converting incident light to charges; recombining means for allowing a portion of the charges in the second area to be recombined with the majority carrier; control means for allowing charges to be respectively stored in the first and second areas and also making the recombining means operative, and for controlling the first and second areas and the recombining means in a manner such that an amount A.sub.INT of charges stored in the first area and an amount D.sub.INT of charges which remain in the second area without being recombined satisfy the relation of A.sub.INT <D.sub.INT ; and suppressing means for suppressing a part of added information of the charges in the first and second areas. Therefore, deterioration in interlacing effect in case of high luminance can be made inconspicuous and an image pickup apparatus having high performance within a wide luminance range can be obtained.

An image pickup apparatus of another embodiment according to the present invention comprises: a light receiving part for converting an optical image to a charge signal; recombining means for allowing a part of charges in the light receiving part to be recombined with the majority carrier; and control means for forming a signal to allow the charge signal in the light receiving part to be transferred and for allowing the recombining means to perform the recombining operation for a predetermined time immediately before the transfer of the charge signal. Therefore, by supplying a pulse for charge recombination immediately before the frame transfer, the excessive charges stored until the start of frame transfer are reduced to a suitable value, thereby making it possible to prevent the blooming or smear which would otherwise occur because of the inability of all of the excessive charges to be transferred upon frame transfer.

In addition, it is possible to eliminate an increase in electric power consumption such as occurs in the case of operation during the vertical blanking interval

Also, an image pickup apparatus of still another embodiment according to the present invention comprises: a light receiving part for converting an optical image to a charge signal; recombining means for allowing a part of charges in the light receiving part to be recombined with the majority carrier; a storage part for storing the charge signal in the light receiving part; and control means for controlling the light receiving part including the recombining means in a manner such that the potential state in the light receiving part becomes a predetermined constant level during the time when the signal in the storage part is read out. Therefore, an electrical power can be saved and no noise is mixed since .phi..sub.AB and .phi..sub.PI are set to constant potentials in the case of recording in the still mode.

On the other hand, since those potentials at this time are set to be lower than the potential at the storage part as "seen" by the electrons, even if blooming occurs in the light receiving part, it does not occur in the storage part.

Other objects and features of the present invention will become apparent from the following description with reference to the accompanying drawings .

FIG. 1 is a schematic diagram showing a conventional CCD image sensor;

FIG. 2 is a diagram for explaining a method of driving the sensor shown in FIG. 1;

FIG. 3 is a diagram for explaining the principle of the surface charge recombination;

FIG. 4 is a diagram showing an example of an arrangement of an image pickup apparatus of the present invention;

FIG. 5 is a cross sectional schematic diagram showing an example of a structure of an image sensor which is suitable for use in the image pickup apparatus of the present invention;

FIG. 6 is a diagram showing an example of an electrode pattern of the sensor shown in FIG. 5;

FIG. 7 is a timing chart for explaining the first embodiment of the method of driving the image pickup apparatus of the invention;

FIG. 8 is a diagram for explaining the potential state of the sensor shown in FIG. 5;

FIG. 9 is a timing chart for explaining the second embodiment of the method of driving the image pickup apparatus of the invention;

FIG. 10 is a diagram for explaining the potential state in the second embodiment of the invention;

FIG. 11 is a diagram for explaining a narrow channel effect;

FIG. 12 is a timing chart for the driving of the image pickup apparatus of the third embodiment of the invention.

FIG. 13 is a diagram showing an example of an arrangement of a clock driver;

FIG. 14 is a timing chart for the operation of the clock driver of FIG. 13;

FIG. 15 is a diagram showing an example of an arrangement of the fourth embodiment of the invention;

FIG. 16 is a cross sectional schematic diagram showing an example of a structure of an image sensor which is fitted for use in the fourth embodiment of the invention;

FIG. 17 is a timing chart illustrating operation in the still mode;

FIG. 18 is a diagram showing an example of an arrangement of the clock driver.

The present invention will now be described hereinbelow with respect to an embodiment.

FIG. 4 is a diagram showing an example of an image pickup apparatus using an image sensor according to the present invention. In this embodiment, a case of a frame transfer type CCD of the single-phase driving method will be explained.

In the diagram, the similar parts and components as those shown in FIGS. 1 to 3 are designated by the same reference numerals.

In this embodiment, a clock .phi..sub.AB for allowing the excessive charges to be extinguished by recombining them with the holes at the center of the surface recombination is applied together with a transfer clock .phi..sub.PI to the light receiving part 1.

On the other hand, transfer clocks .phi..sub.PS and .phi..sub.S are respectively applied to the storage part 2 and horizontal transfer register 3.

A clock driver CKD serves as control means for supplying those clock pulses .phi..sub.PI, .phi..sub.AB, .phi..sub.PS, .phi..sub.S, etc., to the image sensor. A clock generator CKG generates timing signals to form those pulses. A processing amplifier (or suppressor) PAP serves as suppressing means and includes a KNEE circuit or a .gamma.-converting circuit or the like to cut off or non-linearly suppress a signal over a predetermined level as will be explained later. An encoder ECD converts a video signal which is supplied through the suppressor PAP to a signal based on the standard television system such as, e.g., an NTSC signal.

FIG. 5 is a diagram showing schematically structures of electrodes and potentials in the cross section in the boundary area between the light receiving part 1 and the storage part 2.

In the diagram, P.sub.PI denotes a transfer electrode to apply the transfer clock .phi..sub.PI to the light receiving part; P.sub.AB is a recombination control electrode serving as recombining means for applying the recombination clock .phi..sub.AB ; and P.sub.PS is a transfer electrode to apply the transfer clock .phi..sub.PS to the storage part. In the diagram, a solid line indicates the potential state in the case where low-level voltages are applied as the clock pulses .phi..sub.PI and .phi..sub.PS and high-level voltage is applied as the clock pulse .phi..sub.AB. A broken line represents the potential state in the case where the pulses .phi..sub.PI and .phi..sub.PS are at a high level and the pulse .phi..sub.AB is at a low level.

Potential stairs as shown in the diagram are formed in a substrate SS due to ion implantation. On one hand, a P-type inverting layer, for instance, to constitute a virtual electrode (although they are not shown) is formed in the lower portion of the insulation layer that is not covered by the electrodes P.sub.PI, P.sub.PS and P.sub.AB, namely, in the boundary portion between the insulation layer and the semiconductor substrate. Therefore, the potential in the semiconductor area that is not covered by the electrodes is not changed due to the bias to each electrode.

In the diagram, it is assumed that an area of X is a first area and an area of Y is a second area. As shown in the diagram, the second area indicates the area including the electrode P.sub.AB. These first and second areas shall apply similarly to an image pickup apparatus due to a multi-phase driving method instead of limiting to the single-phase driving method.

FIG. 6 is a diagram showing an example of an electrode pattern in the areas shown in FIG. 5. Channel stops CS obstruct the horizontal movement of the charges.

According to the embodiment shown in FIGS. 4 to 6, a width of the electrode P.sub.AB for the charge recombination can be made sufficiently smaller than a width of the transfer electrode P.sub.PI, so that a high removing efficiency can be derived in the removal of the excessive charges.

On one hand, in the CCD image sensor of the single-phase driving method, the operation to recombine the charges can be performed independently of the transfer operation.

Further, a structure for control of the recombination of the image sensor in the embodiment can be formed due to a step of forming polysilicon gates for the electrodes which can be manufactured by the same process as in case of the channel stop and due to an ion implantation step to form the stairs of the internal potentials.

FIG. 7 is a waveform diagram showing the clock pulses .phi..sub.AB .phi..sub..phi..sub.PI, .phi..sub.PS, and .phi..sub.S which are generated from the clock driver CKD to drive the image sensor shown in FIG. 4 and of an output V.sub.OUT of the amplifier 4.

In the diagram, a vertical sync signal V.sub.D is obtained at every television field. The clocks .phi..sub.PI and .phi..sub.PS as many as the number of pixels in the vertical direction of the light receiving part 1 and storage part 2 are supplied synchronously with the V.sub.D for the intervals of t.sub.1 to t.sub.2 and t.sub.3 to t.sub.4 such that, for example, these clocks are in-phase.

Due to this, the charges in each pixel cell in the light receiving part 1 are transferred and stored into the corresponding storage cell in the storage part.

At this time, in the present invention, the clock .phi..sub.AB which is applied to the electrode P.sub.AB is fixed at a voltage level V.sub.4 to prevent the potential below the recombination electrode P.sub.AB from obstructing the transfer of the charges. For instance, as shown in FIG. 8, this voltage V.sub.4 is the voltage value such that the potential level below the electrode P.sub.AB lies between the upper and lower limits of the potential level in the virtual electrode section. More particularly, the voltage V.sub.4 is set at a level between the upper and lower limits of the potential in the area excluding the portion below the electrode P.sub.AB in the second area Y.

The time interval of t.sub.1 to t.sub.2 corresponds to the vertical blanking interval of the standard television signal.

A plurality of clocks .phi..sub.AB are supplied for the interval of t.sub.2 to t.sub.3 at an arbitrary timing. The clocks .phi..sub.AB may be periodically and continuously supplied or may be supplied only for the horizontal blanking interval.

With an increase in number of clocks .phi..sub.AB which are supplied, the removing capability of the excessive charges is raised.

The charges in the storage part are read out one line by one synchronously with the horizontal period by the clocks .phi..sub.PS and .phi..sub.S for the interval of t.sub.2 to t.sub.3 and are outputted as the horizontal line signals. This interval of t.sub.2 to t.sub.3 corresponds to the vertical scan interval of the standard television signal.

Next, the second embodiment of the driving method in the case where a video camera is constructed using such an image sensor provided with means for preventing the diffusion of the excessive charges as mentioned above will be described.

FIG. 9 is a timing chart showing output pulses from the clock driver CKD in the foregoing second embodiment.

As shown in the diagram, different points between this embodiment and the embodiment shown in FIG. 7 are as follows. Namely, a level of the .phi..sub.PI is fixed at a level V.sub.5 which is nearly an intermediate level between -V.sub.1 and V.sub.2 during the storage intervals until t.sub.1, between t.sub.2 to t.sub.a, and after t.sub.4. The rising and trailing of the .phi..sub.PI are switched at every field at the end of the storage intervals.

These points will now be explained. By setting the .phi..sub.PI at the V.sub.5 level during the storage intervals, as shown in FIG. 10(a), potential wells A and C are respectively formed in the substrate below the transfer electrode P.sub.PI and in the substrate below the virtual electrode and the charges are stored in the respective wells.

A plurality of pulses .phi..sub.AB are supplied during those intervals as shown in FIG. 9, so that the potential below the eletrode P.sub.AB increases and decreases as shown in FIG. 10(a). However, the excessive charges collected near the insulation layer 5 among the charges in the well B which are produced when this potential decreases are recombined with the holes when the potential increases, so that these excessive charges are extinguished and do not leak into the well A.

It is now assumed that amounts of charges which enter the wells A and C (or B) during the storage interval in the first field until time t.sub.1 in FIG. 9 are A.sub.INT and C.sub.INT (or B.sub.INT), respectively, as shown in FIG. 10(a). Next, upon vertical transfer which starts from time t.sub.1 in FIG. 9, as shown in FIG. 10(b), by increasing the .phi..sub.PI from the intermediate level V.sub.5 to the V.sub.2 level at the start of transfer, the charges stored in the portions .circle.1 ' and .circle.2 , .circle.2 ' and .circle.3 , . . . are added and are transferred to the storage part. On the other hand, in the second field, by decreasing the .phi..sub.PI from the intermediate level V.sub.5 to the -V.sub.1 level at the start (time t.sub.a) of transfer, the charges stored in the portions of .circle.1 and .circle.1 ', .circle.2 and .circle. 2 ', .circle.3 and .circle.3 ', . . . are added. In this way, the interlacing operation can be executed by changing the combination of the charges that are added at every field.

With such an arrangement, the interlacing . effect can be obtained by use of few pixels, and at the same time the dark current level does not change at every field and the flicker is difficult to occur.

In addition, this embodiment has a feature such that the relation of A.sub.INT <D.sub.INT is satisfied in the case where a saturation charge amount of the well A is A.sub.F, a saturation charge amount in the portions consisting of the wells B and C other than the well A is D.sub.F and an amount of residual charges which are not recombined in the wells of the portions other than the well A is D.sub.INT.

This point will now be explained hereinbelow.

In this embodiment, unless the following relation is satisfied, the total amount of A.sub.INT +D.sub.INT will have exceeded the amount of charges that can be transferred; consequently, there will have been some amount of charges left without being transferred.

Namely, (A.sub.INT +D.sub.INT) has to be less than the smaller value between the saturation charge amounts A.sub.F and D.sub.F.

Therefore, in case of this embodiment, A.sub.INT +D.sub.INT is set to, for example, the minimum value of the A.sub.F and D.sub.F, i.e., about 70% of the Q.sub.SAT. When it is assumed that this value is the maximum storage charge amount Q.sub.max and an amount of light necessary to obtain the charges of Q.sub.max is L.sub.max, the amounts A.sub.INT and D.sub.INT may be set to be equal, i.e., A.sub.INT =D.sub.INT in order to allow the interlacing operation to be performed until the light amount reaches from 0 to L.sub.max.

However, although the interlacing operation can be performed due to the above method, a satisfactory function to remove the excessive charges is not derived.

That is, in order to secure the elements as many as required in the screen size of, e.g., 2/3 inches, it is actually necessary to set a width W of the electrode P.sub.AB to a value near the minimum line width, i.e., to a value of 3 to 4 .mu.m.

A method whereby the number of locations for the recombination is increased is considered to raise the recombining capability of the sensor under such situation; however, in this case, a drawback of deterioration in yield is caused.

On the other hand, a method whereby an area of the electrode P.sub.AB for recombination is enlarged is also considered.

Practically speaking, as shown in FIG. 11, in the case where the width W of electrode is set to 3 .mu.m due to the narrow channel effect, the effective width of the well which is formed below the electrode and which contributes to the recombination is about 0.5 .mu.m. On the other hand, when the width W of electrode is set to 4 .mu.m, the effective width of the well which contributes to the recombination is about 1.5 .mu.m. Therefore, if a sufficient amount of charges which can be collected in this well exist, the amount of charges which can be erased at every clock .phi..sub.AB is improved to about three times. However, in this case, if the amount of charges which can be collected into the well B below the electrode P.sub.AB is not so large, the recombining capability is not derived as described before.

On one hand, the value Q.sub.max becomes a certain constant if the number of pixels and area of the CCD are determined. Therefore, it is necessary to reduce the amount A.sub.INT by an amount of increase in D.sub.INT.

Therefore, in this embodiment, a control is made by the clock driver in a manner such that there is the relation of

between an amount of charges A.sub.INT in the well belcw the electrode P.sub.PI as the first area and an amount of residual charges D.sub.INT which are not recombined in the wells below the virtual electrode and recombinaticn electrode as the second area. Thus, the interlacing effect is obtained and the high recombining capability can be also derived.

In this case, for instance, if the width W of P.sub.AB is 4 .mu.m and the D.sub.INT is set to be 50% of the Q.sub.SAT and the A.sub.INT is set to be about 20% of the Q.sub.SAT, the interlacing capability will be up to about 57% of the L.sub.max. Namely, the interlacing effect is not obtained for the light amount exceeding the above value of 57%, but the anti-blooming capability is improved to about three times the conventional capability. The video camera in this embodiment is provided with suppressing means for setting the interlacing capability to be less than 20% of the L.sub.max with regard to most of the picture plane and for suppressing the signal component corresponding to the light amount exceeding this value due to compression or the like as shown in FIG. 4; therefore, the deterioration in interlacing capability in case of high luminance is inconspicuous.

FIG. 12 is a diagram showing the drive timings in the third embodiment of the present invention. This embodiment comprises: the light receiving part for converting an optical image to a charge signal; recombining means for allowing a part of charges in the light receiving part to be recombined with the majority carrier; and control means for forming a signal to allow the charge signal in the light receiving part to be transferred and for allowing the recombining means to perform the recombining operation for a predetermined time immediately before the transfer of the charge signal. Therefore, it is possible to reduce the excessive charges stored until the start of frame transfer to a proper value by supplying a pulse for charge recombination immediately before the frame transfer, thereby making it possible to prevent the blooming or smear which is caused since those excessive charges cannot be transferred upon frame transfer.

FIG. 12 shows a waveform diagram of the clock pulses and the like which are generated from the clock driver CKD to drive the image sensor shown in FIG. 4, in which a vertical blanking signal V.sub.BLK is outputted for the intervals of t.sub.11 to t.sub.13 and t.sub.14 to t.sub.16 synchronously with the vertical sync signal V.sub.D which is obtained at every television field.

H.sub.BLK denotes a horizontal blanking signal.

That is, t.sub.11 to t.sub.13 corresponds to t.sub.1 to t.sub.2 in FIGS. 7 and 9; t.sub.13 to t.sub.14 corresponds to t.sub.2 to t.sub.3 ; and t.sub.14 to t.sub.16 corresponds to t.sub.3 to t.sub.4. By supplying a plurality of pulses .phi..sub.AB for the intervals of t.sub.11 to t.sub.12 and t.sub.14 to t.sub.15, the excessive charges immediately before the vertical transfer are removed. Further, the clocks .phi..sub.PI and .phi..sub.PS as many as the number of pixels in the vertical direction of the light receiving part 1 and storage part 2 are supplied for the intervals of t.sub.12 to t.sub.13 and t.sub.15 to t.sub.16 such that they are substantially in-phase, thereby allowing the charges in each pixel cell in the light receiving part 1 to be transferred and stored in the corresponding storage cell in the storage part. These points are similar to those in the embodiment shown in FIGS. 7 and 9.

Next, FIG. 13 is a diagram showing an example of an arrangement of the clock driver CKD. FIG. 14 shows a timing chart for the operation of the clock driver CKD. In FIGS. 13 and 14, .phi..sub.D denotes a pulse which is generated twice for one horizontal interval, and TRG is a frame transfer trigger pulse for allowing the frame transfer to be executed. This pulse TRG is generated for the vertical blanking interval or at a timing relative thereto.

The pulse TRG may be outputted at arbitrary timing other than the vertical blanking interval as disclosed in, e.g., Japanese Patent Application No. 61098/1983. In such a case, the image storing time can be also controlled by the timing of this pulse TRG.

A D flip flop D.sub.1 receives the pulse TRG as the clock and its input D is always at a high level, so that an output T.sub.1 becomes a high level due to the trigger (at time t.sub.17 ) in response to the TRG. Therefore, an output T.sub.2 is generated (at time t.sub.18 ) after the delay time of only two clocks .phi..sub.D due to flip flops D.sub.2 and D.sub.3, so that this causes the flip flop D.sub.1 to be cleared and the output T.sub.1 becomes a low level. The length of this interval can be reduced or increased by increasing or decreasing the number of D flip flops. In this embodiment, this interval of t.sub.17 to t.sub.18 is set to one horizontal interval; however, it becomes H/2 interval by omitting the D.sub.2. After the output T.sub.2 became a high level, an output T.sub.3 of the D flip flop D.sub.4 becomes a high level at time t.sub.19 and after predetermined clocks, the flip flops D.sub.3 and D.sub.4 are cleared (at time t.sub.20) in response to an output CARRY of a counter CNT. Thus, the outputs T.sub.2 and T.sub.3 become a low level and the frame transfer is finished.

The clocks .phi..sub.PI, .phi..sub.PS and the like can be generated from a pulse generator SG as shown in FIG. 12; therefore, they are not shown here in particular.

The horizontal blanking signal H.sub.BLK is set at a low level by an AND gate .sub.2 while the output T.sub.2 is at a high level. An output of the AND gate A.sub.2 is supplied to an OR gate OR.sub.1 and an output T.sub.1 ' is generated from the OR gate OR.sub.1 due to the OR of the output T.sub.1 and output of the AND gate A.sub.2. Thus, the output T.sub.1 ' becomes the timing signal to make the .phi..sub.AB operative. Namely, the output T.sub.1 ' becomes a high level either for the horizontal blanking interval excluding the vertical transfer interval of t.sub.18 to t.sub.20 or for the interval of t.sub.17 to t.sub.18 when the output T.sub.1 is at a high level corresponding to the portion immediately before the output T.sub.2.

A clock signal CLK is logically multiplied with the output T.sub.1 ' by an AND gate A.sub.1 to get AND, thereby turning on a switch SW.sub.1 to set the .phi..sub.AB at the voltage level V.sub.3 for only the interval when both clock CLK and output T.sub.1 ' are at a high level. While the T.sub.2 is at a high level, a switch SW.sub.2 is turned on, thereby setting the .phi..sub.AB at the intermediate voltage level V.sub.4. In other cases, a switch SW.sub.3 is closed due to an output of an NOR gate N.sub.1, so that the .phi..sub.AB is set at the voltage level -V.sub.1.

As described above, according to the third embodiment of the present invention, the excessive charges stored until the start of frame transfer are reduced to a proper value by supplying the pulse for recombination of the charges immediately before tte frame transfer, thereby making it possible to prevent the blooming or smear that is caused since all of the excessive charges cannot be transferred upon frame transfer.

On one hand, a large electric power consumption in case of the operation for the vertical blanking interval is not caused; therefore, the invention is also effective even in the case where the frame transfer is performed in other intervals than the vertical blanking interval for an exceptional use such as to obtain a storage time shorter than the field period.

Next, FIG. 15 is a diagram showing the forth embodiment of the present invention, in which the similar parts and components as those shown in FIGS. 1 to 14 are designated by the same reference numerals.

OFD denotes an overflow drain to dran the excessive charges. This overflow drain OFD is arranged on the side of the light receiving part 1 opposite to the storage part 2 and is biased by a constant positive voltage V.sub.OD.

MS indicates a mode setting circuit to switch the output states of the various kinds of pulses that are generated from the clock driver CKD and can change over the frequency of the clock .phi..sub.AB for recombination. The mode settint cicuit MS also controls the turn-on and turn-off of an analog gate AG.

RCC is a recorder. SW.sub.1 is the switch for allowing the still signal to be recorded. When this switch is turned on, the mode setting circuit is automatically set into the still mode as will be explained later and the driver CKD is controlled, and at the same time the gate AG is opened at a predetermined timing for one field or one frame interval.

FIG. 16 is a diagram showing schematically structures of electrodes and potentials in the cross section in the boundary region of the light receiving part 1 and storage part 2 in the fourth embodiment.

A numeral 6E denotes an n+ area constituting the overflow drain.

When the switch SW.sub.1 is OFF, namely, in the movie photograph mode, the clock pulses as shown in FIG. 12 are generated from the clock driver CKD to drive the image sensor shown in FIG. 15 and the output V.sub.OUT of the amplifier 4 and the like are generated.

Next, FIG. 17 shows a timing chart in the case where the switch SW.sub.1 is turned on to perform the photographing operation in the still mode. When the switch SW.sub.1 is turned on at arbitrary time t.sub.0, a signal MODE.phi. for the still mode which will be explained later is generated from the mode setting circuit MS synchronously with the trailing edge (at time t.sub.3) of the next vertical blanking pulse V.sub.BLK.

This signal MODE.phi. is held until time t.sub.14 of the leading edge of the next vertical blanking pulse V.sub.BLK.

On one hand, the pulse .phi..sub.AB is fixed to the potential V.sub.3 and the pulse .phi..sub.PI is fixed to the potential V.sub.2 for the interval when the signal MODE.phi. is being outputted. The analog gate AG is turned on for one field interval (t.sub.11 to t.sub.14) synchronously with the vertical sync signal V.sub.D immediately after the switch SW.sub.1 was turned on.

With respect to the other pulses, they are similar to the case in FIG. 12.

Therefore, during the interval when the signal in one field is read out in response to the pulses .phi..sub.PS and .phi..sub.S synchronously with the vertical sync signal V.sub.D after the switch SW.sub.1 was turned on, the analog gate AG leads this signal to the recorder RCC, so that the signal in one field is recorded.

Particularly, the pulse .phi..sub.AB is at a constant level for the interval of t.sub.13 to t.sub.14 during that interval; therefore, no noise is mixed while the signal V.sub.OUT is being read out and an electric power consumption can be also saved.

On the other hand, the potential barrier in the light receiving part 1 is lower than the barrier in the storage part 2 for almost of the interval (t.sub.13 to t.sub.14). Namely, in FIG. 16, the potential in the area X is as indicated by a broken line and the potential in the area Y is as shown by a solid line, so that even if the pulse .phi..sub.AB is in the inoperative state, the overflowed charges do not substantially leak into the storage part.

Moreover, since the overflow drain is provided on the side of the light receiving part 1 opposite to the storage part 2, the overflowed charges in tne light receiving part 1 at this time will have been drained to the power supply VOD.

Although the potential in the area X in the storage part decreases for only the horizontal blanking interval in response to the pulse .phi..sub.PS, the effective image signal (image signal formed until time t.sub.11) is moved in the storage part 2 downwardly in FIG. 15 whenever it decreases. Thus, it is possible to ignore the charges which leak from the light receiving part 1 into the storage part 2 while the pulse .phi..sub.PS is at a high level.

FIG. 18 shows an example of an arrangement of the clock driver CKD, in which the similar parts and components as those shown in FIG. 13 are designated by the same reference numerals.

In the diagram, D.sub.1 to D.sub.4 denote D flip flops; OR.sub.1 to OR.sub.4 are OR gates; CNT the counter; SG the pulse generator to produce the pulses .phi..sub.PI and .phi..sub.PS ; SW.sub.1 to SW.sub.4 analog switches; DIV.sub.1 and DIV.sub.2 1/2-frequency dividers; A.sub.2 to A.sub.7 AND gates; and NOR.sub.1 an NOR gate.

The clock signal CLK, frequency divided signals of the frequency dividers DIV.sub.1 and DIV.sub.2, and outputs of the mode setting circuit MS are supplied to the AND gates A.sub.3 to A.sub.6 and the following relations are satisfied.

Namely, when the outputs SEL.sub.1 and SEL.phi. of the mode setting circuit MS equal H (hereinafter, called MODE3), the clock CLK is outputted as it is as an output T.sub.5 of the OR gate OR.sub.3. When SEL.sub.1 =H and SEL.phi.=L (hereinbelow, called MODE2), the output T.sub.5 becomes the 1/2-frequency divided output of the clock CLK.

On the other hand, when SEL.sub.1 =L and SEL.phi.=H (hereinfter, called MODE1), the output T.sub.5 becomes the 1/4-frequency divided output of the clock CLK. When the SEL.sub.1 =L and SEL.phi.=L (hereinbelow, called MODE.phi.), the output T.sub.5 always becomes an H level.

T.sub.1 denotes the timing pulse to supply the pulse .phi..sub.AB immediately before the vertical transfer. The pulse .phi..sub.AB is supplied when the pulse T.sub.1 is at a high level.

T.sub.3 is the timing pulse for the vertical transfer. When this pulse T.sub.3 is at a high level, the vertical transfer is performed in response to the pulses .phi..sub.PI and .phi..sub.PS.

While the switch SW.sub.1 shown in FIG. 15 is in the OFF state, the period of the pulse .phi..sub.AB is determined in accordance with the modes MODE1 to MODE3 selected by the mode setting circuit and the pulse .phi..sub.AB is supplied at timings as shown in FIG. 12.

The pulses .phi..sub.PI and .phi..sub.PS are generated from the pulse generator SG at timings as shown in FIG. 12.

When the switch SW.sub.1 is once turned on, the mode setting circuit MS enters the MODE.phi. immediately after that, so that the SEL.sub.1 =L and SEL.phi.=L and an output T.sub.6 of the OR gate OR.sub.4 in FIG. 18 becomes a high level and the pulse .phi..sub.AB is set to the potential V.sub.3. On one hand, the analog switch SW.sub.2 is switched to the side of b during this interval, so that the pulse .phi..sub.PI is fixed to the potential +V.sub.2.

As described above, according to this embodiment, the pulse .phi..sub.AB is supplied for a predetermined time immediately before the frame transfer interval and the excessive charges immediately before the transfer are removed, so that the smear or blooming is not caused.

In addition, the pulse .phi..sub.AB is fixed to a constant potential in case of recording the video output from the image sensor by only one field or one frame, so that an electric power consumption can be saved and no noise is mixed.

On the other hand, the potential barrier in the light receiving part is set to be lower than the potential barrier in the storage part for almost of the time intervals; therefore, the readout signal from the storage part is not influenced by the blooming during the readout operation of the signal.

Further, since the overflow drain is provided on the side of the light receiving part opposite to the storage part, the overflow charges during this interval can be soon removed.

Although an example of the frame transfer type CCD of the single-phase driving method has been described in the above, it will be appreciated that the present invention can be also similarly applied to a CCD image sensor of the multi-phase driving method. It is also obvious that the invention can be applied to not only the CCD image sensor but also all image sensors of the types which convert an image signal to a charge signal and store it.

In the embodiment, the .phi..sub.PI =V.sub.2 and .phi..sub.AB =V.sub.3 in the MODE.phi.; however, even if the .phi..sub.PI =V.sub.5 and .phi..sub.AB =V.sub.4, a similar effect will be derived since the potential barrier in the light receiving part is lower than the barrier in the storage part. In addition, in the embodiment, the potential level of the .phi..sub.PI as well as the .phi..sub.AB can be also controlled by the signals SEL.sub.1 and SEL.sub..phi. from the mode setting circuit, so that the number of input pins of the clock driver can be reduced.

According to the fourth embodiment of the invention, the pulses .phi..sub.AB and .phi..sub.PI are set to the constant potentials in case of recording in the still mode, so that the electric power consumption can be saved and no noise is mixed.

Further, at this time, these potentials are set to be lower than the potential in the storage part with regard to the electrons, so that even if the blooming occurs in the light receiving part, it is not mixed to the storage part.