Power Hemt Structure

The present invention relates to field effect transistors and more particularly to modulation-doped high mobility field effect transistors (MODFET), also referred to as high electron mobility transistors (HEMT).

Field effect transistors (FET's) using gallium arsenide (GaAs) are know to be capable of high speed operation. Devices using gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) heterostructures form a two-dimensional electron gas (2 DEG). In such devices the donor impurities are confined away from the active channel in which electrons may flow. This separation of donor impurities from the electron layers causes the device to exhibit extremely high electron mobilities and thereby to be capable of extremely fast operation, for example, in high speed switching.

Generally, HEMT structures utilize a narrow recess configuration for the control gate so as to reduce the effects of series resistance regions not subject to gate control. While such a configuration allows a transistor to be constructed with high RF gain and low noise figure, the source to drain breakdown voltage tends to be low, for example, 4-6 volts, because of field crowding at relatively sharp corners where the trapezoidal-shaped sides of the gate recess or trench in the GaAs meet the bottom. Consequently, the breakdown voltage is primarily determined by the geometrical configuration of the gate metal-2DEG interface rather than the doping level in the AlGaAs layer.

While the breakdown voltage may be increased by introducing a separation between the gate metal and the drain recess or trench edge, this is herein recognized to be generally undesirable if it is not narrow and tightly controlled since it can lead to current limiting and current lagging effects associated with surface depletion and field dependent trapping and detrapping effects in the doped AlGaAs as well as other problems including I-V collapse at low temperatures in the dark. Furthermore, while the gate to drain breakdown voltage may be increased by a parasitic gate to drain voltage drop, this does not result in an increase of RF output power.

In accordance with an aspect of the invention, a modulation doped field effect transistor comprises a first semiconductor layer having a second semiconductor layer formed thereon. An insulating layer which is to be used as an etch mask in fabrication is formed on the second semiconductor layer. A hole for a gate electrode passes through the insulating layer and the second semiconductor layer, and extends into the first semiconductor layer. The wall portions of the hole in the first and second semiconductor layers respectively slope in opposite directions.

In accordance with another aspect of the invention, each of the wall portions slopes away from a central axis of the hole, in the direction towards the interface between the first and second semiconductor layers.

In accordance with yet another aspect of the invention, the second semiconductor layer is undercut at its interface with the insulating layer, so that the hole is smaller in the insulating layer than in the second semiconductor layer.

The invention will next be described in more detail in conjunction with the drawing in which

the sole FIGURE shows an embodiment in accordance with the invention, in cross-section and not to scale.

The FIGURE shows a high electron mobility transistor (HEMT) in accordance with the invention, in which 10 is a GaAs layer, relatively undoped. Adjacent layer 10 is an AlGaAs layer 12, relatively heavily n-doped. This acts as a donor layer and forms a two-dimensional electron gas (2 DEG) in a region of layer 10 adjacent layer 12, which is the active channel. Layer 14 is relatively heavily n-doped GaAs and over this is an insulating layer 16 of, for example, silicon nitride (Si.sub.3 N.sub.4) which can be etched selectively with respect to the underlying semiconductor layers. A gate trench or recess 17 has a hole portion 18 in layer 16. The hole continues as hole portion 20 in layer 14, hole portion 20 being larger adjacent layer 16 than hole portion 18, so that insulating layer 16 overhangs hole portion 20. Proceeding through semiconductor layer 14, hole portion 20 becomes progressively larger until the interface with semiconductor layer 12. Thereafter, proceeding through semiconductor layer 12, hole portion 20 becomes progressively smaller until a bottom 22 is reached in semiconductor layer 12. In other words, the walls of the gate hole 17 in semiconductor layer 14 slope away from the center in the (downward) direction towards the interface between semiconductor layers 12 and 14 whereas those walls slope away from the center in semiconductor layer 12 in the (upward) direction towards the same interface.

Hole 17 contains a metallic gate electrode 24 formed therein. A gate electrode is being deposited in fabrication, shadowing by insulating layer 16 causes gate electrode 24 substantially not to occupy the portions of the hole 17 in the undercut part. The exact profile of the gate metal edge and the hole edge can be varied by changing the extent of the shielding during deposition provided by insulating layer 16 and by changing the thicknesses of layers 12 and 14, either in total thickness and/or the ratio of respective thicknesses.

The configuration of hole 17 is obtainable by using a 011 gate finger orientation on a 100 oriented GaAs substrate, that is, the length horizontally in the plane of the paper in the FIGURE. Since GaAs is etched preferentially, this results in a reentrant recess profile in the 011 direction. However AlGaAs is etched non-preferentially and this results in a cylindrical profile independent of the gate orientation. As a result of layers 12 and 14 being AlGaAs and GaAs respectively, the overall resulting shape, as illustrated in the FIGURE has a relatively flat interface between the gate metal bottom and AlGaAs layer 12, blending into a gentle curve towards the sides. Since the gate metal does not fill hole 17 out to its sides, a sharp-cornered interface between gate metal and the GaAs/AlGaAs interface is prevented and an extended thin, flat AlGaAs region adjacent the gate metal is avoided. Accordingly, high electric fields at the recess edge are thereby prevented and the gate to drain breakdown voltage is increased without introducing a thin, parasitic AlGaAs layer adjacent the gate metal. In measurements made with a structure in accordance with the present invention, the gate to drain breakdown voltage was found to be substantially improved.