Hidden Control Bits in a Control Register

This invention relates generally to control circuitry, and more particularly to a method and circuit for hiding a control function in a control register of a microprocessor or the like.

Often times, a memory mapped register is used to perform a control function. For example, an address register may be used to select one of several LCD display registers. It may also be true that only the least significant bits (e.g. the four LSBs of eight bits) are required to perform the desired function. If an on/off control for the entire LCD display function is required and there is no control register available, it would be awkward and inefficient to create an additional register to perform the simple on/off function.

One approach is to use one unused bit of the address register to perform the control function. For example, a "1" in the selected bit would enable the LCD function while a "0" in the selected bit would disable it. There are conditions, however, wherein it is desirable or necessary that the address register contain either all 1's or all 0's. This could, perhaps, cause the on/off bit to be forced into the wrong state resulting in the unwanted enabling or disabling of the LCD function.

It is an object of the present invention to provide an improved method and circuit for hiding a control function in a control register.

It is a further object of the invention to implement a control function with two unused bits of a control register.

According to a broad aspect of the invention there is provided a method for controlling a function by utilizing an unused portion of a multibit register. First and second unused bits in the register each capable of assuming first and second stable states are first located. The function is enabled by forcing the first bit into the first state and the second bit into the second state. The function is disabled by forcing the first bit into the second state and the second bit into the first state, the function remaining unaltered if the first and second bits are in the same state.

According to a further aspect of the invention there is provided a control circuit comprising a multi-bit register having at least first and second unused bits capable of assuming first and second states a flip-flop having set and reset inputs; first logic circuitry having inputs coupled to the first and second unused bits and having an output coupled to the reset input for resetting the flip-flop when the first bit is in the second state and the second bit is in the first state; and second logic circuitry having inputs coupled to the first and second bits and having an output coupled to said set input for setting the flip-flop when the first bit is in the first state and the second bit is in the second state.

The above and other objects of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an eight-bit register;

FIG. 2 is a state diagram illustrating how the hidden control function operates; and

FIG. 3 is a logic diagram which implements the control function of FIG. 2.

FIG. 1 illustrates eight bits (0-7) of a memory mapped register (for example, an address register) wherein only the four least significant bits (0-3) are required to generate the requisite number of unique addresses. Thus, bits A, B, C, and D (bits 4-7) may be considered unused. It is an object of this invention to utilize two of these unused bits (for example C and D) to perform a control function. The function to be controlled must not be inadvertently enabled or disabled should the entire contents of the register (bits 0-7) assume an all "0" or all "1" condition. With this in mind, the hidden control function should operate as indicated by the state diagram in FIG. 2.

As will be recalled, there are conditions under which the address register will be forced to an all "0" or all "1" condition and it is desired that such a condition have no effect on the controlled function. FIG. 2 is a state diagram illustrating states q.sub.0 and q.sub.1 which may correspond respectively to the enabled and disabled state of the controlled function. If bits six and seven of the register are used to control the function, the state will shift from q.sub.0 to q.sub.1 only when D=1 and C=0. Similarly, the state will shift from q.sub.1 to q.sub.0 when D=0 and C=1. If the current state is q.sub.0, the conditions of D and C corresponding to 01, 00 and 11 will not result in a state change. Similarly, if the current state is q.sub.1, D and C corresponding to 00, 10, and 11 will not result in a state change.

FIG. 3 is a logic diagram which implements the function illustrated in FIG. 2. As can be seen, D is applied to a first input of NAND gate 10 and, after inversion in inverter 12, to a first input of NAND gate 14. Signal C is applied to the second input of NAND gate 14 and, after inversion in inverter 16 to a second input of NAND gate 10. The outputs of NAND gates 10 and 14 are applied respectively to the first inputs of NAND gates 18 and 20. The output of NAND gate 18 (Q) is coupled to the second input of NAND gate 20, and the output of NAND gate 20 (Q) is coupled to a second input of NAND gate 18. A reset signal (RST) is coupled to a third input of NAND gate 18.

Assuming first that Q=0 and Q=1 (corresponding to state q.sub.1 in FIG. 2), a 00 input (i.e. C=0, D=0) will cause a high output at NAND gate 10 and a high output at NAND gate 14. Since both inputs to NAND gate 20 are high, the output of NAND gate 20 (Q) will remain a zero. Since the Q output is fed back to the input of NAND gate 18, Q will remain a one. If we next assume that C=1 and D=1, the situation remains the same since the output of NAND gate 14 remains high. Finally, if C=0 and D=1, the output of NAND gate 14 remains high thus precipitating no change in the outputs of NAND gates 18 and 20. Should, however, C=1 and D=0, the output of NAND gate 14 goes low causing the Q output of NAND gate 20 to go high. This high is applied to one input of NAND gate 18. Since D=0, the output of NAND gate 10 is likewise high and is applied to the second input of NAND gate 18. Assuming for the time being that the reset signal RST is also high, the output Q will go low. This low is applied to a second input of NAND gate 20 thus latching the states of Q and Q corresponding to the state q.sub.o in FIG. 2. It can be readily seen that if C and D should assume the states 00, 01 or 11, there will be no change in the outputs Q and Q. If however, D=1 and C=0, the output of NAND gate 10 will be low and the output of NAND gate 14 high. The low at the output of NAND gate 10 will cause the output of NAND gate 18 (Q) to go high. This high is applied to the second input of NAND gate 20 causing its output (Q) to go low thus switching back to state q.sub.1. Reset signal RST is provided to force Q high when RST goes low.

Thus, there has been accomplished both a method and circuit whereby a function can be controlled using two unused bits of a memory mapped register. The state of the controlled function will not be altered if both of the bits are either 0 or 1. In this manner, the controlled function is not inadvertantly enabled or disabled if the register is forced to all zeros or all ones.

The above description is given by way of example only. Changes in form and details may be made by one skilled in the art without departing from the scope of the invention as defined by the appended claims.