Semiconductor Memory Device With Low-Noise Structure

The present invention relates to a semiconductor memory device, and particularly to a dynamic type semiconductor memory device employing field effect transistors.

Memory capacity of dynamic type semiconductor memories has been increasing remarkably and 256K-bit dynamic memories have become commercially available. Accompanied by such increase in memory capacity, problem of array noise has been becoming serious. As, is well known in the art, dynamic type semiconductor memories employ so-called one-transistor memory cells, each of which is composed of a capacitor and a transfer gate transistor coupled betwen the capacitor and a bit line. Reading-out of information stored in a memory cell is performed by sensing a small amplitude potential which is produced by capacitive-division of a capacitance of the cell capacitor and the bit line capacitance.

The array-noise is usually caused by capacitive coupling among bit lines in memory cell array, and operations of sense amplifiers affect from each other through the capacitive coupling. For example, most of sense amplifiers amplify one of binary logic levels and the remaining small number of sense amplifiers amplify the other of the binary logic levels and the remaining small number of sense amplifiers amplify the other of the binary logic levels, the remaining small number of sense amplifiers are inevitably affected towards one of the binary logic levels by the most of sense amplifiers.

According to the recent tendency of large memory capacity, the bit line capacitance is increased because of increase in number of memory cells coupled to each bit line while the capacitance of each memory cell capacitors has inevitably become small. Accordingly, the small amplitude signal read-out on the bit line from the addressed memory cell has been further becoming small, and on the other hand amount of the array-noise has increased by the increase in memory capacity. As a result, the substantial signal generated on the bit line from the addressed memory cell has become small in view of the array-noise, resulting in difficult detection of stored information.

It is an object of the present invention to provide a semiconductor memory device which has improved noise-resistant characteristics.

The semiconductor memory device according to the present invention is of the type having a plurality of memory cells, each of the memory cells being composed of a capacitor with electrode commonly supplied with a fixed potential and a transfer gate transistor for operatively connecting the other electrode of the capacitor to one of the bit line, and is featured in that the resistance of the first electrodes of the capacitors and/or the resistance of a wiring for commonly supplying the fixed potential to the first electrode of the capacitors is reduced.

The present invention is based on the novel fact that a major cause of the array-noise is potential fluctuations in the first electrodes of the capacitors due to resistive components of the first electrodes of the capacitors. Therefore, the reduction of the resistive components associated with the above first electrodes of the capacitors effectively reduces the potential fluctuations in the first electrodes of the capacitors so that the array-noise can be suppressed effectively.

Accordingly to one aspect of the invention, the first electrodes of the memory cell capacitors are made of a conductive layer including refractory metal such as Mo, W, Ta, Nb and Ti or silicide of such refractory metal.

According to another aspect of the invention, the first electrodes of the memory cell capacitors are commonly made of a consecutive conductive layer such as a polycrystalline silicon, and at least one highly-conductive wiring is formed on the consecutive conductive layer and contacted with a plurality of different portions of the consecutive conductive layer.

FIG. 1 is a block diagram of a dynamic memory device;

FIG. 2 is a circuit diagram of a part of a memory cell array;

FIG. 3 is a sectional view showing a memory cell according to a prior art;

FIG. 4 is an equivalent circuit diagram of the memory cell in view of array-noise;

FIG. 5 is a sectional view showing the memory cell according to a first embodiment of the invention;

FIG. 6 is a plan view of the memory array according to the first embodiment;

FIG. 7 is a diagram showing the relation between the array-noise and the sheet-resistance of the capacitor electrode wiring layer;

FIG. 8 is a sectional view of the memory cell according to a second embodiment of the invention;

FIG. 9 is a plan view of a memory cell array according to a third embodiment of the present invention;

FIG. 10 is a sectional diagram of FIG. 9 along B--B', and

FIG. 11 is a diagram showing the relation between the array-noise and the number of additional wirings employed in the third embodiment.

FIG. 1 shows a typical layout example of a 256K bit dynamic type semiconductor memory. The memory is basically composed of two 128K bit arrays 1 and 2.

In the array 1, 256 word lines WL are intersecting with 512 pairs of bit lines BL, BL. There are 512 sense amplifiers SA which are arrayed in a sense amplifier block 13. Each of the sense amplifiers is connected to each pair of bit lines BL, BL and the word lines WL are adapted to be driven by decoders 11 and 12 in a known way. Memory cells MC are arrayed at the intersections of the word lines WL and the bit lines BL, BL. The array 2 is also structured in the same manner.

FIG. 2 shows one column of memory cell arrangement in the array 1 or 2. A sense amplifier SA 1 is composed of a pair of flip-flop transistors Q.sub.1 and Q.sub.2, and a transistor Q.sub.3 connected between the sources of the transistors Q.sub.1 and Q.sub.2 and a ground potential. A memory cell MC.sub.1 is composed of a memory cell transistor Q.sub.4 and a cell capacitor C.sub.4 connected between the transistor Q.sub.4 and a constant voltage VFix. A dummy cell DMCo is composed of a transistor Q.sub.5, a capacitor C.sub.5 connected between Q.sub.5 and VFix, and a reset transistor Q.sub.6 for short circuiting the capacitor C.sub.5. The capacitance of the capacitor C.sub.5 is selected at a half of the capacitance of the cell capacitor C.sub.4. Prior to a read operation, the bit lines BL1 and BL1 are precharged to a predetermined potential and the transistor Q.sub.6 is conducting to reset the dummy cell DMC.sub.o.

When the word line WL1 is selected, the transistor Q.sub.4 becomes conducting to connect the cell capacitor to the bit line BL1 while the dummy word line WL' is raised in potential to connect the capacitor C.sub.5 of the dummy cell DMC.sub.o to the bit line BL1. Thus, a small potential difference is provided between the bit lines BL1 and BL1. Then, the sense amplifier SA.sub.1 is enabled in response to a high level of .phi..sub.SE so that the small potential differential is amplified. If the cell MC1 stores "1" level, the amplification is achieved by discharging electric charge at the bit line BL1. On the contrary, if the cell MC1 stores "0" level, the amplification is achieved by discharging electric charge at the bit line BL1 through the sense amplifier SA1.

FIG. 3 illustrates the conventional structure of the memory cell MC1.

On a P-type semiconductor substrate 31, an N-type region 32 as a drain of the transistor Q.sub.4, and an N-type region 40 serving as one electrode of the capacitor C.sub.4 are provided. A field oxide layer 33 is provided to define cell region. A first polycrystalline layer 35 is formed on the region 40 via a thin insulating layer 34 thereby to form the cell capacitor C.sub.4 with the region 40. A second polycrystalline silicon 36 serving as the gate of the cell transistor Q.sub.4 is formed and the second polycrystalline silicon 36 overlaps partially with the first polycrystalline silicon 35 and is connected to a word line 39 (WL) of aluminum formed on the substrate 31 via a silicon dioxide layer 38. The region 32 is extending in the direction normal to the word line 39 and forms one of bit lines (BL or BL). As is clear from FIG. 3, one memory cell employs a multi-layer or stacked-layer structure in which many wiring layers are partially overlapped from each other via inter-layer silicon dioxide and therefore, there are many capacitive couplings between the respective wiring layers. Accordingly, a potential of one of the wiring layers is made a relatively large change, then such potential change is inevitably transmitted to other wirings by the capacitive couplings.

FIG. 4 shows a simplified model of the capacitive couplings, in which the corresponding portions to FIG. 3 are designated by the same reference numerals.

In FIG. 4, CWD is a capacitance between the word line 39 (WL) and the bit line region 32; CWS a capacitance between the word line 39 and the first polycrystalline silicon 35; CDS a capacitance between the bit line region 32 and the polycrystalline silicon 35, CSB a capacitance between the polycrystalline silicon 35 and the substrate 31; CDB a capacitance between the region 32 and the substrate 31; and CWD a capacitance between the word line 39 and the substrate 31. A resistance R is a wiring resistance of the polycrystalline silicon 35.

When a read operation is performed, half of the bitlines are discharged by the sense amplifiers. Namely, potentials of half of the bitlines inevitably drop rapidly. The change in potential at the bit line 32 is transmitted to the word line 39 and the silicon wiring 35 via capacitances CWD, CWS and CDS. Thus, potential changes in many wirings act as the array-noise and the wirings are inevitably affected by each other. Thus, the potential change in one bit line is transmitted to other bit lines through the capacitive couplings.

Referring to FIGS. 5 and 6, a first embodiment of the invention will be described. In the drawings, the portions corresponding to those in FIG. 3 are indicated by the same reference numerals.

This embodiment is achieved by forming the capacitor electrode 35 in FIG. 3 with a refractory metal layer 35.sup.1 -2 and a polycrystalline silicon 35'-1. At the surface boundary of the layer 35'-2 and the polycrystalline silicon 35'-1, a silicide of the refractory metal is present. As the refractory metal, molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb) and titanium (Ti) can be used. Typical thickness of the refractory metal 35'-2 is about 3000 .ANG. and the thickness of the silicon layer 35'-1 is about 3000 .ANG..

FIG. 6 shows a plan view of the capacitor electrodes 35'-1,2. As shown in FIG. 6, the electrodes 35'-1,2 are formed over the respective diffusion regions 40' as the other electrodes of the capacitors as a consecutive single wiring layer with a plurality openings in order to expose the channel regions of the respective memory cell transistors.

According to the present embodiment, in place of high-resistivity polycrystalline silicon 35, the refractory metal - polycrystalline silicon wiring (35'-1,35'-2) is employed. Therefore, the resistance component R in FIG. 4 can be effectively reduced so that the potential fluctuation at the capacitor electrode (35) can be avoided. Thus, the effect of capacitances CWS, CDS and CSB can be suppressed to reduce the array-noise.

FIG. 7 shows the co-relation between the sheet resistance of the electrode 35'-1,2 in FIGS. 5 and 6 and the amount of the array-noise. As is clear from FIG. 7, the array-noise is remarkably reduced by employing the electrode 35' of the sheet resistance of 10.OMEGA./.quadrature. or less. In the above embodiment, 0.2.OMEGA./.quadrature. is obtained for Mo and 1.OMEGA./.quadrature. for the silicide of Mo. Therefore, the array-noise is significantly reduced.

Referring to FIG. 8, a second embodiment of the invention will be described.

This embodiment is realized by replacing the electrode 35 of polycrystalline silicon in FIG. 3 by the electrode 35" of a single molybdenum layer. The thickness of the molybdenum layer 35" is 4000 .ANG. while the gate polycrystalline silicon is of 6000 .ANG.. As compared to the conventional layer 35 of polycrystalline silicon, the sheet resistance of the molybdenum layer 35" is far smaller and therefore, the array-noise can be also effectively suppressed.

With reference to FIGS. 9 and 10, a third embodiment of the present invention will be described. In this drawing, the portions correspondinng to those in the previous drawings are indicated by the same reference numerals.

In this figure, the respective capacitor electrodes formed over the respective diffusion regions 40' as other electrodes of the capacitors are made of single consecutive conductive layer 35" which may be polycrystalline silicon, refractory metal such as Mo, W, Ti, Ta or silicide of the refractory metal and silicon. Here, on the layer 35", a highly-conductive wiring 73 is formed via an insulating layer 75 such as silicon dioxide. The highly-conductive wiring is formed in a strip pattern and contacted with the layer 35" at a plurality of contact points 74. The wiring 73 shortcircuits many portions of the layer 35" thereby to reduce effective resistance of the layer 35". The wiring 73 itself is preferably connected to the potential source V.sub.Fix. As the material of the wiring 73, aluminum is advantageously utilized.

FIG. 10 shows the relation between the amount of the array-noise and the number of the wiring 73 over the whole memory cell array. It would be clearly understood that the larger the number of the wirings 73 is, the less the array noise is. In particular, it is clear from FIG. 10 that two or more wirings 73 reduce the array noise effectively.

As described above, the present invention provides dynamic memory devices in which array-noise is suppressed with ease. Although the present invention has been described by way of the embodiments, the present invention is not limited to those embodiments but applicable to other memory devices.