Method for Making Electrically Programmable Memory Device by Doping the Floating Gate by Implant

The present invention relates generally to a method for making an electrically programmable memory device. More particularly, the present invention relates to the manufacture of ultra high coupling interpoly dielectrics suitable for programming Electrically Programmable Read-Only Memory (hereinafter "EPROM") and Electrically Erasable Programmable Read-Only Memory (hereinafter "EEPROM").

EPROM or EEPROM and methods for making the same are well known in the art. In general, an EPROM or an EEPROM is characterized by a "floating gate" and a electrical connection termed "control gate", both of which are fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline silicon conductive. A typical doping material is phosphorus. The floating gate and the control gate are separated by a layer of insulating material, typically silicon dioxide (SiO.sub.2). The principle upon which the EPROM or EEPROM device operates is that charges are stored on the "floating gate" in a capacitive manner. Thus, the dielectric of the layer of silicon dioxide between the floating gate and the control gate is important.

In the prior art (see for example, U.S. Pat. No. 4,203,158 and W. S. Johnson et al. ISCCC Digest of Technical Papers, pp. 152-153 (February 1980)), the floating gate is formed by reacting SiH.sub.4 in a low pressure chemical vapor deposition chamber and then doped with POCl.sub.3. A layer of silicon dioxide is then deposited, or thermally grown, on the doped polycrystalline layer of silicon. The layer of silicon dioxide is typically approximately 750 Angstroms. Generally, a high oxidation temperature (greater than 1050.degree. C.) and heavier phosphorus doping are required to achieve better interpoly quality on breakdown capability. However, oxidation at high temperature on heavily-doped polysilicon involves several drawbacks, such as: (1) outgassing during interpoly oxidation which causes autodoping on wafer; and (2) oxidation enhanced diffusion of phosphorus from the floating gate to the tunnel oxide, which, forms a trapping center in the oxide. The phosphorus induced trap collapses the threshold window of EEPROM cell at 10.sup.4 cycles. (See: R. B. Marcus et al., J. Electrochem. Soc., p. 1282, June, 1982; K. Saraswat et al., Computer-Aided Design of Integrated Circuit Fabrication Process for VLSI Device, p. 244-290, July, 1981.) Finally, the second layer of doped polycrystalline silicon is then formed on top of the insulating layer of SiO.sub.2.

Because the insulating layer of silicon dioxide is on the order of 750 Angstroms, the typical write or erase voltage, i.e., the voltage which is needed to place charges on or to remove charges off the floating gate has been high, i.e., in excess of 20 volts, which places the shrinkage limits for gate oxide thickness, junction depth and die size.

Silicon nitride (Si.sub.3 N.sub.4) has also been used as an insulating layer of dual dielectric (thermal oxide with silicon nitride on it) between the floating gate and the control gate connection. Silicon nitride has the property that it is more dense than silicon dioxide and, therefore, affords higher capacitive coupling between the floating gate and the control gate. A typical dual dielectric between the floating gate and the control gate is composed of 500 Angstroms oxide and 400 Angstroms nitride. However, even with the use of silicon nitride as the insulating layer, the write and erase voltage is still relatively high, in excess of 20 volts. This is due to the problem of asperity or roughness in the surface of the floating gate. Asperity in the floating gate causes points of electrical field enhancement. Thus, a large amount of insulating material must be interposed between the floating gate and the control gate. This, however, in turn, requires that a large voltage be used. Currently in VLSI technology, there is a preference for small die size in high circuit density packages which requires a relatively high interpoly dielectric breakdown capability and interpoly capacitance.

In the present invention, a method of making an electrically programmable memory device is disclosed in which the floating gate is first formed by depositing a layer of polycrystalline silicon. Subsequently, a layer of silicon dioxide of approximately 200 Angstroms is thermally formed over the polycrystalline silicon. The layer of polycrystalline silicon is then doped by ion implantation technique in which ions are implanted through the insulating layer of silicon dioxide into the layer of polycrystalline silicon to dope it to form the floating gate. A LPCVD silicon nitride (approximately 200 Angstroms) is then deposited on the layer of silicon dioxide. Finally, a pyrogenic oxidation (H.sub.2 /O.sub.2) is performed to reduce the nitride pinhole and nitride/oxide interface state.

FIG. 1 is an enlarged cross-sectional view of an EPROM device of the prior art and an EPROM device manufactured by a method of the present invention.

FIG. 2 is an enlarged cross-sectional view of an EEPROM device of the prior art and an EEPROM device manufactured by a method of the present invention.

FIG. 3 is a cross-sectional view, greatly enlarged, of a section of the floating gate of the EPROM or EEPROM device of the prior art and superimposed thereon a section of the floating gate of EPROM or EEPROM device manufactured by a method of the present invention.

FIG. 4 is an enlarged cross-sectional view of another EPROM device manufactured by a method of the present invention.

FIG. 5 is an enlarged cross-sectional view of another EEPROM device manufactured by a method of the present invention.

FIG. 6 is a graph showing current-voltage characteristics of a device of the prior art and a device manufactured by a method of the present invention.

Referring to FIG. 1, there is shown an EPROM 10 of the prior art. The EPROM 10 comprises a substrate 12, which is typically a single crystalline silicon of the P type having a source 14 and a drain 16 fabricated therein. A first layer 18 of insulating material, typically SiO.sub.2, is grown on the silicon substrate 12. The first layer 18 of SiO.sub.2 is thermally grown at approximately 1,000.degree. C., using HCl and O.sub.2. On the first layer 18 of SiO.sub.2 is deposited the first layer 20 of polycrystalline silicon. The first layer 20 of polycrystalline 20 is deposited by low pressure chemical vapor deposition techniques. In a reaction chamber, SiH.sub.4 is introduced and is reacted at approximately between 620.degree.-670.degree. C., depositing the layer 20 of polycrystalline silicon. The first layer 20 of polycrystalline silicon is then doped by phosphorus, rendering it conductive to form the floating gate. Phosphorus is introduced into the reaction chamber in the form of POCl.sub.3 at 950.degree. C. A second layer 22 of insulating material, i.e., SiO.sub.2, is thermally grown on the floating gate 20. The second layer 22 of SiO.sub.2 is typically on the order of 750 to 1000 Angstroms. A second layer 24 of polycrystalline is deposited on the second layer 22 of SiO.sub.2. The second layer 24 of polycrystalline silicon is doped to form the connection for the control gate of the EPROM 10. A third layer 26 of insulating material, SiO.sub.2, is thermally grown on the second layer 24.

Referring to FIG. 2, there is shown an EEPROM 110 of the prior art. The EEPROM 110 of the prior art is identical to the EPROM 10 of the prior art, shown in FIG. 1, except for the tunnel oxide 15 region between the drain 16 and the floating gate 20. The tunnel oxide region is typically approximately 100 Angstroms thick. This narrow, thin tunnel oxide region 15 permits electrons to tunnel to or from the drain 16 during the erase or write cycle. The fabrication of the first layer 118, second layer 22 and third layer 26 of SiO.sub.2 and the formation of the floating gate 20 and of the control gate 24 is similar to that described for the EPROM 10 of FIG. 1. The shape of the floating gate 20 and the control gate 24 are formed by well-known prior art methods.

In the method of the present invention, the first layer 18 of SiO.sub.2 is thermally grown on the single crystalline substrate 12 in the same manner as that for the EPROM 10 or the EEPROM 110 of the prior art. The floating gate 20, however, is formed by depositing a layer of polycrystalline silicon on the first layer 18 of SiO.sub.2. The layer 20 of polycrystalline silicon is deposited by low pressure chemical vapor deposition technique in which SiH.sub.4 is introduced and is reacted at approximately between 620.degree.-670.degree. C. The second layer 22 of SiO.sub.2 is then thermally grown on the first layer 20 of undoped polycrystalline silicon. The second layer 22 of SiO.sub.2 is approximately 250 Angstroms thick. Phosphorus ions are then implanted in the first layer 20 of polycrystalline silicon through the second layer 22 of SiO.sub.2. Typically, the phosphorus ions are accelerated at 70-120 KEV to impinge the second layer 22 of SiO.sub.2, to pass therethrough and to be deposited in the first layer 20 of polycrystalline silicon. The first layer 20 of polycrystalline silicon, doped with the phosphorus, becomes the floating gate 20. SiO.sub.2 can then be further deposited on top of the second layer 22 of SiO.sub.2 to increase the total thickness to approximately 400-500 Angstroms. The second layer 24 of polycrystalline silicon is then deposited on the second layer 22 of silicon dioxide in the same manner as the prior art. The second layer 24 of polycrystalline can then be doped to be conductive to form the control gate.

Referring to FIG. 3, there is shown a section of the floating gate 20 of the EPROM 10 or EEPROM 110 of the prior art (shown in solid line) and a section of the floating gate 120 of the EPROM or EEPROM made by the method of the present invention (shown in dotted lines). This is a greatly enlarged view, as typically the dimension of the floating gate is less than one micron in size.

As can be seen in FIG. 3, the floating gate 20 of the prior art shows a number of bumps (designated as A, B, C, etc.). The asperity in the floating gate 20 is attributable to the chemical phosphorus doping of the polycrystalline silicon. These bumps in the floating gate 20 form electrical field enhancement points. To prevent undesired discharge between the floating gate 20 and the control gate, the insulating layer therebetween or the second layer 22 of silicon dioxide must be relatively large (on the order of 750 Angstroms). Since ##EQU1## where E is the dielectric constant of the material, A is the area between the two gates, and T is the thickness therebetween, for a large T, the value of C is reduced. Furthermore, since .DELTA.Q=C.DELTA.V for a reduced value of C, a large value of voltage V must be used to place the charge Q on or to remove it from the floating gate 20. Subsequently, the voltage to write or to erase must be large.

In contrast, with the floating gate 120 formed by the method of the present invention, the surface is relatively smooth. The doping material is not chemically introduced and does not deform the surface of the floating gate 120. Because the surface of the floating gate 120 is relatively smooth, the second layer 22 of silicon dioxide can be on the order of 400-500 Angstroms. This increases the capacitive coupling. Thus, the operating voltage for the write and erase cycles can be much lower.

The charging and discharging of the floating gate is accomplished by Fowler-Nordheim tunneling of electrons across the tunnel oxide. The tunnel current is ##EQU2## where E is the electric field across the tunnel oxide, .alpha. and .beta. are constants, electrical field is ##EQU3## where V is the voltage drop across the tunnel oxide and t is the tunnel oxide thickness. V can be calculated from the capacitive equivalent voltage divider circuit.

If we define the coupling ratio as ##EQU4## during the charging state, the coupling ratio is ##EQU5## where C total is the sum of interpoly capacitance (Cpp), gate oxide capacitance and tunnel oxide capacitance. Higher interpoly capacitance results in higher coupling ratio, which, results either in the reduction of charging state applied programming voltage or in shorter charging state programming time.

Referring to FIG. 4, there is shown a cross-sectional view of another EPROM 210 manufactured by a method of the present invention. The EPROM 210 comprises a single crystalline silicon substrate 212, having a source 214 and a drain 216. A first layer 218 of SiO.sub.2 is on the body 212. A first layer of undoped polycrystalline silicon 220 is on the first layer 218 of silicon dioxide. The method involves depositing first layer 220 by low pressure chemical vapor deposition technique of SiH.sub.4 at 620.degree. C. The layer 220 is approximately between 3000-4500 Angstroms thick. A second layer 222 of silicon dioxide is on the first layer 220 of polycrystalline silicon. The second layer 222 is substantially between 200-250 Angstroms. The second layer 222 is formed by thermally oxidizing the first layer 220 in dry O.sub.2 at approximately 1000.degree. C. The first layer 220 of polycrystalline silicon is doped with phosphorus that has been ion implanted through the second layer of 222 of silicon dioxide. P.sup.31 is implanted at 1-5.times.10.sup.5 /cm.sup.2 at 70-120 KEV. Thereafter, the second layer 222 of silicon dioxide is bathed in sulfuric acid at 150.degree. C. for about 10 minutes. Then, the second layer 222 is dipped in a dilute HF acid for about 5 seconds to remove contamination due to the ion implantation. The HF acid removes approximately 25 Angstroms of SiO.sub.2. The dilute HF acid comprises ten parts of distilled water to one part of HF acid. The second layer 222 is then rinsed in distilled water and dried. A third layer 224 of insulating material is deposited on the second layer 222 of silicon dioxide. The third layer 224 comprises silicon nitride (Si.sub.3 N.sub.4) and is deposited by low pressure chemical vapor deposition technique. NH.sub.3 and SiH.sub.2 Cl.sub.2 are reacted at approximately 770.degree. C. The third layer 224 is approximately 250 Angstroms. A pyrogenic oxidation (H.sub.2 /O.sub.2) cycle is then performed to reduce the nitride pinhole and nitride/oxide interface state. The pyrogenic oxidation step is accomplished by reacting H.sub.2 and O.sub.2 at 900.degree. C. for about 2 hours. This automatically produces the third layer 226 of SiO.sub.2 which is between approximately 30-50 Angstroms. Finally, the second layer 228 of polycrystalline silicon is then deposited on the third layer 226 of SiO.sub.2. The second layer 228 of polycrystalline silicon is then doped to form the control gate.

Referring to FIG. 5, there is shown another EEPROM 310 manufactured by a method of the present invention. The EEPROM 310 of FIG. 5 is identical to the EPROM 210 shown in FIG. 4, except with the addition of a tunnel oxide region 315. In all other respects, the first, second, and third layers of insulating material (comprising the two layer of SiO.sub.2 and one layer of Si.sub.3 N.sub.4) and the two layers of polycrystalline silicon are identical to the similar structures for the EPROM 210 and are made in the same manner. The first layer of SiO.sub.2 is approximately 750 Angstroms thick over the thick gate region and is approximately 100 Angstroms thick in the tunnel oxide region. the formation of the shape of the two layers of polycrystalline silicon and the second layer of Si.sub.3 N.sub.4 is based upon well-known prior art methods.

With the EPROM 210 or the EEPROM 310, there is greater capacitive coupling betwen the control gate and the floating gate due to the silicon nitride deposited therebetween. Since silicon nitride has a higher dielectric constant, the capacitance is increased. This means that a lower operating voltage, on the order of 12 volts, can be used to write or to erase charges from the floating gate 220.