Solid State Photosensitive Devices

The present invention relates to solid state photosensitive devices used both in the visible and infrared ranges.

Thus, the present invention more particularly relates to an improvement to solid state photosensitive devices decribed in French Patent Application No. 83 09827 in the name of THOMSON-CSF, namely to solid state photosensitive devices of the type comprising at least one detector connected to a charge integration zone, which is itself connected to a reading stage performing the charge--voltage conversion, constituted by voltage reading means, each of which is connected to an integration zone via a diode making it possible to read the potential corresponding to the charge quantity in the integration zone, by at least one addressing means for sequentially addressing the reading means and by resetting means for the previously read integration zone. However, the present invention can also apply to the reading stage of solid state photosensitive devices mainly constituted by detectors, each of which is connected to a charge integration zone and by a charge transfer shift register receiving in parallel the charges integrated in each charge integration zone and supplying them in series to a reading stage, performing the charge--voltage conversion.

In both of the aforementioned photosensitive device types, the charge quantity Q to be read by the reading stage or charge--voltage conversion stage is firstly stored in a capacitor C, where it gives a voltage variation .DELTA.V=(Q/C). However, these devices are generally limited by a maximum value of the voltage variations .DELTA.V.sub.max, which can be permitted by the circuit. However, the charge quantity which has to be integrated is sometimes difficult to forecast, either because the scene observed is constituted by a variable mean lighting, or the detectors to be associated with the reading device are of different types, particularly in the case of hybrid circuits especially used in the infrared. Therefore the capacitor must be dimensioned in accordance with the maximum charge which it may be necessary to store. Therefore C=(Q.sub.max /.DELTA.V.sub.max). Thus, the capacitor is overdimensioned in most cases of use of solid state photosensitive devices, where the charge Q is generally below Q.sub.max. Thus, for the photosensitive device, this leads to a relatively low photon--output voltage variation conversion factor, so that the output gain is also relatively low. The present invention consequently aims at obviating the disadvantage by making it possible to select the value of capacitor C as a function of the lighting conditions and the nature of the detectors.

The present invention therefore relates to a solid state photosensitive device of the type comprising at least one photosensitive detector, each detector being connected to a charge integration cell, which is itself connected under control of a multiplexer to a charge--voltage conversion stage preceded by a first storage means connected to a resetting means, wherein it also comprises at least one supplementary charge storage means adjacent to the first storage means, said supplementary storage means being controlled by variable bias voltages making it possible to modify the capacitance of the storage means as desired to vary the quantity of integrated that can be stored.

The invention is described in greater detail hereinafter relative to non-limitative embodiments and with reference to the attached drawings, wherein show:

FIG. 1 a plan view of a strip-type photosensitive device used more particularly in the infrared, whose charge integration cells have been modified in accordance with the first embodiment of the invention.

FIG. 2 a diagrammatic cross-sectional view of the device of FIG. 1 and the corresponding surface potentials in the substrate into which said device is integrated.

FIGS. 3a to 3d respectively, a diagrammatic cross-sectional view of another embodiment of the detection and integration part of a solid state photosensitive device according to the invention and the evolution of the corresponding surface potentials in the substrate as a function of the bias voltages applied to the storage means.

FIG. 4 a graph giving the evolution of the voltage as a function of the charges integrated by the photosensitive device of FIG. 3.

FIGS. 5a to 5e respectively, a diagrammatic sectional view of another embodiment of the present invention and the evolution of the corresponding surface potentials in the substrate as a function of the voltages applied to the various storage means.

FIG. 6 a graph giving the evolution of the voltage as a function of the integrated charges in the case of the device of FIG. 5.

FIGS. 7a to 7c plan view of the various modes for installing supplementary storage means according to the invention.

FIGS. 8a and 8b respectively a diagrammatic sectional view of an embodiment of the present invention in the case where the multiplexer is a shift register and the evolution of the corresponding surface potentials in the substrate as a function of the bias voltage applied.

In the various drawings, the same references designate the same elements, but for reasons of clarity, the dimensions and proportions thereof have not been respected.

FIG. 1 shows a photosensitive device more particularly used in the infrared range. In per se known manner, the photosensitive device is constituted by charge integration and photon detection cells 1 and a reading stage 2, which gives an electric image analysis signal at the output. For example, FIG. 1 shows a device having four cells. However, it is obvious that the device according to the invention can have a larger number of cells. Moreover, FIG. 1 relates to a strip-type photosensitive device, but the invention can also apply to a matrix-type device, such as that described in French Patent Application No. 83 09827 in the same of the Applicant.

In the infrared range and as shown in FIG. 1, each cell 1 has a photosensitive detector 3 integrated on to a semiconductor substrate 4 differing from substrate 5 into which are integrated the other elements of the photosensitive device and an integration zone formed on substrate 5. Substrate 4 is preferably made from mercury and cadmium telluride, lead and tin telluride or indium antimonide. In the same way, the substrate 5 is preferably made from P type silicon, but it could also be made from N type silicon in the case of common cathode detection diodes, gallium arsenide or any other equivalent semiconductor material.

For example and as shown in FIGS. 1 and 2, photosensitive detector 3 used in the present invention is a photodiode. However, it is obvious to the Expert that the invention applies to whatever type of detector is used.

Thus, as shown in FIGS. 1 and 2, anode A of photodiode 3 receives a bias voltage V.sub.SD. Cathode K is connected by a connection 7 to the charge integration zone making it possible to integrate into substrate 5 the charges produced in photodiode 3 by the radiation to be detected and symbolized by the wavy arrows in FIG. 2.

Moreover, each charge integration zone on the semiconductor substrate 5 which is biased at a voltage V.sub.SM, comprises a diode D constituted by a N type zone formed in the P type silicon semiconductor substrate 5. This zone is designated by the reference N.sub.1.sup.+ in FIG. 2. Each diode is connected by a connection 7 to cathode K of the corresponding photodiode. Furthermore, according to the invention, an electrode or gate G.sub.C connected to the bias voltage V.sub.GC separates each diode D from a first charge storage capacitor constituted by a gate G.sub.ST2, an insulating layer and a substrate. This first charge storage capacitor is followed by a second charge storage capacitor also formed by a gate G.sub.ST1, an insulating layer and a substrate. The storage capacitor symbolized by gates G.sub.ST2 and G.sub.ST1 are biased, in the manner to be described hereinafter, by two different bias voltages V.sub.GST2 and V.sub.GST1.

In the same way, and as shown in FIGS. 1 and 2, the reading stage 2 comprises four voltage reading means or charge--voltage conversion stages constituted by MOS transistors M.sub.I1, which are connected in follower. The gate G.sub.1 of each MOS transistor M.sub.I1 is connected to a reading diode D' adjacent to the storage capacitor G.sub.ST1 of each charge integration and detection cell 1. Diode D' is connected by a N type diffusion designated by reference N.sub.2.sup.+ in FIG. 2. The drain of the MOS transistor M.sub.I1 formed by the N type diffusion designated N.sub.3.sup.+ in FIG. 2 is connected to a bias voltage V.sub.DD. Moreover, the source of the MOS transistors M.sub.I1 is connected via MOS transistors M.sub.I2 acting as switches, to a charge transistor M.sub.C. The latter is constituted by a depletion mode MOS transistor, whose gate G.sub.3 is connected to the source formed by the N type diffusion designated N.sub.6.sup.+ in FIG. 2, said source being biased by a d.c. voltage V.sub.SS. Furthermore, each gate G.sub.2 of the MOS switching transistors M.sub.I2 is connected to one of the outputs of a logic shift register R with a series input and parallel outputs. Shift register R makes it possible to address and make conductive one of the MOS transistors M.sub.I2 as a consequence of performing the multiplexing of the different sequential stages.

The reading stage 2 also comprises resetting means, which are formed by MOS transistors M.sub.I3, whose gate G.sub.4 is connected to the output of the logic shift register R corresponding to the next sequential stage. The induced source of the MOS transistors M.sub.I3 is constituted by the corresponding storage capacitor G.sub.ST1 and the drain formed by a N type diffusion designated N.sub.Z.sup.+ is connected to a d.c. voltage V.sub.RAZ. In the represented embodiment, use is made of the same logic shift register R for controlling the switching MOS transistors M.sub.I2 and the resetting MOS transistors M.sub.I3, which requires one more stage than the number of cells or the use of a looped shift register.

A description will now be given of the operation of the aforementioned device with particular reference to the lower part of FIG. 2. The latter shows the surface potential in substrate 5 during the reading of a stage, when a low value charge Q has been stored beneath the storage gate G.sub.ST1, the storage gate G.sub.ST2 not being used.

Thus, the left-hand part shows the potential beneath the integration zone of a cell 1, which is realized in per se known manner by diode D, gate G.sub.C and the two storage capacitors G.sub.ST1 and G.sub.ST2. This zone forms an MOS transistor, whose diode D is the source and whose storage capacitor G.sub.ST1 in the represented embodiment, namely in the case of weak illumination, is the induced drain. Thus, in this case, the bias voltage V.sub.GST2 is brought to a low level and gate G.sub.ST2 acts as a passage gate for the electrons.

Thus, the input MOS transistor is polarized under saturation conditions, because the voltage V.sub.GST1 applied to gate G.sub.ST1 exceeds voltages V.sub.GC and V.sub.GST2 applied to gates GC and G.sub.ST2. The level of the charges on diode D is aligned with the potential close to the constant potential beneath gate G.sub.C. The anode A of the photodiode is biased by the d.c. voltage V.sub.SD which is e.g. chosen as being equal to zero volt.

The charges produced in the detector by the electromagnetic radiation are stored in the capacitor produced beneath the storage gate G.sub.ST1 and polarized by V.sub.GST1, as is symbolically shown in FIG. 2, where the hached areas indicate the presence of minority carriers with respect to substrate 5.

The charges produced in the detector are firstly stored beneath the storage grid G.sub.ST1. However, according to the present invention, if the charge to be stored exceeds the storage capacitance G.sub.ST1, the bias voltage V.sub.GST2 is when V.sub.GST2 is switched to high level to be equal to V.sub.GST1 switched to high level, so that e.g. V.sub.GST2 to equal to V.sub.GST1, which then makes it possible to store the charges under G.sub.ST2 instead of solely under G.sub.ST1, as is shown by the broken line in FIG. 2.

With regards to the reading of the charges integrated in the integration zone, this is carried out in per se known manner when the corresponding output i of the shift register R is at logic level 1, so that the gate of MOS transistor M.sub.I2 receives a high voltage so as to make said transistor conductive, all the gates of the other MOS transistors acting as a switch and receiving a logic level 0 so as to block the transistors. In this case, the MOS transistors M.sub.I2 behaves in the manner of a resistor, the MOS transistors M.sub.C, namely the load, being connected to the follower transistor M.sub.I1, so that a conventional follower stage is obtained, the bias voltage V.sub.DD being made much higher than the bias voltage V.sub.SS, as shown in FIG. 2.

The diffusion N.sub.2.sup.+ to the right of the storage gate G.sub.ST1 and connected to gate G.sub.1 of MOS transistor M.sub.11 makes it possible to obtain at the gate a potential representing the potential beneath the storage gate G.sub.ST1 in the represented embodiment.

In addition, the potential at diffusion N.sub.5.sup.+ is aligned with the potential at diffusion N.sub.4.sup.+, because transistor M.sub.I2 is equivalent to a resistor. However, the potential at diffusion N.sub.4.sup.+ is a function of the potential beneath gate G.sub.1, because in a sequential stage the potential difference .DELTA..phi. is a constant. Thus, at diffusion N.sub.5.sup.+ a voltage is obtained, which is representative of the voltage of the storage gate G.sub.ST1. This voltage is supplied across an amplifier A to the output terminal S of the photosensitive device. After reading the information on input I, the logic level 1 of shift register R is shifted by one stage under the action of clock H. This is followed by the reading of input i+1.

The logic level 1 is then applied to gate G.sub.4 of the resetting MOS transistor M.sub.I3, which is made conductive. The charges beneath the storage gate G.sub.S+1 are then discharged from the voltage source or supply V.sub.St1 are then discharged from the voltage source or supply V.sub.RAZ, which can be chosen equal to the voltage V.sub.DD. Thus, the value of the storage capacitance of the input i during the reading of input i+1 is reinitialized. Thus, during the resetting of the storage capacitance, the charges supplied by the photodiode are directly removed to the voltage source V.sub.RAZ and are consequently not used.

Thus, according to the invention, during the integration of charges, use is made of the capacitance produced beneath gate G.sub.ST1, when the charge quantity to be integrated is small, or if said quantity is large the voltage V.sub.GST2 is switched to a high level and the charges are then stored both beneath gate G.sub.ST1 and beneath gate G.sub.ST2. In order to be able to subsequently read the charges and reset the integration cell 1, it is necessary, according to the invention, for the first capacitor G.sub.ST1 to be adjacent to the reading diode D' and to the gate G.sub.4 of the resetting MOS transistor M.sub.I3 as shown in FIGS. 1 and 2. Voltage V.sub.GST2 can be identical to or lower than voltage V.sub.GST1.

FIG. 3a shows another embodiment of the integraton cell of a solid state photosensitive device, whose other parts are identical to the photosensitive devices of FIGS. 1 and 2.

In the embodiment of FIG. 3a, a single storage gate V.sub.GST2 is provided at the integration cell, as shown therein, gate G.sub.ST is adjacent to the reading diode D' formed by the N type diffusion designated N.sub.2.sup.+, which is itself adjacent to the gate G.sub.4 followed by the diffusion N.sub.7.sup.+, the assembly representing the resetting transistor M.sub.I3.

With this configuration, the different storage means for the charges supplied by the photodiodes 3 are constituted by the diode D' connected to the gate G.sub.1 of MOS transistor M.sub.I3 and by the storage gate G.sub.ST biased by the voltage V.sub.GST, which can be raised to a high or low level, as a function of the charge quantity to be integrated. Thus, diode D' can be used as a storage capacitor because, through being adjacent to gate G.sub.4, the electrons stored on diode D' and on gate G.sub.1 can be discharged via gate G.sub.4 to the resetting voltage V.sub.RAZ, without passing beneath the storage gate G.sub.ST2.

With reference to FIGS. 3b to 3d, the different operating possibilities of the embodiment of FIG. 3a will show be shown.

When the charge Q to be stored is high, the bias voltage V.sub.GST is at a high level higher than the resetting voltage V.sub.RAZ, which forms the precharging level shown in FIG. 3b. In this case, the operation is identical to that described with reference to FIGS. 1 and 2, and the electrons supplied by photodiodes 3 are stored both beneath gate G.sub.ST2, in diode D' and on gate G.sub.1. C.sub.ST is the MOS capacitance beneath G.sub.ST and C.sub.O is the sum of the capacitance of diode D' and on gate C.sub.1, so that the total storage capacity C.sub.STT is in this case C.sub.STT =C.sub.ST +C.sub.O.

When the charge Q to be stored is particularly small, the bias voltage V.sub.GST is then reduced to a value close to V.sub.GC, in such a way that, in the absence of any charge, the potential beneath G.sub.ST is close but very slightly above that beneath G.sub.C, as shown in FIG. 3c. In this case, the electrons supplied by the photodiodes 3 pass beneath the gate G.sub.ST and are stored in diode D' and on gate G.sub.1. In this case, the total storage capacity C.sub.STT is C.sub.STT =C.sub.O.

As shown in FIG. 3d, it is possible to envisage an intermediate case, in which the bias voltage V.sub.GST is brought to an intermediate level between the resetting voltage V.sub.RAZ and the bias voltage of gate V.sub.GC. In this case, the electrons supplied by photodiodes 3 are first stored beneath diode D' and gate G.sub.1, and then beneath the storage gate G.sub.ST.

FIG. 4 shows the variation of the output voltage of the system as a function of the integrated charge Q. Line 1b corresponding to the case of FIG. 3b has a slope proportional to ##EQU1## and line 1c corresponding to the case of FIG. 3c has a slope proportional to (1/C.sub.O). Moreover, curve 1d corresponds to the case of FIG. 3d, in which the bias voltage G.sub.ST is an intermediate voltage between the two preceding values. When the charge Q to be stored is small, it is only stored beneath C.sub.O and the slope of curve 1d is in the case proportional to (1/C.sub.O), but when charge Q is larger it is stored in parallel on C.sub.O and C.sub.ST and the slope of curve 1d is in this case proportional to ##EQU2## On examining the different curves of FIG. 4, it can be seen that in the case where the charge to be integrated is small, it is preferable to operate with a smaller storage capacity C.sub.O, so as to obtain larger voltage variations at the output, namely a higher output gain.

A description will now be given with reference to FIGS. 5a to 5e of a third embodiment of the integration cell of a photosensitive device of the type according to FIGS. 1 and 2. In this case, gate G.sub.ST has been replaced by two gates G.sub.ST1 and G.sub.ST2 forming MOS capacitors C.sub.ST1 and C.sub.ST2 biased by two different bias voltages V.sub.GST1 and V.sub.GST2.

A description will now be given of the various operating possibilities for this integration cell with reference to FIGS. 5b to 5e.

In the case of a large charge Q to be integrated, the bias voltages V.sub.GST2 and V.sub.GST1 are both brought to an identical high level exceeding the resetting voltage V.sub.RAZ, as shown in FIG. 5b. In this case, the total storage capacity C.sub.TT is equal to:

in which C.sub.O corresponds to the capacitance of diode D' and of gate G.sub.1, C.sub.ST1 to the capacitance beneath gate G.sub.ST1 and C.sub.ST2 to the capacitance beneath gate G.sub.ST2.

In the case where the charge Q is smaller, the bias voltage V.sub.GST2 can be brought to a low level slightly higher than the bias voltage level of gate G.sub.C, as shown in FIG. 5c. In this case, the total charge storage capacity is equal to:

In the case where the charge quantity to be stored Q is very low, it is possible as in the embodiment of FIG. 3a to only store charges in diode D' and on gate G.sub.1, as shown in FIG. 5d. In this case the total storage capacity C.sub.TT is equal to:

As in the embodiment of FIG. 3a, it is possible to bias V.sub.GST2 and V.sub.GST1 at different voltages, so that V.sub.GST1 is lower than V.sub.RAZ and V.sub.GST2 is lower than V.sub.GST1, but higher than V.sub.GC, as shown in FIG. 5e. In this case, charges Q are firstly integrated into diode D and on gate G.sub.1 and then beneath gate G.sub.ST1, finally being passed beneath gate G.sub.ST2.

The curves giving the output voltage variation as a function of charge Q corresponding to FIGS. 5b to 5c are shown in FIG. 6. In this case, line 2b has a slope proportional to ##EQU3## line 2c a slope proportional to ##EQU4## and line 2d a slope proportional to (1/C.sub.O). Moreover, curve 2e is constituted by three lines respectively having a slope proportional to (1/C.sub.O), then proportional to ##EQU5## and finally proportional to ##EQU6##

In FIGS. 7a to 7c are shown various possible arrangements for gates G.sub.ST1 and G.sub.ST2. One of the constraints imposed during the choice of the arrangement of gates G.sub.ST1 and G.sub.ST2 is that the reading diode D' and the gate G.sub.4 of the resetting MOS transistor M.sub.I3 must be adjacent to the first storage gate which it is wished to use. This gate is designated G.sub.ST1 in the embodiments of FIGS. 7a to 7c, the other adjacence conditions are optional. However, as shown in FIG. 7a, the diode D' can be positioned astride G.sub.ST1 and G.sub.ST2 and G.sub.4 is only adjacent to G.sub.ST1, or, as shown in FIG. 7b and 7c, diode D' may only be adjacent to gate G.sub.ST1 and gate G.sub.4, positioned astride G.sub.ST1 and G.sub.ST2. Moreover, in the case of FIGS. 7a to 7c, the electrons from the detector are not obliged to pass beneath the supplementary storage capacitor G.sub.ST2 and then gate G.sub.ST1 is adjacent to the control gate G.sub.C between the reading diode D of the photodetector and the first storage capacitor G.sub.ST1.

It is obvious that various other arrangements for gates GS.sub.T1 and G.sub.ST2 can be envisaged, without passing beyond the scope of the invention.

A description will now be given with reference to FIGS. 8a and 8b, of an embodiment of the present invention used in a photosensitive device, in which multiplexing is carried out in per se known manner with the aid of a charge transfer shift register R'. In this case, the charge integration and detection cells, which are not shown, are identical to the embodiment of FIG. 1. with the exception of the fact that they only have a single level of storage means. In this case, each storage means is connected to one stage of shift register R, which transfers the integrated charges by acting on the control phases .phi..sub.1 and .phi..sub.2 towards a charge--voltage conversion stage.

As shown in FIG. 8a, the charge--voltage conversion stage, which is separated from register R' by a passage gate G.sub.O, e.g. connected to a fixed voltage V.sub.GO, is constituted by a first storage means G'.sub.ST1 connected to a bias voltage raised to a high level V'.sub.GST1. This storage means is adjacent to a reading diode D'.sub.1 connected to an amplifier A' and to a resetting transistor constituted by the gate G'.sub.RAZ connected to a voltage .phi.'RAZ, which can be brought to a high level or a low level for precharging the reading diode and by the diode D'.sub.1 biased by the voltage V'.sub.RAZ.

According to the invention, a supplementary charge storage means constituted by capacitor G'.sub.ST2 is provided between gate G.sub.O and capacitor G'.sub.ST1. Capacitor G'.sub.ST2 is connected to a bias voltage V'.sub.GST2 which can be brought to a high or a low level, as a function of the quantity of charges to be read, as shown by the broken line in FIG. 8b. The operation of these two storage means G'.sub.ST1 and G'.sub.ST2 is identical to that of the storage means G.sub.ST1 and G.sub.ST2 in FIG. 1. In this embodiment, the use of supplementary storage means does not take it possible to reduce the dimensions of the integration and storage cells, as well as the shift register, which must be dimensioned so a to integrate the maximum charge, but it does make it possible to increase the gain of the output signal.

It is obvious to the worker in the art that the photosensitive device of FIG. 8a can be modified in numerous ways without passing beyond the scope of the invention. Thus, register R' can have 3 or 4 control phases. Gate G.sub.O can be connected to a fixed voltage as shown in FIG. 8a, or to the phase .phi..sub.1.

Moreover, in the two above embodiments, use has been made of one or two supplementary storage means. However, it is obvious that a larger number of storage means can be used without passing beyond the scope of the invention.

Furthermore, with regards to the control of the bias voltages V.sub.GST or V.sub.GST2, said voltages can either be positioned at the start of use as a function of the application or the type of photodetector used, or a servocontrol can be considered. In this case, the servocontrol takes account of the output voltage, compares it with two upper and lower reference voltages and as a function of the result of these comparisons switches the bias voltage of the supplementary storage means from a low level to a high level or vice versa, as explained hereinbefore.

The invention has been described with reference to a solid state photosensitive device, but it can obviously apply to all types of solid state devices in which the charge--voltage conversion stage is preceded by a storage capacitor, so as to increase the gain at the output. However, when the present invention is used in solid state photosensitive devices having as the multiplexer a charge transfer register, the invention can only be used at the reading stage and does not make it possible to reduce the dimensions of the shift register, which in all cases must be able to transfer the maximum admissible charge.