High Speed Control Circuit for Power Field Effect Transistors

The present invention relates to a high speed control circuit for power field effect transistors.

It applies to the construction of power supplies and chopping converters as well as to DC motor control devices.

The power transistors which are used in these applications must be able to switch rapidly, so as to reduce energy losses and increase the chopping frequency. The reduction of the energy losses increases the efficiency, simplifies the cooling systems and increases the reliability. Increasing the chopping frequency reduces the size and the price of the inductances of the transformers as well as of the capacitors used and increases the response speed of controlled systems.

However, the development of such devices is restrained by two main obstacles which limit the switching speed of the field effect transistors. This limiting factor is the high values of the input, gate-source C.sub.GS and drain-gate C.sub.DG capacities. The first capacitance (C.sub.GS) is caused by a simple capacitive effective. The second is caused by Miller effect. These two capacities increase the rise times of the control signals applied to the gate inputs of the field effect transistors, and determine the time required for passing from the voltage V.sub.GS(off) for which the transistor is disabled to the voltage V.sub.GS(on) for which it is enabled.

To reduce the opening or closing time of a power field effect transistor, one known solution consists in increasing the current flowing through the gate of the transistor. It requires inserting a current amplifier with a high switching speed between the control circuit and the gate of the power transistor. However, this solution meets some matching difficulties when in ceertain constructions a galvanic insulation must be inserted between the control circuit and the gate. This situation is met with more particularly when, for a static DC power supply, for example, the configuration of the chopper is such that the source of one or more power transistors is brought to a high or variable potential or when, for safety reasons, it is necessary to isolate the chopper circuit from the mains by a photocoupler or by a transformer.

Although the photocoupler allows the signal to be transmitted in the information state, it has the disadvantage of having to be followed by a high speed amplifier fed by an energy source itself galvanically isolated, which complicates this type of construction.

A transformer, on the other hand, overcomes this drawback, but in order to be efficient it must have a reduced leakage inductance so as to have a response compatible with the control time of a few nanoseconds for power field effect transistors, which makes this type of construction expensive.

The aim of the invention is to overcome the above mentioned drawbacks

For this, the invention provides a high speed control circuit for power field effect transistors including a transformer with primary and secondary windings for transmitting control signals to the gates of the field effect transistors, and further including:

energy storage means coupled to the transformer for storing, on the appearance of the control signals, the energy required for controlling the gates of the field effect transistors,

and transmission means coupled to the transformer and fed with energy by the storage means for applying the control signals, delivered by the transformers, with sufficient energy for controlling the gates of the field effect transistors.

Other features and advantages of the invention will be clear from the following description with reference to the accompanying drawings which show:

FIGS. 1 and 2, curves illustrating the behavior of a power field effect transistor when any control signal is applied to its gate electrode;

FIG. 3: the known organization for controlling a field effect power transistor;

FIG. 4: a representation of a control signal;

FIG. 5: a constructional diagram of a control device with a transformer of the "push-pull" type with two field effect power transistors; and

FIG. 6: an example of construction of a high speed control circuit with power field effect transistors of the invention.

The curves shown in FIGS. 1 and 2 illustrate the general known evolution of the gate-source voltage V.sub.GS of a field effect transistor as a function of the gate current I.sub.g which is applied thereto by its external gate control circuit. These curves result from the fact that the two input capacities, gate-source C.sub.GS and drain-gate C.sub.DG of a transistor limit the drift dV.sub.GS /dt of the possible gate-source voltage V.sub.GS with respect to time t. Therefore these capacities determine the minimum time required for passing from a gate voltage V.sub.GS(off) =0 to a gate voltage V.sub.GS(on), and the time for passing from the voltage V.sub.GS(on) to the voltage V.sub.GS(off) (switching on opening). The time for passing from V.sub.GS(off) to V.sub.GS(on) is, as a first approximation, equal to the sum of the charging time the input capacity C.sub.GS and of the discharging time of the drain-gate capacity C.sub.DG. In FIGS. 1 and 2 the gate-source capacity C.sub.GS is charged between times t.sub.0 and t.sub.1 by receiving an amount of electricity Q.sub.1 then, between times t.sub.2 and t.sub.3 by receiving an amount of electricity Q.sub.3 and the drain-gate capacity is discharged between times t.sub.1 and t.sub.2 by restoring an amount of electricity Q.sub.2.

Between times t.sub.o and t.sub.1, the whole of the gate current I.sub.g passes through the gate-source capacity C.sub.GS. At time t.sub.1 the amount of electricity Q.sub.1 stored in the gate-source capacity C.sub.GS confirms the equation: ##EQU1##

Between times t.sub.1 and t.sub.2, the voltage V.sub.GS is stabilized by the Miller effect to the value V.sub.GS(M), the gate-source capacity C.sub.GS receives a zero current and the drain-gate capacity C.sub.DG receives the whole of the gate current I.sub.g. At time t.sub.2 the amount of electricity which is passed through the drain-gate capacity C.sub.DG confirms the equation: ##EQU2##

Between times t.sub.2 and t.sub.3 the whole of the gate current I.sub.g flows through the gate-source capacity C.sub.GS. Between t.sub.2 and t.sub.3 the amount of electricity stored in the gate-source capacity C.sub.GS confirms the equation ##EQU3##

In the general case, with the function I.sub.g =f(t) unknown, it is not possible to calculate its primitive .intg.I.sub.g.dt. But since the initial and final stage t.sub.o and t.sub.3 are themselves defined and since as a first approximation the current I.sub.g may be considered as substantially constant in these intervals, it is possible to admit ##EQU4##

.epsilon..sub.1(g), .epsilon..sub.2(g), and .epsilon..sub.3(g) are respective primitives of the functions I.sub.g(t) defined in the intervals t.sub.o to t.sub.1, t.sub.1 to t.sub.2 and t.sub.2 to t.sub.3. I.sub.1g, I.sub.2g and I.sub.3g are the mean gate currents between t.sub.o and t.sub.1, t.sub.1 and t.sub.2, t.sub.2 and t.sub.3. These time intervals are defined by the relationships: ##EQU5##

The total switching time is therefore equal to tc=t.sub.3 -t.sub.o and equal to t.sub.3 -t.sub.2 +t.sub.2 -t.sub.1 +t.sub.1 -t.sub.o or else: ##EQU6##

The whole of these relationships shows that the times required for opening or closing the field effect transistor may be reduced by increasing the value of the mean current I.sub.2g.

But the dispersions of the voltage V.sub.GSth which represents the threshold gate-source voltage, on the one hand, and the need for rapid immunity to noise on closure as on opening, on the other hand, lead also to increasing the values of the mean currents I.sub.1 (g) and I.sub.3 (g).

Thus, in order to profit from one of the main advantages of a field effect transistor conferred by its high speed, it is necessary to give up the important advantage provided by its voltage control facilities. By taking for example the case of a type IRF350 transistor and taking into account the fact that its gate-source C.sub.GS and drain-source C.sub.DS capacities cannot be considered as constant for voltages V.sub.DS between 0 and 50 volts, the amount of electricity to be applied to the gate in order to obtain complete switching is Q.sub.1 +Q.sub.2 +Q.sub.3 =Q.sub.c =120 nanocoulombs. To provide switching under these conditions in a time (t.sub.3 -t.sub.o).ltoreq.60 nanoseconds, the current must be equal to ##EQU7##

This means, in known solutions, that high speed switching current amplifiers 1 must be inserted between the control circuits 2 of the field effect power transistors 3 in the way shown in FIG. 3, fed between a voltage potential V.sub.A and a ground circuit M. But these solutions, when they are used by providing galvanic insulation by means of a transformer, are costly. Furthermore, the leakage inductances L of the transformers must be reduced as much as possible so as to be compatible with the control times of a few tens of nanoseconds for field effect transistors.

The solution proposed by the invention consists in inserting between each transformer and field effect power transistor signal receiver at least one element which:

1. Demands energy of the transformer during the non significant phases of the signal and stores this energy,

2. Receives the significant phases of the signal while presenting an infinite impedance without consequently requesting energy from the transformer and without affecting the signal and finally

3. Transmits the signal with the energy required to the receiver considered, this energy being taken from the stock of energy formed during the non significant phases of the signal.

This principle may not only be applied to the construction of the signal receiving controls using the devices of the invention inserted between a secondary winding of a transformer delivering the control signal and each signal receiving device, but may also be applied, as is shown in FIG. 5, to several devices 5, 6 of the invention interposed between signal receivers formed by two series mounted "push-pull" transistors 8, 9 feeding into a common load 10 shown with broken lines; and secondary windings referenced respectively 7.sub.2 and 7.sub.3 of transformers 7 whose primary 7.sub.1 is controlled by rectangular type signals, of the form of the one shown in FIG. 4, having positive and negative half waves during time intervals A and C respectively and a zero amplitude during a time interval B intermediate between the intervals A and C.

One embodiment of the circuits 5 and 6 is shown in FIG. 6.

The circuit of the invention which is shown in FIG. 6 is placed between a signal transformer 11 having a primary and a secondary winding referenced respectively 11.sub.1 and 11.sub.2, and a signal receiver shown in FIG. 6 by a half stage 12 of a power series "push-pull", the other half stage 13 being shown in broken lines. The power receiver is controlled by two series connected "mosfet" stages 14 and 15 one of whose gates are connected directly to a terminal A of the secondary winding 11.sub.2, and the other gate connected through a capacitor 16 and a resistor 17 connected in parallel. Capacitors 18 and 19 are connected in parallel to the terminals of the secondary 11.sub.2 through two diodes 20 and 21 connected respectively by an anode and a cathode to the terminal A so as to form with capacitors 18 and 19 a voltage doubler.

Assuming that a signal of the type shown in FIG. 4 is applied to the primary 11.sub.1 of transformer 11, the operation of the circuit shown in FIG. 6 is as follows. This signal appearing at the terminals of the secondary winding 11.sub.2 charges capacitors 18 and 19 during the times marked A and C of FIG. 4 through diodes 20 and 21 to their peak values respectively. Transistors 14 and 15 are closed (OFF) respectively during the time intervals A and C of the signal. The charging currents for capacitors 18 and 19 are zero during the rising and falling fronts of the signal which under these conditions is not affected. The energy required for operation of transistors 14 and 15, which are connected as a follower source is then supplied by capacitors 18 and 19 which are then isolated from the secondary 11.sub.2 by the diodes 20 and 21 during the significant phases of the signal, the transistors 14 and 15 being open respectively during the time interval C and A. Thus, no energy is taken from the transformer during the significant phases of the signal. To make the circuit of the invention even more efficient, it will be possible to choose the input capacities of transistors 14 and 15 so that they are substantially a hundred times smaller than that of the power transistors 12 for resolving the rise and damping time problems. Similarly, the values of resistors 17, 22 and capacitor 16 will be chosen for efficiently biasing the transistor 15 so as to compensate for the threshold voltages V.sub.GSth and for lowering the plateau of the signal below the voltage 0 so as to increase the immunity to noise.