Analog Signal Multiplexer

This invention relates to analog signal multiplexers and, more particularly, to such a multiplexer that passes an analog signal with its normal polarity or its inverted polarity or prevents passage of the signal entirely.

Analog signal multiplexers switch input signals from one or more input paths to a single output path. These signals are often currents that can be summed or switched separately into the output path. For example, an analog signal multiplexer may receive three input currents and deliver any of these currents individually or summed together as an output signal.

The performance of an analog signal multiplexer is judged primarily on its precision, signal bandwidth, and switching speed. The precision, or linearity, is directly affected by changes in current as different input signals are switched to the output path and produce common mode voltage "bumps" or spikes in the switching process. The present invention overcomes this drawback by maintaining the linearity and signal bandwidth while switching between input paths.

An object of the invention therefore is to provide an improved analog signal multiplexer that minimizes bandwidth limitation, whose output signal is linearly proportional to its input signals and which provides switching speeds faster than presently available.

A second object of the invention is to provide for such a multiplexer a plurality of channels that are simple in design.

A third object of the invention is to provide such a channel that can also invert the polarity of its input signal in producing the output signal for the channel.

A fourth object of the invention is to provide such a channel that can turn off the signal path from the channel to the multiplexer.

To achieve these objects, an analog signal multiplexer according to the invention comprises a plurality of channels. Each channel includes a pair of differential amplifiers for receiving signals that form a differential signal and a pair of output transistors for applying negative feedback to each amplifier. Each output transistor produces an output signal that together form a differential output signal. The current gain of each output signal may be set by means such as a gain setting resistor in the emitter of each transistor. Each differential amplifier has a pair of emitter-coupled transistors with each transistor having a additional emitter cross-coupled to the additional emitter of the opposite transistor of the other emitter-coupled pair. To bias the emitter-coupled and the emitter cross-coupled pairs, a plurality of current sources are provided, each current source biasing a different pair.

Each channel of the analog signal multiplexer may operate in a number of different modes. In a NORMAL mode, current sources are enabled to bias the emitter-coupled pair of each differential amplifier to apply the two input signals comprising the differential input signal to the output transistors and produce a differential output signal of the same polarity as the differential input signal. In the INVERT mode, other current sources are enabled to bias the emitter cross-coupled transistor pairs to apply the input signals to opposite output transistors to produce a differential output signal with an inverted polarity. In an OFF mode each of the current sources is enabled to bias both the emitter-coupled transistor pairs and emitter cross-coupled pairs. With a substantially pure differential signal, both input signals of the differential input signal combine to produce no differential output signal.

The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description of a preferred embodiment which proceeds with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a channel of an analog signal multiplexer according to the invention.

FIG. 2 is partial schematic diagram of an analog signal multiplexer showing the connection of two channels.

FIG. 3 is a block diagram of an analog signal multiplexer comprising a plurality of channels.

FIG. 1 shows one channel of an analog signal multiplexer 10 embodying the invention. The circuit includes an input stage comprising a pair of differential amplifiers 12 and 14 for receiving a differential input signal comprising +V.sub.in and a -V.sub.in. The differential amplifier 12 includes a pair of emitter-coupled transistors Q.sub.1 and Q.sub.2, +V.sub.in being received by the input stage at the base of Q.sub.1. The differential amplifier 14 similarly includes a pair of emitter-coupled transistors Q.sub.4 and Q.sub.5, -V.sub.in being received at the base of Q.sub.4. Each of these transistors Q.sub.1 through Q.sub.4 includes a second emitter for cross coupling the transistor to the opposite transistor of the other differential amplifier. Q.sub.1, for example, is cross coupled to Q.sub.5 to form a first emitter cross-coupled transistor pair. Q.sub.2 is similarly cross-coupled to Q.sub.4 to form a second emitter cross-coupled transistor pair.

Q.sub.1 and Q.sub.2 are biased as an emitter-coupled pair by a first selectable current source comprising I.sub.1 and I.sub.2. Although I.sub.1 and I.sub.2 are shown as independent current sources that can be selectively activated, they also represent a single current source that can be turned off or enabled to provide two levels of current, the first level being half of the second level.

Q.sub.4 and Q.sub.5 are similarly biased as an emitter-coupled pair by a second selectable current source comprising I.sub.3 and I.sub.4. I.sub.3 and I.sub.4 are independent current sources that also represent a single second current source that can be turned off or enabled to provide the two levels of current.

Each emitter cross-coupled transistor pair is provided with its own selectable current source for bias. The first emitter cross-coupled pair comprising Q.sub.1 and Q.sub.5 is biased by a third selectable current source represented by independent sources I.sub.5 and I.sub.8. The second emitter cross-coupled pair comprising Q.sub.2 and Q.sub.4 is biased by a fourth selectable current source represented by independent sources I.sub.6 and I.sub.7. These current sources, as those previously described, represent a single current source that can be turned off or enabled to provide two selectable levels of current.

The differential amplifier comprising Q.sub.1 and Q.sub.2 is coupled to an output transistor Q.sub.3 that is biased by a current source I.sub.B. The base of Q.sub.3 is coupled to the collector of Q.sub.2, and a resistor R.sub.1 and voltage source that produce the collector current. The emitter of Q.sub.3 is coupled to the base of Q.sub.2 to provide negative feedback and produce a voltage +V.sub.o having unity voltage gain at the emitter of Q.sub.3 with respect to the input signal affecting Q.sub.2. The voltage +V.sub.o is applied across a gain-setting resistor R.sub.2 whose resistance determines the current gain of +I.sub.o at the collector of Q.sub.3. With the negative feedback, +I.sub.o is linearly proportional to the input signal applied to Q.sub.2. Similarly, the differential amplifier comprising Q.sub.4 and Q.sub.5 is coupled to an output transistor Q.sub.6 that is biased by current source I.sub.B through gain-setting resistor R.sub.5. The base of Q.sub.6 is coupled to the collector of Q.sub.5 and a resistor R.sub.4 and voltage source that produce the collector current. The emitter of Q.sub.6 is coupled to the base of Q.sub.5 to provide negative feedback and produce a voltage -V.sub.o having unity voltage gain with respect to the input signal affecting Q.sub.5. The voltage -V.sub.o is applied across resistor R.sub.5 to produce an output signal current -I.sub.o linearly proportional to the input signal applied to Q.sub.5.

Each channel described above of the analog signal multiplexer 10 can operate in three modes: NORMAL, INVERTED, or OFF. The mode chosen determines the form of the differential output signal. As will be explained, the differential input signal in the NORMAL mode is passed from the bases at Q.sub.1 and Q.sub.4 to the collectors of Q.sub.3 and Q.sub.6 to produce an output signal current of the same polarity. In the INVERTED mode, the polarity of the output signal currents is inverted, with +V.sub.in appearing as a signal current at the collector of Q.sub.6 and -V.sub.in appearing as a signal current at the collector of Q.sub.3. In the OFF mode portions of both +V.sub.in and -V.sub.in are applied to both Q.sub.2 and Q.sub.5, blocking the passage of any input signal to Q.sub.3 and Q.sub.6 and producing no differential output signal for the stage.

Table 1 for selecting the mode of operation desired is shown below.

In the NORMAL mode of operation, the input signal voltage +V.sub.in and -V.sub.in are reproduced as +V.sub.o and -V.sub.o across resistors R.sub.2 and R.sub.5. The emitter-coupled transistor pairs are biased by enabling current sources I.sub.1 through I.sub.4 and disabling I.sub.5 through I.sub.8. Assuming transistors Q.sub.1, Q.sub.2 and Q.sub.4, Q.sub.5 are balanced, equal amounts of current are drawn into the collectors of each transistor with the voltage at each base equal. As +V.sub.in and -V.sub.in vary, the voltage at the emitters of Q.sub.1 and Q.sub.4 will vary, affecting the current drawn through the collector of the emitter coupled transistors Q.sub.2 and Q.sub.5. As +V.sub.in rises, for example, the voltage across the base emitter junction of Q.sub.2 will decrease temporarily, decreasing the current drawn into the collector of Q.sub.2 and causing the voltage at the base of Q.sub.3 to rise. The voltage at the emitter of Q.sub.3 rises as a result. With the emitter voltage fed back to the base of Q.sub.2, the rising Q.sub.3 base voltage causes Q.sub.2 to draw more current through its collector and thereby lower its collector voltage. If +V.sub.in falls, on the other hand, the voltage across the base emitter junction of Q.sub.2 increases temporarily, increasing the current drawn into the collector of Q.sub.2 and thereby lowering the voltage at the base and emitter of Q.sub.3. The same response occurs with -V.sub.in and transistors Q.sub.5 and Q.sub.6. Thus, the differential input voltage equal to +V.sub.in -(-V.sub.in) is replicated across R.sub.2 and R.sub.5. The current +I.sub.o is therefore proportional to +V.sub.in and -I.sub.o is proportional to -V.sub.in.

In the INVERTED mode, the first emitter cross-coupled transistor pair Q.sub.5 and Q.sub.1 and the second cross-coupled pair Q.sub.4 and Q.sub.2 are biased by enabling current sources represented by I.sub.5 through I.sub.8 and disabling I.sub.1 through I.sub.4. The voltage +V.sub.in now affects transistor Q.sub.5 and output transistor Q.sub.6, and -V.sub.in affects transistor Q.sub.2 and transistor Q.sub.3. Q.sub.3 and Q.sub.6 respond as before, but the output signal currents +I.sub.o and -I.sub.o now have a polarity opposite of that +V.sub.in and -V.sub.in, respectively.

In the OFF mode, both the emitter-coupled pairs and the emitter cross-coupled pairs are biased by selecting the odd numbered current sources and disabling the even numbered sources, or vice versa. This cross biasing applies +V.sub.in and -V.sub.in to both Q.sub.2 and Q.sub.5.

The effect of applying +V.sub.in to the coupled pairs of Q.sub.1, Q.sub.2, and Q.sub.1, Q.sub.5 and applying -V.sub.in to the coupled pairs of Q.sub.4, Q.sub.2 and Q.sub.4, Q.sub.5 is best understood by example. Assume that no input signal is applied to the bases of Q.sub.1 and Q.sub.5 and that the bias voltage is zero volts. The emitter of Q.sub.1 will be changed to -0.7 volts. The base of Q.sub.2 will attempt to respond to the negative feedback of Q.sub.3 to change to zero volts. However, +V.sub.o, the Q.sub.2 base voltage, is also under the influence of -V.sub.in through the coupling of the additional emitter of Q.sub.2 to Q.sub.4. In this case, the additional emitter is also at -0.7 volts; so no voltage difference across the parallel emitters arises and Q.sub.2 base voltage changes to zero volts. The same result occurs at the base of Q.sub.5 and -V.sub.o changes to zero volts.

Now assume a small differential voltage is applied to the bases of Q.sub.1 and Q.sub.4, +0.1 volts at Q.sub.1 and -0.1 volts at Q.sub.4. The currents in the transistors will vary in response to the differing base voltages. Most of I.sub.1 flows through Q.sub.1 because +V.sub.in is more positive than +V.sub.o. Most of I.sub.7 flows through Q.sub.2 because -V.sub.in is less positive than +V.sub.o. Most of I.sub.3 flows through Q.sub.5 because -V.sub.in is less positive than -V.sub.o. Most of I.sub.5 flows through Q.sub.1 because +V.sub.in is more positive than -V.sub.o. As a result, one unit of current flows in Q.sub.2, and one unit in Q.sub.5 ; nearly two units of current flow in Q.sub.1 ; very little current flows in Q.sub.4. The current through the collectors of Q.sub.2 and Q.sub.5 remain constant as +V.sub. in and -V.sub.in vary.

If the input signal voltage is varied by a greater amount, for example, +V.sub.in up to 1 volt and -V.sub.in up to -1 volt, +V.sub.o and -V.sub.o continue to remain at zero volts. A +V.sub.n of 1 volt raises the emitter voltage of Q.sub.2 to 0.3 volts approximately. A -V.sub.in of -1 volt would cause the additional emitter's voltage to fall to -1.7 volts, but this fall is prevented by the limitation on +V.sub.o to zero volts. This voltage limits the emitter voltage of Q.sub.4 and Q.sub.2 to -0.7 volts, turning off the emitter of Q.sub.4 coupled to Q.sub.2 and the emitter of Q.sub.2 coupled to Q.sub.1. Similarly, -V.sub.o will not drop below zero volts, thereby shutting off the emitter of Q.sub.5 coupled to Q.sub.1 and the emitter of Q.sub.4 coupled to Q.sub.5. The other emitters of Q.sub.5 and Q.sub.2 remain active. Therefore, the collector currents through Q.sub.2 and Q.sub.5 remain constant when +V.sub.in and -V.sub.in are applied to both Q.sub.2 and Q.sub.5.

FIG. 2 shows a schematic section of two multiplexer channels together. The output currents +I.sub.o1 and +I.sub.o2 are summed at an output node 16 of the multiplexer. With both channels in the NORMAL mode, I.sub.oT is the sum of the two currents. With either channel in the INVERTED mode, I.sub.oT is the difference between the two currents. With either channel in the OFF mode, I.sub.oT will equal only the current of the enabled channel. Similarly, -I.sub.oT is the sum of -I.sub.o1 and -I.sub.o2 at an output node 18.

FIG. 3 shows a block diagram of a three channel analog signal multiplexer illustrating how a number of input signals can be multiplexed together. Each channel has a separate input signal path with the outputs of the channels combined in a common output signal path.

The advantage of the analog signal multiplexer 10 over the prior art is evident from the continuous flow of current that results when a channel is switched to the OFF mode. Unlike prior art multiplexers, no common mode voltage "bumps" or spikes occur when a channel is switched to the OFF mode or between other modes because the currents in Q.sub.2 and Q.sub.5 remain constant when +V.sub.in and -V.sub.in are applied to both transistors. The speed of the switching can be therefore higher because the differential amplifiers experience little adverse effect as the result of the rapid switching between modes.

Having illustrated and described the principles of the invention in a preferred embodiment, it should be apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, Q.sub.1 through Q.sub.8 are represented by single bipolar transistors. Alternative devices may also be used, such as Darlington pairs, field effect transistors, or combinations thereof.