Syndrome Calculating Apparatus

The present invention relates to syndrome calculating apparatus, and more particularly to syndrome calculating apparatus for obtaining syndromes from received codes where random errors and the like in received data are to be corrected with the Reed Solomon Code which is a kind of the BCH Code (Bose-Chaudhuri-Hocquenghem Code) used as an error correcting code.

In digital data transmission of high reliability, data are transmitted as coded in order to detect error patterns in received data and correct errors. In such case, it is most preferable to use, as an error correcting code, the Reed Solomon Code which has the highest correcting ability for random errors and which is a kind of the BCH Code.

In particular, optical disks recently developed present a higher error rate due to surface roughness of the optical disks themselves, turbulency of servo or the like, as compared with a magnetic disk device commonly used in the prior art. It is therefore indispensable to incorporate in an optical disk reproducing device a decoding device for detecting and correcting errors in data read from the optical disks.

Such decoding includes the following steps of:

(1) obtaining syndromes from a received data;

(2) obtaining the number of error locations from the syndromes;

(3) obtaining the dimension of an error; and

(4) executing error correction.

The Reed Solomon Code is constituted by the elements in the Galois field GF (q.sup.m). For a digital circuit, q=2 can be established. When the primitive element of this Galois field GF (2.sup.m) is .alpha., the following equation is established:

When m bits constitute 1 symbol, the generator polynomial for error correction of t symbols can be expressed by the following equation:

The code polynomial of a transmission code of a data symbol added by an inspection symbol is expressed by the following equation: ##EQU1##

Accordingly, when f (x) is equal to 0, then 1, .alpha., .alpha..sup.2, . . . , .alpha..sup.2t-1, or .alpha., .alpha..sup.2, . . . , .alpha..sup.2t are the root.

That is, the following equations are established: ##EQU2##

In fact, when the transmission code above-mentioned (b.sub.0, b.sub.1, . . . , b.sub.n-1) is transmitted and received, it is not ensured at all that the received code (a.sub.0, a.sub.1, . . . , a.sub.n-1) is the same as the transmission code and it is therefore not ensured that 0 is obtained for all equations above-mentioned.

Therefore, the following equations are established: ##EQU3##

S.sub.i (i=0, 1, . . . 2t) becomes 0 when the transmission code has been received without errors, but it becomes other value than 0 if the transmission code has been erroneously received. Such S.sub.i is defined as a syndrome.

Therefore, from syndromes S.sub.0, S.sub.1, . . . , S.sub.2t-1 obtained according to the equations above-mentioned, an error location polynomial is obtained. Then, the inverse elements of the roots of the error location polynomial can be obtained so that the error locations are obtained and the error are corrected.

In a series of the calculations above-mentioned, the calculations for obtaining the respective syndromes S.sub.0, S.sub.1, . . . , S.sub.2t-1 are surprisingly troublesome. In order to carry out these calculations at a high speed, there has been conventionally proposed syndrome calculating apparatus constituted by, for example, ROM tables and shift registers (Unexamined Patent Publication No. 5759/1984).

This syndrome calculating apparatus above-mentioned is designed to calculate the following equations faithfully: ##EQU4##

It is therefore required to use ROMs having an excessively great capacity, and the syndrome calculating time cannot be sufficiently shortened, as a whole.

It is an object of the present invention to provide syndrome calculating apparatus capable of calculating syndromes at a high speed.

It is another object of the invention to provide syndrome calculating apparatus having a simplified structure.

In order to achieve the objects above-mentioned, the syndrome calculating apparatus in accordance with the invention comprises:

first addition means for respectively supplying the bits of each of unit codes constituting a received code to a plurality of latch means;

second addition means for supplying, to at least one of the plurality of latch means, the output bit of at least one of the plurality of latch means;

gate means for supplying the signals of the first and second addition means to the plurality of latch means, respectively; and

gate control means for selectively opening the gate means;

the output bits of the plurality of latch means being supplied respectively to the first addition means connected to the vary latch means;

the output bit of said at least one of the plurality of latch means being supplied to the second addition means connected to said at least one of the plurality of latch means so as to produce the same result as that obtained by the multiplication of power of the root of the primitive polynomial in the Galois field.

In obtaining syndromes by successively entering received codes to the syndrome calculating apparatus arranged as above-mentioned, one gate means is opened by a control signal from the gate control means so that only the respective bits of each of unit codes constituting a received code, or the unit codes constituting a received code and the output bits of the plurality of latch means as respectively added to each other by the first addition means, are supplied again to the plurality of latch means. Then, the other gate means is opened by a control signal from the gate control means so that the output bits of the plurality of latch means as added to one another by the second addition means are supplied to at least one of the plurality of latch means so as to produce the same result obtained by the operation of multiplication power of the root of the primitive polynomial in the Galois field. Thereafter, one gate means and the other gate means are alternately opened so that the addition and latch operations above-mentioned are repeated. Then, there can be finally obtained the bits constituting the syndromes, from the respective latch means.

The foregoing will be discussed in more detail in the following.

When the following polynomial is considered:

the multiplication by (2.sup.m -1) power of the root .alpha. in the primitive polynomial in the Galois field GF (2.sup.m), results in 1 and the following equation is established: ##EQU5##

Therefore, by repeating a series of operations of the multiplication of the unit codes of a received code by .alpha..sup.j, the addition of the results thus multiplied, to the next unit codes and the multiplication by a.sup.j of the results thus added, the syndrome S.sup.i can be finally obtained.

It is preferable that the syndrome calculating apparatus in accordance with the present invention comprises:

a pair of calculating units to which unit codes in the odd place and unit codes in the even place are respectively entered successively;

third addition means for adding the output bits of one of the pair of calculating units to which unit codes in the even place are successively entered, to one another so that such addition corresponds to the operation of multiplication of power of the root; and

fourth addition means for adding the output bits of the other of the pair of calculating units to which unit codes in the odd place are successively entered, to the output bits of the third addition means in a correlative manner; and each calculating unit further comprises:

first addition means for respectively supplying the bits of each of unit codes constituting a received code to a plurality of latch means;

second addition means for supplying, to at least one of the plurality of latch means, the output bit of at least one of the plurality of latch means;

gate means for supplying the signals of the first and second addition means to the plurality of latch means, respectively;

gate control means for selectively opening the gate means;

the output bits of the plurality of latch means being supplied respectively to the first addition means connected to the vary latch means;

the output bit of said at least one of the plurality of latch means being supplied to the second addition means connected to said at least one of said plurality of latch means so as to produce the same result as that obtained by the operation of multiplication of power of the root of the primitive polynomial in the Galois field.

In obtaining syndromes by successively entering received codes to the syndrome calculating apparatus arranged as above-mentioned, unit codes in the odd place and unit codes in the even place are respectively supplied to the pair of calculating units successively. In each of the calculating units, one gate means is opened by a control signal from the gate control means so that only the respective bits of each of unit codes constituting a received code, or the unit codes constituting a received code and the output bits of the plurality of latch means as respectively added to each other by the first addition means are supplied again to the plurality of latch means. Then, the other gate means is opened by a control signal from the gate control means so that the output bits of the respective latch means as added to one another by the second addition means are supplied to at least one of the plurality of latch means so as to produce the same result obtained by the operation of the multiplication of power of the root of the primitive polynomial in the Galois field. Thereafter, one gate means and the other gate means are alternately opened so that the addition and latch operations above-mentioned are repeated to carry out necessary calculations. Thereafter, the output bits of one of the calculating units to which unit codes in the even place are successively entered, are added to one another by the third addition means to obtain the output bits equal to values obtained by the multiplication of power of the root. Then, the output bits of the other of the calculating units to which unit codes in the odd place are successively entered, are added to the output bits of the third addition means by the fourth addition means in a correlative manner. There can be finally obtained the bits constituting syndromes.

The foregoing will be discussed in more detail in the following.

When the following polynomial is considered:

it is easily made sure that this polynomial is the same as the following formula:

Since this formula has the same form as that of the syndrome calculating formula, the syndrome can be expressed in the form of T.sub.i (.alpha..sup.j).

The syndrome S.sub.i (i=0, 1, . . . , 2t or 2t-1, where t is the error correcting ability) in the Reed Solomon Code having a code length n=2.sup.m -1 can be obtained by the following equation:

where (b.sub.n-1, b.sub.n-2, . . . , b.sub.1, b.sub.0) are transmission signals.

The syndromes S.sub.i above-mentioned can be changed into the following equation so that S.sub.i can be expressed in the form of T.sub.i (.alpha..sup.j). ##EQU6## where p=2.sup.m-1 -1

Accordingly, a series of operations of respectively fetching the unit codes of received codes in the odd place and even place successively, multiplying these codes by .alpha..sup.j, adding the results thus multiplied to the next unit codes and multiplying the results thus added by .alpha..sup.j, are repeated. Then, the output bits of the calculating unit for the odd place are added to one another so that such addition corresponds to the operation of multiplication of power of the root. Then, the bits obtained) by this addition are added to the output bits of the calculating unit for the even place in a correlative manner (so that such addition produces the same result obtained by the calculation of

where p=2.sup.m-1 -1.

Then, the syndrome S.sub.i can be finally obtained.

Further, when the Galois field above-mentioned is GF (2.sup.m), there can be obtained syndromes for decoding binary received codes used in transmission of digital data, reading of digital data from optical disks, etc. and so forth.

FIG. 1 is an electric circuit diagram showing an embodiment of a syndrome calculating unit for calculating a syndrome S.sub.1.

FIG. 2 is an electric circuit diagram showing an embodiment of a syndrome calculating unit for calculating a syndrome S.sub.2.

FIG. 3 is an electric circuit diagram showing an embodiment of a syndrome calculating unit for calculating a syndrome S.sub.3.

FIG. 4 is an electric circuit diagram showing an embodiment of a unit for generating a control signal.

FIGS. 5(A)-(D) is a timing chart illustrating a syndrome calculating operation.

FIGS. 6(6-1 and 6-2) is an electric circuit diagram showing another embodiment of a syndrome calculating unit for calculating a syndrome S.sub.2.

FIG. 7 is a timing chart illustrating a syndrome calculating operation in the embodiment in FIG. 6.

FIG. 8 is an electric circuit diagram showing another example of latch means.

FIG. 9 is a block diagram schematically showing processing for decoding with the use of syndrome calculating apparatus in accordance with the present invention.

FIG. 9 is a block diagram schematically showing processing for decoding received codes with a double error correcting RS code in GF (2.sup.4) with the use of syndrome calculating apparatus in accordance with the present invention.

To syndrome calculating units 1, 2, 3 and 4 for respectively calculating syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3, the unit codes of a received code, a unit code fetching controlling signal, a signal for controlling addition corresponding to multiplication and a clock signal are supplied in succession to obtain the syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3. These syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 are entered into a decoding device 9 so that a series of codes in which errors have been corrected can be obtained.

The primitive polynomial in the Galois field GF (2.sup.4) is given by x.sup.4 +x+1. Where the root of this primitive polynomial is .alpha., the following equation is established:

Since the Galois field GF (2.sup.4) is an extension field of the ground field GF (2), the operation conditions in the GF (2) are satisfied in the operations in the Galois field GF (2.sup.4), so that the following equations are established:

Accordingly, the equation above-mentioned .alpha..sup.4 +.alpha.+1=0 is the same as .alpha..sup.4 =.alpha.+1.

This embodiment employs the following generator polynomial g (x):

The syndrome calculating unit 1 is so designed as to calculate S.sub.0 =a.sub.0 +a.sub.1 + . . . +a.sub.14. It is therefore sufficient to add in succession the unit codes of a received code entered, to one another as they are. The syndrome S.sub.0 can be easily obtained by using, for example, an arrangement which has JK flip-flops (not shown) each corresponding to each of the bits of a unit code and which is designed to supply, to a JK input terminal of the JK flip-flops, the respective bits of a unit code and the output of corresponding JK flip-flops are supplied through XOR gates (not shown).

FIG. 1 is an electric circuit diagram showing an embodiment of the syndrome calculating unit 2 for calculating the syndrome S.sub.1.

The syndrome calculating unit 2 has four JK flip-flops 21a, 21b, 21c and 21d respectively corresponding to the bits of each of unit codes of a received code, and includes XOR gates 22a, 22b, 22c and 22d to which the respective bits of a unit code and the output signals of the JK flip-flops 21a, 21b, 21c and 21d are supplied, AND gates 23a, 23b, 23c and 23d adapted to be opened by a gate control signal 5 for supplying the output signals from the XOR gates 22a, 22b, 22c and 22d to OR gates 24a, 24b, 24c and 24d, respectively, and AND gates 25a, 25b, 25c and 25d adapted to be opened by a gate control signal 6 for supplying the output signals of the JK flip-flops to the OR gates 24a, 24b, 24c and 24 d, respectively. An XOR gate 26b is disposed at the input side of the AND gate 25b. The output signals of the JK flip-flops 21a and 21d are supplied to the input terminal of the XOR gate 26b. The output signal of the JK flip-flop 21b is supplied to the input terminal of the AND gate 25c. The output signal of the JK flip-flop 21d is supplied to the input terminal of the AND gate 25a. The output signal of the JK flip-flop 21c is supplied to the input terminal of the AND gate 25d. Further, a clock signal 7 and a clear signal (not shown) are respectively supplied to a clock input terminal and a clear input terminal of each of the JK flip-flops 21a, 21b, 21c and 21d.

The following description will discuss the operation of the syndrome calculating unit 2 arranged as above-mentioned.

For example, an arbitrary element in the Galois field GF (2.sup.4) is expressed by the following equation:

Therefore, the following equations are established: ##EQU7##

Accordingly, when the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 are respectively supplied to the XOR gates 22a, 22b, 22c and 22d and the AND gates 23a, 23b, 23c and 23d are opened by the gate control signal 5, the JK flip-flops 21a, 21b, 21c and 21d supply the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 as they are. Therefore, when the AND gates 25a, 25b, 25c and 25d are opened by the gate control signal 6, the bit c.sub.3 is supplied to the JK flip-flop 21a, the bit c.sub.0 and the bit c.sub.3 as added to each other by the XOR gate 26b are supplied to the JK flip-flop 21b, the bit c.sub.1 is supplied to the JK flip-flop 21c and the bit c.sub.2 is supplied to the JK flip-flop 21d. That is, with no multiplication specially carried out, a series of bits corresponding to c.sub.3 +(c.sub.0 +c.sub.3).alpha.+c.sub.1 .alpha..sup.2 +c.sub.2 .alpha..sup.3 are supplied from the JK flip-flops 21a, 21b, 21c and 21d.

FIG. 2 is an electric circuit diagram showing an embodiment of the syndrome calculating unit 3 for calculating the syndrome S.sub.2.

The syndrome calculating unit 3 has four JK flip-flops 31a, 31b, 31c and 31d corresponding to the respective bits of each of unit codes of a received code, and includes XOR gates 32a, 32b, 32c and 32d to which the respective bits of a unit code and the output signals of the JK flip-flops 31a, 31b, 31c and 31d are supplied, AND gates 33a, 33b, 33c and 33d adapted to be opened by the gate control signal 5 for supplying the output signals of the XOR gates 32a, 32b, 32c and 32d to OR gates 34a, 34b, 34c and 34d, respectively, and AND gates 35a, 35b, 35c and 35d adapted to be opened by the gate control signal 6 for supplying the output signals of the JK flip-flop to the OR gates 34a, 34b, 34c and 34 d. XOR gates 36b and 36c are disposed at the input side of the AND gates 35b and 35c. The output signals of the JK flip-flops 31c and 31d are supplied to the input terminal of the XOR gate 36b. The output signals of the JK flip-flops 31a and 31d are supplied to the input terminal of the XOR gate 36c. The output signal of the JK flip-flop 31c is supplied to the input terminal of the AND gate 35a. The output signal of the JK flip-flop 31b is supplied to the input terminal of the AND gate 35d. Further, a clock signal 7 and a clear signal (not shown) are respectively supplied to a clock input terminal and a clear input terminal of each of the JK flip-flops 31a, 31b, 31c and 31d.

The following description will discuss the operation of the syndrome calculating unit 3 arranged as above-mentioned.

The following equation is established: ##EQU8##

Accordingly, when the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 are respectively supplied to the XOR gates 32a, 32b, 32c and 32d and the AND gates 33a, 33b, 33c and 33d are opened by the gate control signal 5, the JK flip-flops 31a, 31b, 31c and 31d supply the bits above-mentioned c.sub.0, c.sub.1, c.sub.2, c.sub.3 as they are. Therefore, when the AND gates 35a, 35b, 35c and 35d are opened by the gate control signal 6, the bit c.sub.2 is supplied to the JK flip-flop 31a, the bits c.sub.2 and c.sub.3 as added to each other by the XOR gate 36b are supplied to the JK flip-flop 31b, the bits c.sub.0 and c.sub.3 as added to each other by the XOR gate 36c are supplied to the JK flip-flop 31c, and the bit c.sub.1 is supplied to the JK flip-flop 31d. That is, with no multiplication specially carried out, the JK flip-flops 31a, 31b, 31c and 31d supply a series of bits corresponding to c.sub.2 +(c.sub.2 +c.sub.3).alpha.+(c.sub.0 +c.sub.3).alpha..sup.2 +c.sub.1 .alpha..sup.3.

FIG. 3 is an electric circuit diagram showing an embodiment of the syndrome calculating unit 4 for calculating the syndrome S.sub.3.

This syndrome calculating unit 4 has four JK flip-flops 41a, 41b, 41c and 41d corresponding to the respective bits of each of units codes of a received code, and includes XOR gates 42a, 42b, 42c and 42d to which the respective bits of a unit code and the output signals of the JK flip-flops 41a, 41b, 41c and 41d are supplied, AND gates 43a, 43b, 43c and 43d adapted to be opened by a gate control signal 5 for supplying the output signals of the XOR gates 42a, 42b, 42c and 42d to OR gates 44a, 44b, 44c and 44d, respectively, and AND gates 45a, 45b, 45c and 45d adapted to be opened by a gate control signal 6 for supplying the output signals of the JK flip-flops to the OR gates 44a, 44b, 44c and 44 d, respectively. XOR gates 46b, 46c and 46d are disposed at the input side of the AND gates 45b, 45c and 45d. The output signals of the JK flip-flops 41b and 41c are supplied to the input terminals of the XOR gate 46b. The output signals of the JK flip-flops 41c and 41d are supplied to the input terminals of the XOR gate 46c. The output signals of the JK flip-flops 41a and 41d are supplied to the input terminals of the XOR gate 46d. The output signals of the JK flip-flops 41b is supplied to an input terminal of the AND gate 45a. Further, a clock signal 7 and a clear signal (not shown) are respectively supplied to a clock input terminal and a clear input terminal of each of the JK flip-flops 41a, 41b, 41c and 41d.

The following description will discuss the operation of the syndrome calculating unit 4 arranged as above-mentioned.

The following equation is established: ##EQU9##

Accordingly, when the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 are respectively supplied to the XOR gates 42a, 42b, 42c and 42d and the AND gates 43a, 43b, 43c and 43d are opened by a gate control signal 5, the JK flip-flops 41a, 41b, 41c and 41d supply the bits above-mentioned c.sub.0, c.sub.1, c.sub.2 and c.sub.3 as they are. Therefore, when the AND gates 45a, 45b, 45c and 45d are opened by a gate control signal 6, the bit c.sub.1 is supplied to the JK flip-flop 41a, the bits c.sub.1 and c.sub.2 as added to each other by the XOR gate 46b are supplied to the JK flip-flop 41b, the bits c.sub.2 and c.sub.3 as added to each other by the XOR gate 46c are supplied to the JK flip-flop 41c, and the bits c.sub.0 and c.sub.3 as added to each other by the XOR the 46d are supplied to the JK flip-flop 41d. That is, with no multiplication specially carried out, the JK flip-flops 41a, 41b, 41c and 41d supply a series of bits corresponding to c.sub.1 +(c.sub.1 +c.sub.2).alpha.+(c.sub.2 +c.sub.3).alpha..sup.2 +(c.sub.0 +c.sub.3).alpha..sup.3.

In each of the syndrome calculating units above-mentioned, after the necessary additions have been made, the clear signal (not shown) is supplied to the JK flip-flops to clear the contents of the JK flip-flops to zero, thus preparing for the next syndrome calculation.

FIG. 4 shows an embodiment of a circuit for generating the gate control signals 5 and 6, and the clock signal 7.

In this embodiment, a clock signal 53 externally supplied, is used, as it is, as the clock signal 7. This clock signal 53 as inverted by an inverter 51 is supplied to a clock input terminal of a T flip-flop 52. A positive power voltage is applied to a T input terminal and a clear signal 54 is supplied to a clear terminal. The output signal Q, as it is, of the T flip-flop 52 is used as the gate control signal 6. This output signal Q taken out through an inverter 55 is used as the gate control signal 5.

FIG. 5 is a timing chart illustrating the syndrome calculating operation above-mentioned.

The clock signal 7 is a pulse signal having a predetermined period as shown by D in FIG. 5. At the falling timing of this pulse signal, the JK flip-flops fetch data.

As respectively shown by C and B in FIG. 5, the gate control signals 5 and 6 have a period twice the period of the clock signal 7 and are opposite in phase for alternately opening the AND gates.

Accordingly, while the gate control signal 5 is in the high level the first time, the AND gates are opened to supply the first unit code a.sub.14 (See A in FIG. 5) of a received code to the JK input terminals of the JK flip-flops and this unit code a.sub.14 is fetched by the JK flip-flops at the falling timing of the clock signal 7.

Then, while the gate control signal 6 is in the high level, the AND gates are opened to supply the output signals of the JK flip-flops to the JK input terminals of the JK flip-flops so as to produce the same result obtained by the operation of multiplication of power of .alpha., and the output signals above-mentioned are fetched by the JK flip-flops at the falling timing of the clock signal 7.

While the gate control signal 5 becomes the high level the second time, the AND gates are opened to supply the second unit code a.sub.13 of the received code (See A in FIG. 5) and the output signals of the JK flip-flops as added by the XOR gates, to the JK input terminals of the JK flip-flops, and at the falling timing of the clock signal 7 the signals thus added are fetched by the JK flip-flops.

Then, while the gate control signal 6 is in the high level, the AND gates are opened to supply the output signals of the JK flip-flops to the JK input terminals of the JK flip-flops so as to produce the same result obtained by the operation of multiplication of power of .alpha., and at the falling timing of the clock signal 7 the output signals above-mentioned are fetched by the JK flip-flops.

Thereafter, a series of operations above-mentioned to be made after the gate control signal 5 has become the high level the second time, are repeated many times as required so that a syndrome can be obtained.

That is,

and

the operations of the multiplication of power of .alpha. (to be carried out for the first operation only) and the multiplication of the multiplied result added to the next unit code, by power of .alpha., are repeated for each period of the gate control signal as the number of iterations as required, so that a syndrome can be obtained.

In the embodiment above-mentioned, the JK flip-flops are used as latch means. As shown in FIG. 8, however, the similar results can be achieved by supplying the clock signal inverted by an inverter 62, to a clock input terminal of a D flip-flop 61.

The XOR gates (which are connected to the AND gates to be opened by the gate control signal 6) corresponding to addition means are not always connected to all JK flip-flops. However, it can be considered that the portions of the JK flip-flops to which the XOR gates are not connected, carry out addition exerting no influence upon the output signals of the JK flip-flops (for example, addition of zero). Therefore, XOR gates having one input terminal to which 0 is always supplied, can be connected to these portions of the JK flip-flops.

FIG. 6 is an electric circuit diagram showing another example of the syndrome calculating unit 3 which is mainly constituted by a calculating portion 3a for fetching unit codes in the odd place sequentially, and a calculating portion 3b for fetching unit codes in the even place sequentially, these calculating portions 3a and 3b being disposed for calculating the syndrome S.sub.2.

In FIG. 6, like parts are designated by like numerals as in the embodiment in FIG. 2.

The calculating portion 3a has four JK flip-flops 31a, 31b, 31c and 31d corresponding to the respective bits of each of unit codes of a received code, and includes addition circuits 32a, 32b, 32c and 32d to which the respective bits of a unit code and the output signals of the JK flip-flops 31a, 31b, 31c and 31d are supplied, AND gates 33a, 33b, 33c and 33d adapted to be opened by a gate control signal 5a for supplying the output signals of the addition circuits 32a, 32b, 32c and 32d to OR gates 34a, 34b, 34c and 34d, respectively, and AND gates 35a, 35b, 35c and 35d adapted to be opened by a gate control signal 6a for supplying the output signals of the JK flip-flops 31a, 31b, 31c and 31d to corresponding OR gates 34a, 34b, 34c and 34d.

Addition circuits 36a, 36b, 36c and 36d comprising for example XOR gates are disposed at the input side of the AND gates 35a, 35b, 35c and 35d. The output signals of the JK flip-flops 31a and 31d are supplied to the input terminals of the addition circuit 36a, while the output signals of the JK flip-flops 31a, 31b and 31d are supplied to the input terminals of the addition circuit 36b. The output signals of the JK flip-flops 31b and 31c are supplied to the input terminals of the addition circuit 36c, while the output signals of the JK flip-flops 31c and 31d are supplied to the input terminals of the addition circuit 36d. A clock signal 7a is supplied to a clock input terminal of each of the JK flip-flops 31a, 31b, 31c and 31d. The description is omitted of the calculating portion 3b which has the same arrangement of that of the calculating portion 3a.

Further, the syndrome calculating unit 3 has a third addition unit 37 which includes an addition circuit 37a for adding the output signals of the JK flip-flops 31a and 31d of the calculating unit 3b to which unit codes in the even place are successively entered, and an addition circuit 37b for adding the output signals of the JK flip-flops 31c and 31d of the calculating unit 3b. This third addition unit 37 is adapted to supply the output signals of the JK flip-flops 31b and 31c as they are, thus producing the same result obtained by the multiplication of .alpha..sup.2.

Further, the syndrome calculating unit 3 has a fourth addition unit 38 which includes addition circuits 38a, 38b, 38c and 38d. These addition circuits 38a, 38b, 38c and 38d respectively add each of the output signals of the JK flip-flops 31a, 31b, 31c and 31d of the calculating portion 3a to which unit codes in the odd place are successively entered, to the output signal of the JK flip-flop 31c of the calculating portion 3b, the output signal of the addition circuit 37b, the output signal of the addition circuit 37a and the output signal of the JK flip-flop 31b of the calculating portion 3b, respectively, thereby to obtain the syndrome S.sub.2.

Inverters 39a and 39b are disposed for obtaining gate control signals 5b and 6b in inverted state of gate control signals 5a and 6a. A gate circuit 39c is adapted to be opened by a control signal and designed to generate a clock signal 7b of the calculating portion 3b, in addition to the clock signal 7a of the calculating portion 3a.

The following description will discuss the operation of the syndrome calculating unit arranged as above-mentioned.

Where q.sub.i =a.sub.2i and p.sub.i =a.sub.2i+1, the syndrome S.sub.2 can be expressed by the following equations: ##EQU10##

Since q.sub.i is also an element of the GF (2.sup.4), q.sub.i can be expressed by the following equation:

Therefore, q.sub.i .alpha..sup.4 can be expressed by the following equation: ##EQU11## The same can be applied to p.sub.i .alpha..sup.4

Accordingly, when the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 are respectively applied to the addition circuits 32a, 32b, 32c and 32d and the AND gates 33a, 33b, 33c and 33d are opened by the gate control signal 5a, the JK flip-flops 31a, 31b, 31c and 31d supply the bits c.sub.0, c.sub.1, c.sub.2 and c.sub.3 as they are. Therefore, when the AND gates 35a, 35b, 35c and 35d are opened by the gate control signal 6a, the bits c.sub.0 and c.sub.3 as added to each other by the addition circuit 36a, are supplied to the JK flip-flop 31a, the bits c.sub.0, c.sub.1 and c.sub.3 as added to one another by the addition circuit 36b are supplied to the JK flip-flop 31b, the bits c.sub.1 and c.sub.2 as added to each other by the addition circuit 36c are supplied to the JK flip-flop 31c and the bits C.sub.2 and c.sub.3 as added to each other by the addition circuit 36d are supplied to the JK flip-flop 31d. That is, without multiplication specially carried out, the JK flip-flops 31a, 31b, 31c and 31d supply a series of bits corresponding to (c.sub.0 +c.sub.3)+(c.sub.0 +c.sub.1 +c.sub.3).alpha.+(c.sub.1 +c.sub.2).alpha..sup.2 +(c.sub.2 +c.sub.3).alpha..sup.3.

By repeating the operations above-mentioned, T.sub.7 (.alpha..sup.4) can be obtained in the calculating portion 3a, while T.sub.6 (.alpha..sup.4) can be obtained in the calculating portion 3b.

Thereafter, by supplying the output bits of the calculating portion 3b to the third addition circuit 37, the output signals of the JK flip-flops 31c and 31d are added to each other, the output signals of the JK flip-flops 31a and 31d are added to each other and the output signals of the JK flip-flops 31b and 31c are supplied as they are.

That is, there can be supplied the same output signals as those obtained when the following calculation is carried out; ##EQU12##

Finally, the output signals of the calculating portion 3a and the output signals of the third addition circuit 37 are supplied to the fourth addition circuit 38, so that T.sub.7 (.alpha..sup.4)+.alpha..sup.2 T.sub.6 (.alpha..sup.4)=S.sub.2 or the syndrome S.sub.2 can be obtained.

The following description will discuss in more detail the foregoing with reference to FIG. 7 showing a timing chart.

The clock signals 7a and 7b (See A and B in FIG. 7) having the same phase and the same period are supplied to the JK flip-flops 31a, 31b, 31c and 31d of each of the calculating portions 3a and 3b, the gate control signals 5a and 5b (See C and E in FIG. 7) opposite in phase and having the same period are supplied to the AND gates 33a, 33b, 33c and 33d, and the gate control signals 6a and 6b (See D and F in FIG. 7) opposite in phase and having the same period are supplied to the AND gates 35a, 35b, 35c and 35d. The gate control signals 5a and 6a above-mentioned are opposite in phase and have the same period, and the gate control signals 5b and 6b above-mentioned are opposite in phase and have the same period. The gate control signals above-mentioned have a period twice that of the clock signal.

Accordingly, at the beginning of syndrome calculation, the gate control signal 5a is in the high level to open the AND gates 33a, 33b, 33c and 33d of the calculating portion 3a, so that the first unit code a.sub.14 (See G in FIG. 7) is fetched by the JK flip-flops 31a, 31b, 31c and 31d.

Then, the gate control signal 5a becomes the low level to close the AND gates 33a, 33b, 33c and 33d of the calculating portion 3a. As the result, fetching of a unit code is stopped, and the gate control signals 5b and 6a become the high level. When the gate control signal 5b becomes the high level, the AND gates 33a, 33b, 33c and 33d of the calculating portion 3b are opened so that the second unit code a.sub.-- is fetched by the JK flip-flops 31a, 31b, 31c and 31d. When the gate control signal 6a becomes the high level, the AND gates 35a, 35b, 35c and 35d of the calculating portion 3a are opened. The output signals of the JK flip-flops 31a, 31b, 31c and 31d are then supplied respectively to the corresponding addition circuits 36a, 36b, 36c and 36d, in which necessary addition operations are carried out. The results thus added are again fetched by the JK flip-flops 31a, 31b, 31c and 31d.

Thereafter, the gate control signal 5b becomes the low level to close the AND gates 33a, 33b, 33c and 33d of the calculating portion 3b. As the result, fetching of a unit code is stopped, and the gate control signals 5a and 6b become the high level. When the gate control signal 5a is in the high level, the AND gates 33a, 33b, 33c and 33d of the calculating portion 3a are opened so that the third unit code a.sub.12 is fetched by the JK flip-flops 31a, 31b, 31c and 31d. When the gate control signal 6b is in the high level, the AND gates 35a, 35b, 35c and 35d of the calculating portion 3b are opened. The output signals of the JK flip-flops 31a, 31b, 31c and 31d are then supplied respectively to the corresponding addition circuits 36a, 36b, 36c and 36d, in which necessary addition operations are carried out. The results thus added are again fetched by the JK flip-flops 31a, 31b, 31c and 31d.

Thereafter, by repeating the operations above-mentioned, unit codes in the even place and unit codes in the odd place are respectively fetched by the calculating portions 3a and 3b. The unit codes thus fetched are subjected to addition corresponding to the multiplication of power of the root. The timing of the unit code fetching and addition in the calculating portion 3a is reverse to that in the calculating portion 3b. As a whole, therefore, the fetching and addition operation is not interrupted at all, thus assuring high-speed processing.

The detailed description above-mentioned has been made of another example of the syndrome calculating unit 3 for calculating the syndrome S.sub.2. For other syndromes S.sub.1 and S.sub.3, a syndrome calculating unit similar to said another example can be used, which will be schematically discussed in the following.

For the syndrome S.sub.1, the following equation is established: ##EQU13##

For the syndrome S.sub.3, the following equation is established: ##EQU14##

Accordingly, for the syndrome S.sub.1, it is enough to dispose a calculating portion for calculating T.sub.7 (.alpha..sup.2), a calculating portion for calculating T.sub.6 (.alpha..sup.2), an addition circuit which produces the same result obtained by the multiplication of the calculation result of T.sub.6 (.alpha..sup.2) by .alpha. and another addition circuit for adding the output signal of the first-mentioned addition circuit to the calculation result of T.sub.7 (.alpha..sup.2).

For the syndrome S.sub.3, it is enough to dispose a calculating portion for calculating T.sub.7 (.alpha..sup.6), a calculating portion for calculating T.sub.6 (.alpha..sup.6), an addition circuit which produces the same result obtained by the multiplication of the calculation result of T.sub.6 (.alpha..sup.6) by .alpha..sup.3 and another addition circuit for adding the output signal of the first-mentioned addition circuit to the calculation result of T.sub.7 (.alpha..sup.6).

After a series of calculating operations required have been carried out, a clear signal is supplied to the JK flip-flops 31a, 31b, 31c and 31d to clear the content to zero, thus preparing for the next syndrome calculation.

For a circuit for generating the gate control signals 5a and 6a and the clock signal 7a, there can be used the circuit shown in FIG. 4 as it is. That is, the gate control signals 5 and 6 in the circuit in FIG. 4, are used, as they are, as the gate control signals 5a and 6a, while the clock signal 7 as it is used as the clock signal 7a.

As apparent from the foregoing, with a simple arrangement of feedback units and addition units only, this embodiment can eliminate time of waiting for unit code fetching and time of waiting for addition operation, thereby to achieve the syndrome calculation at a high speed.

In the embodiment above-mentioned, the JK flip-flops are used as latch means. As shown in FIG. 8, however, the same results can be achieved by supplying a clock signal inverted by the inverter 62 to the clock input terminal of the D flip-flop 61.

It is noted that the present invention should not be limited to these embodiments above-mentioned. For example, for the application where the code length is long and there are many error correcting symbols, this invention can be used by changing the combination of the gates. In addition, the following equation can be used as the generator polynomial g (x):

Various modifications in designing can be made without departing from the spirit of the invention.