US 4,763,288 AGrant
System for Simulating Electronic Digital Circuits
Issue Date:1988-08-09
•13 Claims
•16 Drawing Sheets
Abstract
A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor. The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs. When the circuit is simulated, the start time and finish time for each component is determined, giving the execution time for the circuit. Output data from a group is made available to other groups when the simulated time is advanced to the finish time for the group. Proper timing is thus assured without performing the simulation at the pixel level.
Metadata
Assignee
- Schlumberger Systems & Services, Inc.
Inventors
- Michael F. Deering
- Neil Hunt
Application Information
Application Number:US 8154716
Filing Date:1985-12-31
Priority Date:1985-12-31
Art Unit:234
Classifications
IPC:
G06G 748G06F 1100
Field of Search:
364340371578-580;518;149-151706;73220;23
Patent Drawings (16 sheets)
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for simulating the behavior of electrical circuits. In particular, the invention relates to a method and apparatus for simulating, on a computer, the behavior of electronic circuits having high speed, computationally intensive pipelined components for processing digital data.
2. Description of the Prior Art
Electrical circuit simulators have existed for many years as part of computer-aided circuit design systems. The circuit designer uses simulators to aid in the development of electrical circuits. The simulator models the behavior of a proposed circuit design, usually on a computer, without requiring the acquisition and interconnection of the particular discrete circuit components.
Some simulators allow the designer to analyze a high level functional model of the circuit, by computing the results of a particular set of processing operations on vectors of data elements, without regard for timing details such as whether data elements arrive at components in synchronization, or the time that the processing operations will take. This model is efficient to execute on a computer and is useful at the early stages of design.
Lower level simulation models provide the detailed timing analysis at the data element level which is necessary to verify that the circuit will actually work as desired and to determine how long it will take. A conventional simulator which provides details at the data element level normally operates at the data element level. In such simulators, a variable is used to indicate the current simulated time. All events which occur at this time are simulated before the time variable is advanced to the next time. The speed and capabilities of modern digital circuits make it very inefficient to simulate the behavior of such circuits in this manner, particularly on sequential processors.
In pipelined digital systems, signals representing discrete data elements flow through a sequence, or pipeline, of processing components in turn, being transformed at each stage. At any time, many different components are actively processing different data elements. Parallel paths in the circuit may also be active at the same time processing the same or different data elements. If a system simulates a pipelined system in the conventional manner, it simulates all of the processing of data elements which occurs at each component at a specific time. Then, it advances its time variable to the next simulated time and simulates the processing of the data elements which have been transformed at the previous times. The computational overhead of routing the data elements from each output of each component to the inputs of its successor components is incurred for each active component at each advance of simulated time. The simulator must determine the correct inputs to the correct successor components by searching the data structures which describe the circuit components and their connections.
The programming code to route the data elements from component to component in a conventional prior art simulator is substantially large compared to the code to simulate the actual processing of data elements. If data element routing is performed for each data element which is output from each active component, only a small fraction of computer processing time is spent replicating the processing of data elements. This inefficienoy can seriously degrade the performance and increase the effective costs of the simulation. For circuits having parallel pipelines of high speed, computationally intensive components, the costs and elapsed time of such a simulation process limits its effectiveness as a design aid.
SUMMARY OF THE lNVENTION
A simulator for electronic digital circuits is provided which combines the efficiency of a high level functional simulation with the detailed timing analysis which has heretofore been provided only by simulation at the data element level. The inefficiencies of routing individual data elements from component to component at each time increment are avoided by routing entire vectors of data elements. The processing at each component is simulated for an entire vector of data elements before the processing of a vector by the next component is simulated. The substantial reduction in computational overhead which is achieved by routing vectors instead of data elements makes it possible to perform very extensive calculations to discover how the simulation would have performed at the data element level. It is thus possible to ensure that the circuit works at the data element level and to calculate the time that the actual processing will take.
According to the invention, the processing of a vector of data elements by each component in a synchronous group is simulated and any output vectors are stored for access by other components. As each component is simulated, a finish time for the component is calculated. The timing of the group is synchronized by ensuring that signals representing corresponding data elements will arrive together at components having multiple inputs.
According to a further aspect of the invention, the simulation of a plurality of independently synchronized groups is possible. The invention ensures that data generated by the simulation of each group is made available only to those other groups which will start processing after the first group is finished.
In the preferred embodiment described herein, an apparatus and method are described for simulating the behavior of circuits having high-speed, computationally intensive components for processing visual image data. A frame of image data is input from a video camera and the output of the simulated processing is displayed on a monitor The results of the detailed timing analysis are reported to the designer. By utilizing the novel techniques taught by this invention, the inefficiencies of conventional simulators are avoided without the loss of critical timing detail.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. l is a block diagram of a preferred embodiment of an apparatus for simulating the behavior of a circuit for processing digital visual image data;
FIG. 2 is a block diagram illustrating the major functional blocks of the simulation system;
FIG. 3 is a block diagram of the internal data structures which describe the circuit to be simulated;
FIGS. 3A-3B are illustrations of a circuit segment and the corresponding data structures;
FIG. 4 illustrates the high level functional flow of the circuit simulation function;
FIG. 5 is a flow chart illustrating the circuit checking function for editing the schematic diagram of the circuit to be simulated;
FIGS. 6 and 6A-6D are flow charts of the function which determines of the group to be simulated;
FIGS. 7 and 7A-7C are flow charts of the function which calculates the scaling factors at each net;
FIGS. 8 and 8A-8E are flow charts of the timing analysis function;
FIGS 9 and 9A-9B are flow charts of the group simulation function;
FIGS. 10 and 10A-10B are flow charts of the post-simulation update function. de
DESCRIPTION OF PREFERRED EMBODIMENT
The present preferred embodiment of the invention will now be described in detail with reference to the accompanying drawings. In this embodiment, the circuit to be simulated consists of specialized VLSI components for visual image processing and computer vision applications. A description of typical visual signal processing (VSP) components simulated in this embodiment is included in Appendix A.
In the context of visual signal processing, input and output vectors are referred to as frames, and data elements are referred to as picture elements, or pixels. The digital representation. of a visual image is a rectangular frame of pixels, where each pixel is a discrete rectangular area within the frame having a value corresponding to the brightness of the image over that area.
FIG. 1 is a block diagram of a typical embodiment of an apparatus 10 for simulating the behavior of circuits which process digital visual image data. The apparatus comprises video camera 12, frame buffer 14, workstation 16 and video monitor means 18. Frame buffer 14 incorporates analog-to-digital converter means 20 and digital-to-analog converter means 22. The analog output signal of video camera 12 is coupled into analog-to-digital converter means 20 and converted to digital form. Frame buffer 14 is coupled to workstation 16 so that workstation 16 can read from and write to frame buffer 14. The analog output of digital-to-analog converter means 22 is supplied to grey-scale monitor means 18 for display.
Workstation 16 is typically a programmable digital computer having a monitor with a bit map display, and user interface means such as a keyboard and/or a "mouse." For example, a "Sun 2/160" workstation from Sun Microsystems, Inc. of Mountain View, Calif. may be used. Frame buffer card VG-121 from Data Cube Inc. of Peabody, Mass. may be used with this workstation. The frame buffer contains control logic to accept a continuous stream of image data, to capture one frame upon receipt of a command from workstation 16, and to generate a continuous stream of image data for display by repeatedly displaying the image stored in the frame buffer.
A user interfaces with the system by interacting with the workstation display in a graphical manner. Using a mouse or other pointing device, the user places component icons on a schematic diagram, and draws in interconnections representing pixel bus connections. These component icons represent functional abstractions which can be achieved using one or more VSP chips.
Typically a camera icon will be included in the schematic, corresponding to the real video camera 12. This allows real images to be input to the simulation. lmages are transferred between analog-to-digital converter means 20, frame buffer 14, and digital-to-analog converter means 22 as a stream of pixels scanned from the image line-by-line. One digitized image may be captured by the frame buffer 14 and input to workstation 16.
Results from the simulation, if in the form of images, are written to frame buffer 14 and displayed on monitor means 18 by including a monitor icon in the schematic. The image stored in the frame buffer is repeatedly output to digital-to-analog converter means 22 and displayed on monitor means 18. An analysis of the timing behavior may be displayed at workstation 16.
Rather than including a camera icon in the schematic, the user may include a different icon which will cause digitized images to be read from digital storage means. Similarly, results may be written to digital storage means using a file writing icon.
Workstation 16 is programmed according to the invention to accept and simulate the circuit entered in schematic form by the user. The block diagram of FIG. 2 illustrates the major functional blocks of the simulation system. Command interpreter 30 accepts commands entered from the keyboard, or selected from a menu with the mouse. When a valid command is accepted, command interpreter 30 calls the appropriate function to execute the command. Schematic editor 32 is called for accepting, editing and storing schematics entered by the user. One of the commercially available schematic capture programs may be used for the schematic editor. Image display subsystem 34 is called to execute commands which allow the user to interact with the image displayed on one or more monitors. The circuit simulator 36 is called to simulate the behavior of the circuit using parameters set by the user. Other user commands are executed by functional block 38 to perform such functions as saving and loading data files and controlling debugging options.
FIG. 3 is a block diagram of the internal data structures 39 used in this embodiment to store data describing a circuit in the computer memory in a format which can be used by the circuit simulator 36. These data structures may be constructed directly by schematic editor 32. Alternatively, the data structures may be reconstructed from a file previously created by schematic editor 32.
Several different kinds of data structures are used in this embodiment to represent the circuit components and their interconnections. Those data structures which describe the components include the component-type structures 40, the component-instance structures 42, and the component-data structures 44.
The component-type structures 40 are data structures containing data fields which describe the fixed properties of each type of component. There is one component-type structure for each type of component known to the system. The user may define new types to the system. Fixed properties include the number of input and output pins for each type of component, pointers to the functions which implement the simulation of the component at various phases of the simulation, the component delay and incremental clock rate scaling factors, and various flags indicating such things as whether the component is an independent source or an independent destination.
The schematic of a circuit which is entered by the user typically contains 0, 1, or many "instances" of particular component types. While the fixed properties of these component types need not be repeated for each component instance, properties which are not fixed must be described for each component instance. The component-instance structures 42 and component-data structures 44 contain the variable, or "per-component instance," data. There is one component-instance structure and one component-data structure for each component instance in the schematic. The component-instance structures 42 are data structures containing all of the per-component instance data fields which are relevant to all of the different types of components. The compo- nent-data structures 44 also contain per-component instance data, but these structures contain different data fields for each type of component, typically the data fields which are needed to describe the internal state of the component instance.
Pointers are used to link the component-instance structures 42 to the appropriate component-type structure 40 and component-data structures 42. Together, these data structures describe all of the fixed and variable properties of a particular component instance without redundancy.
The net-instance structures 46 are data structures containing data fields which describe the interconnections between component instances. A net instance represents a bundle of wires, each capable of carrying one bit, plus hand-shaking and clock connections. The connect structures 48 are data structures containing data fields which describe the way in which component instances are connected to the net. The connect structures 48 also describe how and which bits of the net are connected to the component instance. One or many components may drive bits of the net, and one or more components may be driven by the net.
FIGS. 3A and 3B illustrate how pointers in the data structures are used to describe a segment of a typical circuit. FIG. 3A shows a circuit segment containing one net 56 driving two component instances 58 and 60, via connections 62 and 64. FIG. 3B illustrates the corresponding data structures and pointers. Net-instance structure 66 points to one connect structure 68. The connect structures 68 and 70 represent connections 62 and 64 connected to one end of net 56 and are linked by a pointer. The connect structures also point to the component-instance structures 72 and 74, and to the net-instance structure 66. The component-instance structures 72 and 74, representing component instances 58 and 60, point to the net-instance structure 66, component-data structures 76 and 78, and component-type structures 80 and 82.
Returning to FIG. 3, it is seen that the internal data structures also include component-list structure 50 and net-list structure 52. As each new component-instance structure is allocated it is added to the component-list data structure 50. This allows all of the components in the circuit to be visited once by traversing the list, rather than having to follow the connectivity of the circuit. Similarly the net-list structure 52 contains a list of all the net-instances in the circuit.
The logic of the simulation function will now be described with reference to FIGS. 4-10C. Component instances generally will be referred to as components in this description.
FIG. 4 illustrates the high level functional flow of the simulation function 36. The circuit checking function 86 edits the internal data structure representation of the circuit for completeness and for compliance with specific design rules. If the circuit passes all of the checks without any problems, the initialization and control function 88 performs component configurations and controls the actual simulation of groups of components. The control function requests the simulation of a group of components by specifying a component. The build-groups function 90 then determines which other components are members of the same group. A group of components is defined as a set of components which must operate in synchronism. Clock rate scaling function 92 traverses the components in the group to compute clock rate scaling factors for each net. Timing analysis function 94 computes the relative timings around all of the component instances in a group and resolves delays for variable delay components. The group is then scheduled (96) for simulation. Eventually, the simulation function 98 simulates the behavior of the group. Each of these functions will now be described in greater detail.
Referring to FIG. 5, the circuit checking function 86 first performs component checks at block 100. This function checks that the component list is not null, that each element in the component list is a valid component, and that each component-instance has a valid pointer to a component-type structure. At block 102, each component is checked to verify that it has all of its inputs and outputs connected to exactly one net, and that the net is in the net list. At block 104, any special per component type checks are performed. At block 106, the check nets function checks that the net list is not null, that each net is driven by at least one component and that each net drives at least one component. At block 108, the connect structures are checked to insure that they are correctly linked to the component and net-instance data structures. Any errors detected by circuit checking function 86 are reported back to the user. If no errors are detected, execution proceeds to the initialization function (FIG. 4, block 88).
In the real system which is simulated by the simulator described in this embodiment, execution is controlled by a control program supplied by the user. This program is executed on a control processor connected to each of the components. In the simulator, this control program may default to the virtual program, contained in the simulator. Alternatively, the user may supply actual program code to replace all or part of the virtual program. The user code is linked into the simulator and executed on the same processor that executes the simulation.
The user code performs initialization function 88. Components are configured by calling functions which are provided in the simulator which interact with the simulation of components, allowing component modes and behaviors to be controlled just as if the code were accessing the real hardware. If any component is not configured by the user code, a default configuration is effected by the virtual program.
The control program next prepares groups of components for simulation by calling the start-group function to prepare and schedule a particular group of components for execution. Referring to FIG. 6, the start-group function 600 is illustrated. This function is called with a pointer to a component instance structure (normally for a source component, such as a camera). At block 602, a test is made to determine if the specified component is a member of a group which is already marked active (either because it has just been scheduled or because it has not finished execution from some previous scheduling). If the component is active, control returns to the caller at block 604 with an error indicator. Otherwise, at block 606, the build-group function is called to compile a list of all of the components and nets in the group containing the specified component. When control returns to the start-group function, the scaling and timing functions will have been executed, and, at block 608, the defined group is scheduled for simulation. Control then returns to the control program at block 610.
A group of components is a set of connected components which must operate in synchronism. A group is delimited by components which have no pixel input (e.g. cameras), components which have no pixel output (e.g. correlators), or components which have both an input and an output but where the input and output are completely independent (e.g. the frame buffer component). Disabled components are considered as components with no output and thus as destination components. Groups must be recompiled at every rescheduling because the extent of the group may vary if components are disabled. Since the control program can alter the enabled or disabled stated of each component, it could alter the effective connectivity of the circuit and hence the extent of groups of components within a circuit.
The build-group function 606 is illustrated in FIG. 6A. The build-group function 606 performs a recursive walk over the circuit data base to discover the extent of the group and build a list of components and nets in the group. It is called with a pointer to a component-instance structure. At block 612, a test is made to determine whether the specified component is enabled and, if not, at block 614, control returns to the calling program with an error indicator. At block 616, a test is made to see whether the specified component has been marked as active. An active component is one that is part of a group that has been scheduled for execution and has not completed execution. At block 620, a new group data structure is created. The build-scan-comp-out function is then called at block 622, to start the recursion. When control returns to the build-group function the group will have been defined. The build-group function will, at block 624, call the clock rate scaling function for this group. Then, at block 626, the timing analysis function is called for this group. At block 628, control returns to the start-group function.
Referring to FIG. 6B, the build-scan-comp-out function 622 is illustrated. This function is called with pointers to a specific component, the group list, and a "from-net." The from-net is an indicator of the net which was traversed to arrive at this component, and is used to avoid recursing indefinitely around a loop of components. (This parameter is null on the first call for a source component.) At block 630 the specified component is marked as active. At block 632, a test is made to determine whether the component is enabled; if not, control returns to the caller at block 634. If the component is not disabled and it is not already on the group list (block 636) then, at block 638, the component is added to the group list. Then, at blocks 642 and 644, for each of the nets connected to the outputs of this component, a test is made to determine whether this net is the from-net and has therefore already been traversed. If it is not, then, at block 646, the build-scan-net function is called for this net. Then, if this component is an independent source component (block 648), it is added to the list of source components at block 650 and control is returned to the calling program at block 652. Otherwise, at blocks 654 and 656, for each of the nets connected to the inputs of the specified component, a test is made to see whether this net is the from-net. If it is not, the function build-scan-net is called at block 660 for this net. When all of the input nets for this component have been examined, control is returned to the calling program at block 662.
Referring to FIG. 6C, the build-scan-net function 664 is illustrated. This function is called with pointers to a particular net, a "from-component" (indicating the component from where this net was followed) and the group list. If this net is already on the group list, (block 666) control is returned to the calling program at block 668. Otherwise, at block 670, the net is added to the group list. Then, at blocks 672 and 674 for each of the components driven by this net a test is made to determine whether this component is the "from-component", in which case the component has already been visited, and it is ignored. Otherwise, at block 676 the function build-scan-comp-in is called for this component. Then, at blocks 678, 680 and 682, for each of the components driving this net, if it is not the from-component, the function build-scan-comp-out is called. Control returns to the calling program at block 684.
Referring to FIG. 6D, it will be seen that the build-scan-comp-in function 686 is symmetrical to the build-scan-comp-out function. It is called with pointers to a specific component-instance, the group list, and a from-net. At block 688, the specified component is marked active and at block 690, a test is made to determine whether the component is enabled. If not, control is returned to the caller at block 692. Otherwise, at block 694, the group list is checked to determine whether this component is already on the group list, and, if it is, control returns to the caller at block 696. Otherwise, at block 698, the component is added to the group list. Then, at block 700 and 702, for each of the nets connected to the inputs of this component, a test is made to see whether it is the from-net and has already been visited. If it has not been visited, the function build-scan-net is called at block 704 for this net. If this component is an independent destination component, (block 706) control is returned to the calling program at block 708. Otherwise, at blocks 710 and 712, and 714, for each of the nets connected to the outputs of this component a test is made to see if it has already been visited, and, if not, the function build-scan-net is called. When all of the nets connected to this component have been examined, control returns to the caller at block 716.
In this manner, the functions build-scan-comp-in and build-scan-comp-out are invoked for all of the components in the specified group so that when they have all returned, the group list structure contains a list of all of the components and nets in the group and all of the source components in the group.
When control returns to the build-groups function, it calls the find-scaling function. This function traverses the components in the group again, in exactly the same manner as the build-group functions above, but this time to compute the clock rate scaling factors for each net.
A common clock is connected to all of the components in the group. The clock rate scaling factor describes the ratio of clock cycles to valid pixels at each net in a group. For each group there is a single clock rate which is the fastest rate at which pixels can flow from component to component. At many nets in the group, valid pixels must necessarily flow more slowly than this maximum rate. Components in the group may produce one output pixel for each input pixel, a single output pixel for a number of input pixels, or a number of output pixels for a single input pixel. If a component outputs one pixel for every two incoming pixels, then the output net will exhibit half as many valid cycles as the input net. Likewise, if a component outputs two pixels for every one pixel input, then the input net will exhibit half as many valid cycles as the output net, to leave enough time for the component to output all of its valid output pixels. The clock rate scaling factor is a vector quantity with three components: the line rate scaling factor, the pixel rate scaling factor and the clock scaling factor. The clock scaling factor is the number of clock cycles per clock cycle and is therefore always unity. The pixel rate scaling factor is the number of clock cycles per valid pixel, and therefore must be greater than or equal to unity. The line rate scaling factor describes the number of line cycles per valid line, where a line cycle is defined as the clock cycle time multiplied by the pixel scaling factor and by the line length of the image. It is also greater than or equal to unity.
An incremental scaling factor parameter associated with each component instance is set when the component is configured and stored in the component-instance data structure. The incremental scaling factor is a vector quantity giving the ratio of the output net scaling factors to the input net scaling factors. For example, a component which outputs one pixel for every two input has an incremental pixel scaling factor of two.
Scaling factors must be identical at each point in the group where nets converge. Therefore, components with multiple inputs must have the same scaling factors on each of their input nets. Similarly, components with multiple outputs must have the same scaling factors on each of their output nets. The clock rate scaling functions propagate the scaling factors from net to net using the incremental scaling factors for each component. The group is traversed in the same recursive manner as the build-group functions described above.
Referring to FIG. 7, the find-scaling function 624 is illustrated. References to scaling factors are to the vector quantities described above. The find-scaling function is called by the build-group function with a pointer to a group list. The group list contains a list of all of the components and nets in a group. At block 722, the find-scaling function examines all of the source components in the group to see whether the user has specified an absolute scaling factor for any of the source outputs in the group. If no specified scaling factor is found, then an arbitrary component is selected and a scaling factor of one is assumed. Otherwise, the specified component and rate are used as a starting point. At block 726, the function scaling-comp-out is then called to begin the recursive walk through the group from the selected starting point. When control is returned to the find-scaling function at block 728, the scaling factors are normalized. If a fractional scaling factor was assigned at any net, then the scaling factors of the whole group are divided by the smallest scaling factor to make them all greater than or equal to unity. This insures that there is never more than one pixel passed per clock cycle. A warning message is issued if the real circuit will not behave properly under the settings and conditions imposed by the user.
FIG. 7A illustrates the scaling-comp-out function 740. This function is called with pointers to a component, a from-net and a scaling factor. If the component is not enabled (block 742) control is returned to the calling program at block 744. Otherwise, at blocks 746 and 748, the scaling factor is propagated to all of the output nets by calling the scaling-net function for each of the output nets connected to this component. At block 750, the input scaling factors are computed for the specified component by dividing the output scaling factors by the incremental scaling factors. Then, at blocks 752 and 754, the newly computed input scaling factor is propagated to all of the input nets of this component by calling the function scaling-net for each of the input nets connected to this component. Control is then returned (at block 756) to the calling program.
The function scaling-net 760 is illustrated in FIG. 7B. This function is called with pointers to a net, a from-component, and a scaling factor. At block 762, a test is made to determine whether this net has been visited before. This is done by determining whether a scaling factor for this net has been defined in the net-instance structure. If a scaling factor has been defined, its value is compared (block 764) to the value to be propagated to determine whether an error condition exists, and control is returned to the calling program at block 766. If this net has not been visited before, the scaling factor for this net is stored in the net-instance structure at block 768. Then, at blocks 770 and 772, for each of the components with inputs connected to this net, a check is made to determine whether the component is disabled. If the component is disabled, it is ignored. If the component is enabled, the scaling-comp-in function is called for this component at block 774. Then, at blocks 776 and 778, for each of the components with outputs connected to this net, a test is made to determine whether the component is disabled and, if it is, it is ignored. Otherwise, at block 780, the scaling-comp-out function is called for this component.
The scaling-comp-in function 782 is illustrated in FIG. 7C. This function is called with pointers to a component, a from-net and a scaling factor. It is symmetrical to the scaling-comp-out function. At block 784, a test is made to see if the component is disabled, and if it is, control is returned to the caller at block 786. Otherwise, at blocks 788 and 790, the scaling factor is propagated to all of the other input nets of this component, by calling the scaling-net function for each of the input nets connected to this component. Then at block 792, the output scaling factors are computed by multiplying the input scaling factors by the incremental scaling factors. At blocks 794 and 796, the newly computed output scaling factor is then propagated to all of the output nets of this component by calling the function scaling-net for each of the output nets connected to this component. After the scaling, the scaling variable in the net-instance structure for each net in the group contains values of the line, pixel, and clock scaling factors for that net.
When control returns to the build-group function from the find-scaling function, time-scan function is called to perform the timing analysis. This is the final pre-simulation phase. The timing analysis function computes the relative timings around all of the components in a group, and resolves the delays for components having variable delays. It checks that all of the fixed delays add up to the same number at the same place for each possible path through the group. Given that the scaling rates are also matched, which has already been enforced by the scaling functions discussed above, this insures that the pixels on each input for multiple input components arrive in synchronism.
When the group is simulated, entire frames of pixels are simulated at each component, stored, and passed from component to component. The timing analysis function provides the detailed evaluation of pixel synchronism which would otherwise be lost by simulating at the frame level.
Some components in the circuit may reduce the size of the image by subtracting pixels or lines. To evaluate synchronism, the concept of a reference pixel, or "first virtual pixel" is useful. The "first virtual pixel" is the first pixel which would have been output if an alteration in size had not occurred, i.e., the first pixel in the largest image in the group. If the time of arrival of the first virtual pixel on each of the input nets of a component with multiple inputs is the same, and the scaling factors are also the same, then all of the corresponding pixels in the images will arrive together, even if one of the images is of a different size than the other.
Generally, the designer wants images to arrive at components with multiple inputs in direct correspondence, i.e., with pixels corresponding to the same location in the frame arriving together. Sometimes an indirect correspondence is desired, e.g., with each line from one input corresponding to the next line from another input. Indirect correspondence is achieved by specifying an offset for a variable delay component (one line of offset in this example). In this case, the simulator will first match the arrival time of the first virtual pixel and then add the offset to the variable delay.
The delay between the input of a pixel to a component and the output of the corresponding pixel is a characteristic of a component in a given configuration. Components may have a fixed delay, or a variarble delay which is set by the user when the real circuit is executed. Component delays are stored in the component-instance structure as vectors with three values: clock delay, pixel delay, and line delay. The timing analysis traverses the group and uses the delays to compute the time (relative to the group start time) at which the first virtual pixel arrives at each net in the group. The pixel delay is multiplied by the pixel scaling factor and the line delay is multiplied by the line scaling factor. The relative times for each net are expressed in terms of clock cycles, valid pixel cycles, and valid line cycles.
The component-instance data structures contain vector variables referred to here as output time and input time. These variables represent the relative time at which the first virtual pixel arrives at all outputs (or inputs) of a component. They are initially undefined and are computed by the timing analysis function. In the following discussion of the timing analysis function, it will be understood that these times are always relative to the starting time of a particular group. Similarly, the net-instance data structures contain a vector variable referred to herein as net time, and it will be understood that the net time represents the relative time at which the first virtual pixel arrives at a particular net. It follows that the net time must match the output time for a component if the net is an output net of the component, or the input time for an input net. The timing analysis will enforce this requirement.
The timing analysis functions will now be described in detail. All function calls are followed by a test of a return code to determine whether the called function has detected an error. In this manner, detected errors will result in warning messages being issued and processing being aborted. The details of return code processing are known to those skilled in the relevant arts.
Referring to FIG. 8, the function time-scan 626 is illustrated. This function is called with a pointer to a group list. At blocks 802, 804, and 806 the function time-scan-comp-out is called for each source component and for each mode. The timing analysis will be repeated for each of the timing modes-clocks, pixels and lines. When time-scan-comp-out has been called for each source component and for each mode, then at blocks 808, 810, and 812, for each net in the group list and for each mode, a test is made to determine whether there are an excessive number of variable delays in the system. This test is done by checking the net time. If the net time is still undefined at block 812, then there are too many variable delays and a warning message is issued at block 814. When the timing analysis is complete, control returns to the calling program at block 816.
The remaining timing analysis functions are all called with a mode indicator and will perform their function on variables for the indicated timing mode. This selection of variables for a particular mode is implied in the following discussion.
Referring to FIG. 8A, the function time-scan-comp-out 820 is illustrated. This function is called with pointers to a component-instance, a from-net and the net time determined by the calling program. The from-net indicates the net which was traversed to arrive at this component and is used to limit the recursion. At block 822 a test is made to determine whether the specified component is disabled. If the component is disabled, control returns to the calling program at block 824 with an error indicator. At block 826, a test is made to determine whether the output time for this component has been defined. If it has, at block 828, the output time is compared to the net time which was passed to this function indicating the net time on the output net. If these times are unequal, then control returns to the caller at block 830 with an error indicator. Otherwise, processing continues at block 832. If the output time at this component is undefined, then, at block 834, output time is set to the value of net time passed to this function. This value will now be applied to all of the other output nets. At block 836 and 838, for each net connected to the output of this component, a test is made to determine whether this output net has been is the from-net. If it is the from-net, then it is ignored. Otherwise at block 840, the function time-scan-net is called, with the output time passed as one of the parameters.
At block 832, a test is made to determine whether this component is an independent source component. If it is, then a test is made at block 842 to determine whether the output time for this component is zero. If not, an error indicator is set at block 844. Control is returned to the calling program at block 846. If this component is not an independent source component, then processing continues. At blocks 848 and 850, for each input net to this component, a test is performed to determine whether the scaling factor at this input net equals the scaling factor at the other input nets for this component. This is done by initializing a local variable for the scaling factor as undefined and then setting this variable to the scaling factor value at the first input net that is visited. Then as each input net is visited, its scaling factor is compared to the stored local scaling factor. If any of the scalingwhether the compontrol returns to the calling program at block 852 with an error indicator.
If the scaling factors at all of the inputs are equal, processing proceeds. The flow chart continues at FIG. 8B. At block 854, a test is made to determine the delay is undefined, then a test is made at block 856 to determine whether the input time for this component has been determined. If the input time is not known, control returns to the caller at block 858. If the input time has been defined then the delay is calculated from the input and output times at block 860.
The delay is calculated as follows: First the input time is subtracted from the output time. The result is divided by the scaling factor for the input net for this component. Then this value is added to the value of the offset for this component. The offset is set by the user and stored in the component-instance data structure and is non-zero when the user desires that two images arrive at a component in indirect correspondence. At block 862, the calculated delay is tested to see if it is negative. If it is negative, an error indicator is set at block 864. Control returns to the calling program at block 866.
If the test at block 854 indicated that the delay is known then, at block 868, the input time is calculated. This is done by multiplying the delay by the scaling factor and subtracting the result from the output time. At block 870, the component-instance data structure is checked to determine whether the input time has been previously defined. If it has, then, at block 872, the stored value is compared to the calculated value of input time. If the values are unequal, an error indicator is set at block 874. Control returns to the calling program at block 880.
If the input time has not been previously defined, then at blocks 882 and 884, for each input net, a test is made to determine whether this net is the from-net, and, if it is, it is ignored. Otherwise, at block 886, the time-scan-net function is called for this net, with the input time passed as one of the parameters. When all input nets have been scanned, control returns to the calling program at block 888.
Referring to FIG. 8C, the time-scan-net function 890 is illustrated. This function is called with pointers to a net-instance, a from-component, and a variable indicating the component input or output time as determined by the calling function. The from-component indicates the component from which this net was traced. At block 892, a test is made to determine whether the net time variable for this net has been previously defined. If it has, then a test is made at block 894 to determine whether the defined net time equals the input or output time passed from the calling function. If the times do not match then an error indicator is set at block 896. Control returns to the calling program at block 898.
If the net time is undefined, then, at block 900, the net time is set to the value of the time passed from the calling function. Then, at blocks 902 and 904, for each component driven by this net, a test is made to determine whether this component has already been visited and, if it has, it is ignored. If this component has not been visited, then at block 906, the function time-scan-comp-in is called with the net time passed as one of the parameters. Then, at blocks 908 and 910, for each component driving this net, a test is made to determine whether this component has been visited. If it has, it is ignored. If it has not been visited, then the function time-scan-comp-out is called at block 912 with the net time passed as one of the parameters. Control returns to the caller at block 914.
Referring to FIG. 8D, the function time-scan-comp-in 920 is illustrated. This function is called with pointers to a component-instance, a from-net, and, the net time passed from the calling function.
At block 922, a test is made to determine whether this component is disabled. If it is, control returns to the calling program with an error indicator at block 924. If the component is enabled, then at block 926 the component-instance structure is checked to determine whether the input time for this component has been defined. If it has, then, at block 928, the stored input time is compared to the net time passed to this function indicating the time on the input net. If these values do not match, then, at block 930, control returns to the calling program with an error indicator.
If the input time has not yet been defined, then, at block 932, it is set to the value of the net time passed to this function. Then at blocks 934 and 936, for each input net connected to this component, a test is made to determine whether this net is the from-net. If this net is not the from-net, then at block 938 the function time-scan-net is called for this net, with the input time passed as one of the parameters. Then, at block 940 a test is made to determine whether this is a destination component, and, if it is, control returns to the calling program at block 942. Otherwise, at blocks 944 and 946, for each output net connected to this component, the scaling factors are compared to verify that the scaling factors are equal at each net. If the scaling factors do not match, then control returns to the calling program at block 948 with an error indicator. At block 950, the component-instance data structure is checked to determine whether the delay variable is known. If the delay is currently unknown, then, at block 952, the component-instance structure is checked to see whether the output time for this component is known. If it is not known, then control returns to the calling program at block 954. If the output time is known, then the delay is calculated at block 956. This calculation is performed by subtracting the input time from the output time and dividing the result by the input net scaling factor for this component. If an offset for this component has been specified, then it is added to the delay. Then, at block 962, the delay is tested to see whether it is less than 0. If the delay is less than zero, then at block 964, an error indicator is set. At block 960 control returns to the calling program.
If the test at block 950 determines that the delay is already known for this component, then, at block 968, the output time is calculated. The output time is calculated by multiplying the component delay by the input net scaling factor for this component and adding the result to the input time. At block 970, the component-instance structure is checked to see whether an output time has been previously defined for this component. If it has, then, at block 972, it is compared to the value of the output time which was just calculated. If these values do not match, an error indicator is set at block 974. Control returns to the caller at block 976.
If the test at block 970 indicates that the output time was not previously defined, then, at blocks 978 and 980, for each output net connected to this component, a test is made to determine whether this component is the from-component. If it is not, then at block 982 the function time-scan-net is called for the output net, with the output time passed as one of the parameters. At block 984, when all nets have been scanned, control returns to the calling program.
When the timing analysis is completed, each net has the relative time from the time at which the group starts execution until the first virtual pixel will arrive at that net. The variable delays have been resolved, unless too many variable delay components have been included in the circuit, in which case the circuit is unconstrained and unresolvable. Any timing conflicts have generated a warning message and aborted the simulation.
After the timing analysis is successfully completed for a particular group of components, control returns to the start-group function and the actual simulation of that group is scheduled. The simulator maintains an event queue system to schedule future events. Two kinds of events are queued: simulation events and update events. A simulation event represents the start of processing of a single frame of data on a group of components forming a synchronous pipeline. An update event is scheduled after the completion of the simulation event and represents the end of processing for a single frame of data for the group of components.
When a group of components is scheduled for simulation, all of the precomputations for the group have been made and all of the components in the group have been marked active. The control program may now prepare and schedule some other group for simulation or it may relinquish control by calling a "wait" function. No actual simulation occurs until a wait function is called. When a wait function is called, simulated time is advanced up to the start time of the next scheduled event in the event queue and that event is executed. Events in the event queue are executed in their scheduled order until there are either no more events in the queue or a time specified by the simulation control program has been reached.
The simulator maintains a current simulated time variable. When an event in the event queue is executed, the simulated time variable is advanced to the start time for this event. If the event is a simulation event, the current simulated time variable is set to the time at which processing starts for this group, and the time variable is not advanced during the simulation of the group. However, the processing of an entire frame of data by each component in the group is simulated until the simulation of the behavior of the group is complete. The simulation thus extends into the future, at each component in the group, beyond the time represented by the simulated time variable. The simulator will not, however, simulate events occurring earlier than this time. The simulated time variable is used as a reference time for many analytical computations which are used to compute the details which would have been found by observing a more detailed and time-consuming simulation by a conventional technique, i.e., a technique wherein all events occurring in the system at the simulated time are simulated before any future events are simulated.
The execution of a simulation event for a scheduled group of components will now be described. Referring to FIG. 9, the simulate-group function 1000 is illustrated. This function is called with a pointer to a group list when the next scheduled event is a simulation event. At block 1002, a finish-time variable is initialized to the current simulated time. As each component is simulated this variable is adjusted to indicate the component's finishing time, if that time is later than the previously recorded time. Next, at blocks 1004 and 1006, the simulate-pipeline function is called for each of the source components in the group. This will result in the entire group of components being simulated, one pipeline at a time. The simulate group function will then, at block 1008, schedule an update event for the group at the finish time of the latest finishing component. Control returns to the caller at block 1010.
Details of the simulate-pipeline function 1020 are illustrated in FIG. 9A. This function is called with a pointer to a particular source component. At block 1022, a test is made to see whether the component is enabled. If the component is not enabled, the function returns control to the calling function at block 1024. Otherwise, at block 1026, the originate function is called for the specified source component, with a pointer to the component instance data structure for this component.
The originate function allocates an output buffer for this component and then calls the appropriate image processing library function to simulate the sourcing behavior of this component for an entire frame of data. The image processing library functions utilized in this embodiment are described in detail in Appendix B. A timing computation is performed to compute the time at which this component would finish. If this time is later than the previous latest finishing time then this time is recorded as the new latest finishing time for the group. Control is then returned to the simulate-pipeline function. At block 1028, the successor component order is computed, i.e. the order in which components connected to the output of this component should be simulated. Then, at blocks 1030 and 1032, the simulate-component function is called for each component in the successor component order. Control returns to the caller at block 1034.
FIG. 9B illustrates the simulate-component function 1040. This function is called with a pointer to a component-instance structure. At block 1042 a test is made to determine whether the component is enabled, and if it is not, control is returned to the caller at block 1044. Otherwise, the image function for this component is called at block 1046 with a pointer to the component instance data structure. The image function is similar to the originate function for source components. The image function locates the input image data for each input net to this component, using a pointer in the net-instance structure, and determines whether all of the input image buffers (if any) have been computed. Output buffers are allocated for this component and the appropriate image processing library function is called to simulate the performance of this component on an entire frame of data. The input image buffers may then be freed (if they are no longer required) and the output image buffers are linked to the output net so that they are available for subsequent components. Finally, the finishing time is computed and, if appropriate, the latest finish time is updated. Control then returns from the image function to the simulate-component function, where, at block 1048 a test is made to determine whether this is a destination component. If it is, control is returned to the calling program at block 1050. Otherwise, at block 1052, the successor component order for this component is computed and, at blocks 1054 and 1056, for each component in the successor order, the simulate-component function is called recursively. When all of the successor components connected to the output nets of this component have been followed to the destination components which delineate the extent of the group, control returns to the simulate-pipeline function, and eventually to the simulate-group function of FIG. 9. The process is repeated for each source component until each component in the group has been visited. An update event is then scheduled for this group.
As previously noted, when a particular group of components is simulated, the simulated time variable is not advanced beyond the start time for this group. However, events are simulated which extend into the future beyond that time, and the latest finishing time for the components in the group is computed. The next event to be simulated may be scheduled to start at a simulated time which is between the start time of the prior simulated event, and the computed finish time of that event. Care must be taken to ensure that, except as allowed by the component connections, the results of the simulation of a group are not made available to the rest of the system until simulated time catches up with the time at which the execution of the group of components on an entire frame of data finishes. The invention ensures this by distinguishing update events from simulation events. An update event is scheduled for the latest finish time for the group and is queued for execution at that time. The update event signals to all of the components in the group that they can make available any results to any other functions. It also clears the active flag so that components can again be rescheduled.
The execution of an update event is illustrated by FIGS. 10-l0B. The update-group function 1100 calls the update-pipeline function for each source component (blocks 1102 and 1104). The update-pipeline function 1130 calls the reschedule function associated with the source component at block 1132. The reschedule function may set flags or transfer data from temporary buffers to final buffers. At blocks 1134 and 1136 the update component function is called for each successor component. Control returns to the caller at block 1138.
Referring to FIG. l0C, the update-component function 1140 calls the update function associated with the particular component. The update function may transfer data from temporary buffers to final buffers (e.g. in a frame buffer component) and set flags indicating that the updated information may be accessed. The component is then marked inactive at block 1144. If this component is a final destination component (block 1146), then, at block 1148 control is returned to the calling program. Otherwise, at blocks 1150, 1152 and ll54, for each component in the successor order, the update-component function is recursively called. When all of the successor components connected to the output nets of this component have been followed to the destination components which delimit the group, control is returned to the update-pipeline function of FIG. l0A and eventua11y to the update-group function. The process is repeated for each source component until each component in the group has been visited.
The computation of the finish-time for each component will now be explained. The net times which were calculated by the timing analysis step represent the delay from the group start time to the time at which the first virtual pixel arrives at each net. There are three components to this delay: clock delay, line delay, and pixel delay. Each of these delays has been multiplied by the appropriate scaling factor, giving a vector which is a number of clock cycles of delay, scaled pixel cycles of delay, and scaled line cycles of delay. When a component is simulated, and the size of the output image is known, the number of lines and pixels in the image are used to evaluate the actual delay in terms of clock cycles. In this manner the delay until the first virtual pixel would arrive on each net is computed as each component is simulated. This delay, or relative time, is added to the start time for the group to give the absolute time at which the first virtual pixel arrives at each net. Knowing the size of the image, and the offset from the first virtual pixel to the first real pixel (which is propagated from component to component by the simulation function), the absolute time at which the first real pixel and last real pixel arrive at each net is calculated as follows:
First, a global "line-time" parameter for the group is calculated. This parameter is the time in clock cycles which the first source component takes to generate a line. The length of a line is added to the inter-line gap (the time needed for the source to retrace from the end of the line to the start of another). The result is multiplied by the pixel scaling factor for the source output, giving the number of clock cycles to clock one line along a net. This is the "line-time" for the group.
Secondly, the real start time is calculated for each component. The absolute time at which the first virtual pixel arrives at the input nets and the offset from the first virtual pixel to the first real pixel, in lines and pixels, have been calculated. The following equation gives the time at which the first real pixel arrives at the inputs: ##EQU1##
Thirdly, the finish time, or time at which the last real pixel is output by the component, is calculated using the size of the output image in lines and columns: ##EQU2##
As each component is simulated the latest finishing time is recorded. When the whole group has been simulated it is kgnown what the group finish time is and the update event is scheduled for this time.
The timing analysis techniques described herein are novel techniques which allow the simulator to check that each pipeline is correctly balanced and to assist the user to program variable delay components with the correct value for the default behavior or for an explicitly specified non-standard behavior. The timing data allows the simulator to partition the exchange of data between components and the user's application code in a manner consistent with the reality being simulated, and also allows the simulator to determine the actual performance of the simulated system, including the time it will take for the system to execute.
It has been shown that the simulation technique described herein utilizes internal memory buffers to hold data representative of entire frames of pixels. Images often occupy a relatively large amount of memory, so it is important that the simulator utilize techniques which minimize the number of buffers in use at a particular time. Although there is logically one image buffer associated with each interconnecting net in the simulated system, only those nets which have an image associated with them at any particular time have a real image buffer actually allocated. Furthermore, in some cases, the same region of physical memory in the computer can be shared and used as two image buffers at once.
Consider, for example, an image buffer serving as in input to some processing function, where this image buffer is not required for any subsequent processing function. Only the portion of this buffer containing pixel data which is still being accessed need be actually kept. If the same image processing function is generating an output image, then only that portion of the output buffer which has already had pixel data written into it need be allocated. In some cases the portions of the input and output buffer which must be valid do not overlap. In this case, the same buffer can be used for both the input and the output buffer. A flag in the component data structure indicates whether the function that simulates that component has the required property enabling buffer sharing. The image buffers associated with the interconnecting nets have a reference count variable. When the image buffer is first allocated, this variable is set to the number of functions which will need this image as an input. At each subsequent use of the image buffer, this reference count is decremented by one. Finally, the reference count is decremented to 0 which is the signal that the buffer is no longer is needed. The buffer is deallocated, allowing the freed memory to be reallocated for some other task.
Before each component is simulated, its shared buffer status flag is inspected to determine whether this component could share its input and output buffers as described above. If so, then the reference count for the input buffers are inspected and, if one is found which has a reference count of one, signifying that the buffer will not be required again, then that image buffer is made available as the component's output buffer. In this way the simulator avoids having to allocate unnecessary memory.
Another technique which affects the amount of memorY used by the simulator is the choice of simulation order, i.e., the successor component order referred to earlier in connection with FIG. 9A. When an interconnecting net is driven by one component and fans out to several, a choice must be made as to which of the possible successor components to simulate next. All of the choices at each pipeline are divided into three categories. In the first category are placed successor components which have no outputs and which do not store an image after they have been processed. In the second category are placed successor components which have no outputs, but which will retain an image as part of their state after execution of the pipeline. Execution of components in the second category is potentially more expensive than those in the first category. In the final category are placed all of the remaining components. These are the components which have outputs and which potentially involve many more buffers before processing is completed down their particular path. Having categorized each of the successor components, they are executed category by category, with the components within one category being executed in an arbitrary order. This system allows the user to specify that a particular component is to be placed in a particular category, to be executed before or after any other component. Various other categories may be identified and included in the alghorithm. Using this system the simulator thus selects an execution order which minimizes the number of buffers used to store intermediate images.
The preferred embodiment of the invention has now been described for purposes of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. For example the method of traversing the circuit may be varied from the particular method described. Similarly, the software simulation of the image processing behavior of some of the circuit components could be replaced by using the hardware components themselves as part of the simulator. It is intended that the scope of the invention be defined by the claims appended hereto. ##SPC1##
Claims
We claim:
1. A method for simulating on a computer an electronic digital circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output vector on each of said output nets in response to an input vector on each of said input nets according to a known processing behavior, said input vector and said output vector comprising an ordered set of data elements transmitted serially on a net, said method comprising: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid data elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of data elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding data elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output vector in response to at least one input vector according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; and (g) determining a component finish time for each component in the group to generate a latest component finish time.
2. The method of claim 1, further comprising the step of: calculating delay values for those components having a variable delay to ensure that all reference element input times are equal.
3. The method of claim 1 in which said circuit is a circuit for processing video image data and said data elements represent picture elements and said vectors represent frames of picture elements.
4. The method of claim 3 further comprising the steps of: receiving an input image from a camera; digitizing said image to produce a frame of picture element; and displaying on a monitor at least one group output vector as a frame of picture elements.
5. The method of claim 1 wherein the circuit comprises a plurality of synchronous groups of components, the method further comprising the steps of: repeating all of the steps of claim 1 for each group in the circuit; and reporting at least one of said group output vectors and a latest one of said finish times.
6. The method of claim 5 further including the step of passing a group output vector from a first group to a second group having a start time later than the latest component finish time generated for said first group.
7. An apparatus for simulating an electronic circuit for processing visual image data, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, the apparatus comprising: a camera; a frame buffer card coupled to said camera; a computer workstation coupled to said frame buffer card for reading and writing to said frame buffer; a monitor coupled to said frame buffer; said workstation being programmed to simulate the circuit in response to an image from said camera, and to cause an output image to be written to said frame buffer and displayed on said monitor, said program comprising: means for: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets; (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that corresponding picture elements will arrive together at components having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group having at least one input net and at least one output net, to generate at least one group output frame; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism, to generate a circuit output frame; and (i) writing the circuit output frame to said frame buffer card for display on said monitor.
8. The apparatus of claim 7, wherein said workstation is further programmed for calculating delay values for those components having variable delays to ensure that all reference element input times are equal at those components having a plurality of inputs.
9. A method for simulating on a computer an electronic digital visual image processing circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, said method comprising: (a) defining a first group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding picture elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism to generate a circuit output frame and a circuit finish time; and (i) storing the circuit output frame.
10. The method of claim 9 further comprising the steps of: displaying the stored circuit output frame; and reporting a circuit finish time.
11. The method of claim 9 further comprising the step of: calculating delay values for those components having variable delays to ensure that all reference element input times are equal at those components having a plurality of inputs.
12. The method of claim 9 wherein the scaling factors calculated by said calculating step comprise a line rate scaling factor and a picture element rate scaling factor.
13. The method of claim 9 wherein there is a largest frame in a group and the largest frame has a first picture element and the reference element input time is a relative time at which a first virtual picture element arrives at an input net, the first virtual picture element being the first picture element in the largest frame in the group.