Method of Coding Digital Information Organized in Frames Using a CMI Code, a Device for Implementing This Method and Application to Servitude Information for a High Capacity Digital Network

The present invention relates to coding information using a CMI code and more particularly the coding of multiplexed digital information organized for example in frames.

The CMI code is well known. Such a code for example is described in the notice G 703 pages 55 to 57 of the CCITT such as reshaped in Geneva in 1980. The CMI code is a two level code without zero return of the signal. A binary 0 at the input is coded into a signal with level A.sub.1 and A.sub.2 (respectively low level and high level) in each half period (time T/2). A binary "1" at the input is coded into a signal of level A.sub.1 or A.sub.2 over a period, this level alternating for successive binary "1"s. The CMI code may be expressed more simply by saying that a binary "1" is coded 00 and 11 alternately and a binary "0" is coded 01.

However, when the binary train of information results from the multiplexing of a plurality of signals organized in frames, for recognizing these signals it is necessary to provide a frame locking word. Now, the insertion of such a word may disturb the statistics of the code itself.

The present invention aims at overcoming this drawback. For this, it provides first of all a method for coding digital information in the CMI code, in which said information is organized in frames, each comprising a position for a frame locking word V, in which method the binary element 1 is chosen for said word V, the CMI code is violated at the position of said word V and immediately before said word V is inserted a binary filling element B, said binary element B being chosen so that the statistics of the coding law are kept as a whole.

The invention proposes using as frame locking word a binary "1" placed at the end of a frame. This binary element V would then be coded in the CMI code 11 or 00. In order to recognize it, the CMI code is violated at the position of the frame locking word V by coding it 00 if it should be coded 11, or 11 if it should be coded 00.

However, coding of this word B does not take into account the useful information contained in the frame and the invention proposes, for respecting the statistics of the CMI coding law, to use the last but one binary element B of the frame, for filling each frame.

Advantageously, for keeping the statistics of the coding law as a whole, violation is chosen at the position of said word V alternately equal to 11 and 00, from one frame to the next, and said binary element B is chosen:

equal to 0 in the binary system if the number of "1"s of useful information of the frame before introduction of said binary elements B and V is uneven,

equal to 1 in the binary system if said number is even.

In fact, the mean energy level of the signal may be disturbed if the statistics of the CMI code are not respected, that is to say if the number of binary "1"s coded 11 is different from the number of binary "1"s coded 00. In so far as the binary Os are concerned, this problem does not exist because they are coded 01 in the CMI code.

The method of the invention for respecting the statistics of the coding law consists then essentially in searching in each frame for the parity of the number "1" and in coding the binary element "B", so that, when the number of binary "1"s before filling is even, the binary element B is coded identically to the frame locking binary element and when the number of binary "1"s before filling is uneven, the binary element is coded 01.

The invention also provides a particularly simple and efficient device for implementing the above method.

For this, it provides a device having means for coding, in the CMI code, a binary signal organized in frames each having a position for a frame locking word V, in which device:

said coding means are adapted so as to violate the CMI code at the position of said locking word V chosen equal to 1,

means are provided for inserting, immediately before said word V, a binary filling element B and

means are provided, responsive to the useful information contained in the frame for determining the value of said binary element B so that the statistics of the coding law are kept as a whole.

Advantageously:

means are provided for keeping the value of said binary signal at zero at the position of said word V,

said coding means are adapted for inserting at the position of said word V, a violation alternatively equal to 11 and 00, from one frame to the next,

said means for determining the value of said binary element B are adapted so that:

B=0 in the binary system if the number of "1"s of useful information of the frame before introduction of said binary elements B and V is uneven,

B=1 in the binary system if said number is even.

Advantageously again:

said determination means include:

means for detecting the parity of said number,

an exclusive OR gate receiving the output signal from said detection means and a signal representative of the coding of said violation,

the output of said exclusive OR gate delivering a signal representative of the value of the binary element B.

The method of the invention applies in particular to the coding of servitude information such as monitoring, signalling, order channels, alarms, remote monitoring of high capacity digital transmission network, said information being multiplexed in frames.

This digital servitude channel, coded in accordance with the method of the invention, may then be applied in line in a way known per se for modulating a laser, for example.

Other features and advantages of the invention will be clear from reading the following description illustrated by the drawings, in which:

FIG. 1 is a diagram of the device for coding multiplexed information in the CMI code in a frame of 32 binary elements, and

FIG. 2 shows a diagram of the timing of the signals available at the output of the elements of the device of FIG. 1.

In the following description will be described the case of a frame of 32 binary elements, but the invention would similarly apply to a frame comprising any number of binary elements.

The method of coding in the CMI code of the invention consists, on the one hand, in choosing for frame locking word the last binary element of the binary frame and, on the other hand, in adopting a binary "1" for this framelocking word V. In addition, this frame locking word V is violated in its coding in the CMI code, that is to say that if it should, because of the last binary "1" of the frame, be coded 11 and not 00, it will not be coded in accordance with the CMI code as 11 but 00 and reciprocally. The method of coding the frame locking word V must further be adapted to the frame structure of the multiplexed information and, for the statistics of the CMI code, the coding of these violations should be alternated at each frame.

To fulfill all these requirements which are apparently difficult to make compatible, in accordance with the invention, in each frame, the last but one binary element B is used for on the one hand, fulfilling all these requirements relating to the frame locking word V and, on the other hand, for respecting the statistics of the CMI coding law. This binary element B is then a simple binary filling element and its coding depends then, on the one hand, on that of the frame locking word V which is imposed by that of the preceding frame and, on the other hand, on the useful information contained in the frame.

This binary filling word B may then, depending on the case, be coded, using the CMI code, 01, 11 or 00 depending on the needs. If, in the binary frame, the number of "1"s before filling is even, then the same value, in the CMI code, is adopted for B as for the frame locking word V.

On the other hand, if the number of "1"s in the binary frame before filling is uneven, the value 01, in the CMI code, is adopted for B.

The following frame examples illustrate the choice of the filling bit B.sub.2 as a function of the frame locking word V.sub.2 and of the useful contents of the frame, this word V.sub.2 itself depending on the word V.sub.1 of the preceding frame.

It will be noted that, each time, V.sub.2 is opposed to V.sub.1. In example 1, B.sub.2 is chosen equal to 00 for the number of binary "1"s is even therefore B.sub.2 =V.sub.2. In example 2, B.sub.2 is chosen equal to 01 for the number of binary "1"s in the frame is equal to three, therefore uneven. In example 3, the number of binary "1"s is equal to 2, therefore even and B.sub.2 is coded equal to V.sub.2. In example 4, the number of binary "1"s is equal to three, therefore uneven so B.sub.2 is equal to 01. Only the binary "1"s have been shown and it has been assumed that the other binary information elements of the frame were binary "0"s, therefore coded 01 in the CMI code, so without any effect on the statistics.

Referring to FIG. 1, a multiplexer 1 receives the digital information x.sub.0,x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7 in parallel. This information may for example be service information and has been previously coded in binary code. It may for example be a question of remote monitoring information, signalling, supervision information, order and alarm channels in a high capacity digital transmission network, comprising for example a laser emitter. This multiplexer 1 outputs information in series, at a suitable rate. The clock signal H, here of a frequency 128 Khz, is for example derived from a local oscillator 2, here of a frequency of 2.048 Mhz, through the divider circuit 3. Signal H is derived from H through the inverter I. The divider circuit 3 receives then the signal of frequency 2.048 Mhz and delivers at the outputs Q.sub.5,Q.sub.6,Q.sub.7,Q.sub.8,Q.sub.9, and Q.sub.10 the signals S.sub.1,S.sub.2,S.sub.3,S.sub.4,S.sub.5, and S.sub.12, respectively, derived from the input signal by dividing by 32, 64, 128, 256, 512 and 1024 respectively. The signals S.sub.1 and S.sub.4 are applied to the input of the AND gate P.sub.1 so as to form a signal S.sub.6 which is applied to the control input A.sub.1, of lowest rank, of the multiplexer 1. The signals S.sub.2 and S.sub.4 are applied to the input of an AND gate P.sub.2 which outputs a signal S.sub.7 to the control input B.sub.1, of the next rank, of multiplexer 1. Signals S.sub.4 and S.sub.3 are applied to the input of an AND gate P.sub.3 so as to form the signal S.sub.8 which is applied to the control input C.sub.1, of the highest rank, of multiplexer 1. These different signals are shown in the timing diagram of FIG. 2. The multiplexer 1 may for example be a CMOS 4512 produced by Motorola. An inhibition signal S.sub.9 is also applied to the inhibit input of this multiplexer 1. The use of this signal S.sub.9 is related to the insertion of the locking bit V at the end of each frame as will be explained subsequently. This signal S.sub.9 is for example generated by an OR gate P.sub.4 which receives at its inputs the signals S.sub.1, S.sub.2, S.sub.3, S.sub.4 delivered by the divider circuit 3. This signal S.sub.9 is a signal locating the position V of locking at the end of each frame, and in the particular example described, the sixteenth bit of each frame. It allows the state of the signal S.sub.10 to be kept at 0 at the output of the multiplexer 1 at these locking positions V and here at the positions of the sixteenth bit of each frame.

This signal S.sub.10 is applied simultaneously to the inputs J and K of a flip flop JK operating at the timing H. This flip flop JK is insensitive to the binary "0"s applied at the input and only takes into account the binary "1"s, which each cause the change of its output signal S.sub.11.

We may then say that the flip flop JK detects the parity of the numbers of the "1"s of the useful information of the frame before introduction of the binary elements B and V. This signal S.sub.11 is applied, on the one hand, to the input of a type D flip flop 5 and, on the other hand, to the input of an exclusive OR gate P.sub.5. This gate P.sub.5 also receives the signal S.sub.12. In fact, the signal S.sub.12 is a parity signal of the violation of the frame locking word V which changes state at each frame. The signal S.sub.11 is a signal recording the binarY "1"s of the useful information signal (frame locking bit V excluded since the inhibit signal S.sub.9 causes resetting of the signal S.sub.10 at this position). Thus, at the output of gate P.sub.5, the signal S.sub.13 contains, at the position of the filling bit B, its binary value 0 or 1, depending on the parity of the number of 1s indicated by the signal S.sub.11. It is therefore easy, as in the particular case of FIG. 1, to multiplex it previously with certain useful information, but it could also be applied directly to the input of the multiplexer 1.

Thus, as shown in FIG. 1, a multiplexer 8 here receives at four inputs information Sig 1, Sig 2, Sig 3, the nature of which will be discussed subsequently, and the filling bit B, so as to deliver at two outputs the data x.sub.3 and x.sub.7 to the input of the multiplexer. This multiplexer 8 is controlled by the signal S.sub.5 from the divider circuit 3.

As was mentioned above, the binary signal S.sub.11 at the output of the JK type flip flop 4 is applied to the input of type D flip flop 5, operating at the timing of clock H, whose essential function is to deliver a signal S.sub.14 identical to signal S.sub.11, but phase locked with the clock signal H. The binary signal S.sub.10 is also applied to the input of a type D flip flop 6 so as to be there locked also with the clock H which gives the signal S.sub.15. It can be seen that this signal S.sub.15 is as a whole identical to the binary signal S.sub.10, except for the filling bit B, which is inserted therein in true size whereas the bit B is only present for a half clock cycle on the signal S.sub.10, because of the delay in the JK flip flop 4.

Finally, coding of the binary signal properly speaking is provided, according to the invention, by means of CMI coding circuit 7.

This circuit 7 is here a multiplexer, for example CMOS of type 4512 produced by Motorola. It receives at its inputs x'.sub.0 and x'.sub.1 clock signal H and the signal S.sub.14, respectively and, at its combined inputs x'.sub.2 and x'.sub.3, the signal S.sub.12.

The control signals for this multiplexer 7 are: at the control input A.sub.2, of lowest rank, the signal S.sub.15 and, on the control input B.sub.2, of the next rank, a signal S.sub.16 determining the position of the frame locking bit V, the control input C.sub.2 of highest rank applied to zero. The signal S.sub.16 is here derived from the signal S.sub.9 by applying the signal S.sub.9 to the input of an AND gate P.sub.6 which also receives the signal S.sub.5 obtained by means of an inverter, not shown, from the signal S.sub.5.

The output of gate P.sub.6 is connected to the D input of a flip flop 9 after inversion of the signal in an inverter I. Flip flop 9 is clocked by the clock signal H and outputs the signal S.sub.16. From the truth table of multiplexer 7 it may be deduced that x'.sub.0 codes the binary "0"s by recopying the clock signal H whereas as x'.sub.1 codes the binary "1"s. The inputs x'.sub.2 and x'.sub.3 code the locking bit V. At the output, the signal S.sub.17 is obtained containing information organized in frames and coded in the CMI code in accordance with the invention.

It will be noted that, in the example shown in FIG. 1, the information applied to the inputs x.sub.1 to x.sub.7 of multiplexer 1 are partially premultiplexed, for example by means of the multiplexer 8. In fact, when it is a question for example of servitude information, formed for example by order, signalling, supervision, remote monitoring, alarm channels, etc . . . , the flow rates of each of these channels are unequal and a frame is organized as a function of the amount of information required for each service. If for example the overall flow of servitude information is fixed at 128 kbit/s, as in the example of the description, it is sufficient to divide the useful binary elements between the different servitudes. Thus we may attribute, in the example of the invention:

64 kbit/s for the omnibus audio channel (input x.sub.0)

8 kbit/s for the remote monitoring channel (input x.sub.4)

16 kbit/s for the order channel for the sake of security (inputs x.sub.1 and x.sub.5 connected together)

16 kbit/s for the supervision channel (inputs x.sub.2 and x.sub.6 connected together)

In the particular case which has just been described considering the fact that the signal S.sub.9 is at level 1 at the position of the sixteenth bit of the frame, the signal S.sub.10 is necessarily at zero during this sixteenth bit, which could be used for upstream fault signalling, for example. The insertion of such signalling downstream of multiplexer 1, not shown for the sake of simplicity, is within the scope of a man skilled in the art. Naturally, a high level signal could be produced and applied, to the inhibition input of multiplexer 1, only during the locking word V, and the upstream fault signalling could then be inserted at input x.sub.0, at the time of the sixteenth bit of the frame.

With such multiplexing, using the CMI coding of the invention, a frame may be obtained having 32 binary elements for servitude channels of a high capacity transmission network.

Such a frame structure may obviously be modified for adapting it to the number of channels to be multiplexed, to the in line flow rate, and a frame may be obtained having any number of binary elements.

The choice of the 128 kbit/s rate has a quite particular interest for the servitude channel. In fact, as mentioned in the French patent No. 2 526 554 of the applicant, such a digital signal may serve for frequency overmodulating a laser emitter. This 128 kbit/s rate is certainly a constraint for this very particular application of forming a frame for digital information coded in the CMI code.