Transistor Driving Circuit and Circuit Controlling Method

This invention relates to a transistor driving circuit, especially a transistor driving circuit for such application as a CRT display, a television receiver or a switching power supply, and a method for controlling the circuit.

In the prior art, transistor driving circuits have some problems with various characteristics: for example, it is not possible to adequately shorten their fall times, that is, the duration indicating their switching speeds. In substance, transistor driving circuits having a sufficiently high speed ability were not previously available for switching, especially transistor driving circuits for high definition CRT displays.

It is an object of the present invention to provide an improved transistor driving circuit.

It is also an object to provide a method for controlling a transistor driving circuit having an ability for high speed switching.

It is another object to provide a transistor driving circuit in which the variation in fall time of an output transistor due to a rise in temperature is reduced and the fall time is constantly held at a minimum, so that there is little possibility of a thermal

In order to achieve the above objects, in the present invention, a storage period or a carrier storage time of an output transistor in a driving circuit is detected, and in response to an increase or a decrease in the storage period, one of the signals supplied to a primary coil of a transformer of a driving circuit is controlled in order to continuously hold the storage period at a minimum value. This may be achieved by either controlling the driving pulse by regulating a characteristic of the driving pulse, especially the pulse width, or by controlling the driving supply voltage used.

The present invention is based on a discovery by the present inventors that there is a point at which both the storage period and the decreasing duration become minimum values as the driving pulse width or the driving supply voltage supplied to the primary coil are varied.

Therefore, it is possible to hold the fall time at the minimum value by detecting the storage period t.sub.stg and controlling one of the signals supplied to the primary coil to keep the storage period t.sub.stg at the minimum value t.sub.sm. As a result, in this invention, it becomes possible to suppress the generation of energy losses during the fall time and prevent thermal runaway.

FIG. 1 shows a circuit diagram of a transistor driving circuit in the prior art;

FIGS. 2a to 2e illustrate waveforms of voltages or currents at indications a to e in FIG. 1;

FIGS. 3a to 3t illustrate waveforms of voltages or currents for explaining a method of solving one of the problems in the circuit shown in FIG. 1;

FIG. 4 shows a graph for explaining a principle of the present invention;

FIG. 5 illustrates a circuit diagram of an embodiment of the present invention;

FIG. 6 shows a detailed circuit diagram of the block 16 shown in FIG. 5;

FIG. 7 shows a detailed circuit diagram of the block 22 shown in FIG. 5;

FIG. 8 shows a detailed circuit diagram of the blocks 17, 18 and 19 shown in FIG. 5;

FIGS. 9A to 9L illustrate waveforms of voltages or currents at indications A to L in FIG. 5;

FIG. 10 shows a circuit diagram of a voltage controlled monostable multivibrator used in FIG. 5;

FIG. 11 illustrates an output characteristic of the circuit shown in FIG. 10; and

FIG. 12 shows a circuit diagram of another embodiment of the present invention.

An example of the transistor driving circuit in the prior art is explained by using FIGS. 1 and 2, hereinafter. FIG. 1 shows a circuit diagram of a circuit for driving a horizontal deflection output circuit in an appliance such as a television receiver or a display. FIGS. 2a to 2e illustrate waveforms of voltages or currents at indications a to e in FIG. 1.

FIGS. 2a and 2b depict a voltage waveform of a horizontal oscillating pulse supplied to a base of a driving transistor 1 and a voltage waveform of a collector of the driving transistor 1, respectively. FIGS. 2c, 2d and 2e show waveforms of a current flowing in a base of an output transistor 5, a collector voltage and a collector current I.sub.c of the transistor 5, respectively. In FIGS. 2c and 2e, the currents flowing in the directions shown in FIG. 1 are positive. Referring to FIG. 1, the driving transistor 1 and the output transistor 5 act as switches. The output transistor 5 is driven to an OFF state at a time t.sub.o, so that remaining carriers which accumulated in a base region start to recombine and the collector current I.sub.c shown in FIG. 2e starts to decrease at a time t.sub.1. In a transition duration from the time t.sub.1 to a time in which the collector current I.sub.c becomes zero, the collector voltage rises as shown in FIG. 2d and a large energy loss is generated.

Now, assuming that I.sub.cp indicates the maximum collector current during an ON state of the output transistor 5, a decreasing duration or fall time t.sub.f, that is, a duration from a time in which the collector current is 0.9 I.sub.cp to a time in which the collector current becomes 0.1 I.sub.cp, is used for indicating a switching speed. Under a charge control model, the fall time t.sub.f is expressed by the following formula, ##EQU1## where V.sub.CB is a variation of the base voltage, C.sub.ob is a collector junction capacity, h.sub.FE is a current gain in a large amplitude operation and I.sub.B2 is a maximum value of a reverse base current. As apparent from formula (1), the decreasing duration t.sub.f becomes smaller when the absolute value of I.sub.B2 becomes larger. Further, a forward base current I.sub.B1 is proportional to the product I.sub.cp .times.h.sub.FE. When setting a large current ratio I.sub.B2 /I.sub.B1 of the driving circuit, a polarity of a transformer 4 is selected so that the output transistor 5 switches to the OFF state during the ON state of the driving transistor 1. That is, it is possible for a large current to flow from a condenser 2, as an energy storage means just after the driving transistor 1 switches to the ON state at t.sub.o. The condenser 2 is connectable to either terminal of a primary coil of the transformer 4. Further, at the secondary side of the transformer 4, a base-emitter voltage V.sub.BE of the output transistor 5 has a reverse polarity to the electromotive force of the transformer 4 during the ON state of the output transistor 5. In contrast, the base-emitter voltage V.sub.BE due to a carrier storage effect has the same polarity to the electromotive force of the transformer 4 during the OFF state of the output transistor 5. Accordingly, a peak value of the reverse base current I.sub.B2 shown in FIG. 2C becomes larger than a peak value of the forward base current I.sub.B1. In general, it is possible to set the current ratio I.sub.B2 /I.sub.B1 at about 1.2 to 1.4. However, it is not possible to shorten the fall time t.sub.f adequately.

On the other hand, a horizontal deflection frequency f.sub.H in prior art circuits has become higher in response to development of displays having higher definition. Since the loss during the fall time of the collector current of the output transistor 5 is in proportion to the cube of the frequency f.sub.H, the loss increases sharply in response to the rise of the frequency f.sub.H. This is a first problem recognized by the present inventors. Further, even if the frequency f.sub.H is set so that the loss is acceptable in a normal temperature operation, there is a possibility that a thermal runaway will occur, that is, the temperature rises due to some reason, the fall time increases, the loss increases and finally the transistor 5 breaks down. This is a second problem recognized by the present inventors.

The present inventors have suggested some changes of circuit parameters so that the magnetic flux density of the transformer 4 could be set to not saturate during a charge period of the output transistor 5, and to saturate during a charge period of the transformer 4, and the magnetic flux density, of the transformer 4 is kept at nearly a residual magnetic flux density, when the output transistor 5 is driven to the OFF state.

FIGS. 3a to 3f illustrate waveforms of voltages or currents at indications a to e in FIG. 1, with transformer 4 designed for the above condition. FIGS. 3a, 3b, 3c, 3d and 3f correspond to FIGS. 2a, 2b, 2c, 2d and 2e respectively. FIG. 3e shows a variation of the magnetic flux density of the transformer 4. Referring to FIG. 3e, B.sub.m denotes a saturated magnetic flux density and B.sub.r designates the residual magnetic flux density. When the transistor 1 switches to the ON state, the current flows through the primary coil of the transformer 4 and the magnetic energy is stored in the transformer 4. Therefore, the magnetic flux density of the transformer 4 rises in proportion to the time, and reaches the saturated magnetic flux density B.sub.m at a time t.sub.4, at which the transistor 1 turns off. After the time t.sub.4, the magnetic energy accumulated in the transformer 4 is spent as the forward base current of the transistor 5 shown in FIG. 3C. At a time t.sub.5, when the transistor 1 turns on again, the magnetic flux density of the transformer 4 has decreased to the residual magnetic flux level B.sub.r. Here, the base current of the output transistor 5 decreases linearly from the time t.sub.4 to the time t.sub.5 and becomes almost zero at the time t.sub.5, because the magnetic energy accumulated in the transformer 4 is small and is consumed at the output transistor 5. By selecting such a characteristic as the one of the transformer 4, it will become possible to shorten the fall time of the output transistor 5 and to reduce the loss at the normal temperature. Accordingly, it will be possible to resolve the first problem at the normal temperature.

However, in the case of the temperature of the output transistor rising due to some reason other than a rise of the horizontal deflection frequency f.sub.H, such as a rise in ambient temperature, there is a high possibility that thermal runaway will occur, even if the frequency f.sub.H is low. Therefore, the second problem will be not resolved by the above method.

FIG. 4 shows a characteristic of the storage period t.sub.stg and the decreasing duration t.sub.f in the case where the pulse width W.sub.P of the driving pulse of the output transistor or the driving supply voltage E.sub.o is increased. A curve A indicates the fall time t.sub.f and a curve B indicates the storage period t.sub.stg. Here, a scale for the storage period t.sub.stg is about one figure larger than the one for the storage period t.sub.f. By increasing the pulse width W.sub.P or the driving supply voltage E.sub.o, the fall time t.sub.f and the storage period t.sub.stg decrease and begin to increase at a pulse width W.sub.m or a driving supply voltage E.sub.o, respectively. As is apparent from FIG. 4, the pulse width and the driving supply voltage for a minimum value t.sub.sm coincides with one for a minimum value of the fall time.

Preferred embodiments of the present invention will be explained referring to the drawings. FIG. 5 shows a block diagram of the first embodiment. The blocks 13, 16, 22 and 23 shown in FIG. 5 are drawn in detail in FIGS. 6, 7, 8 and 10. Referring to FIG. 5, the numeral 20 denotes the same driving circuit as shown in FIG. 1. In this embodiment, a transistor driving circuit is constructed by the driving circuit 20, a detecting circuit 21 for detecting a storage period of the output transistor 5, a judgment circuit 22 for judging the occurrence of an increase or a decrease of the storage period detected by the detecting circuit 21, an adjusting circuit 23 for adjusting a pulse width of a pulse signal which is supplied to the base of the transistor 1 of the driving circuit 20, an AFC circuit (automatic frequency control circuit) 11, and a trigger circuit 12, for example, a voltage controlled oscillator (hereinafter, VCO). AFC circuit 11 and the trigger circuit 12 may be the same circuits as used in a conventional television or conventional display. Therefore, detailed descriptions for them are omitted. A horizontal deflection signal (H sync) is supplied to the AFC circuit 11 and an output signal of the driving circuit 20 is fed back to the AFC circuit 11 via a transformer 10.

The detecting circuit 21 comprises two waveform shapers 14 and 15 and a storage period detector 16. The waveform shaper 14 receives the collector voltage of the transistor 1, and the waveform shaper 15 receives the output signal of the driving circuit 20 via transformer 10. The storage period detector 16 detects the storage period of the output transistor 5 by detecting a difference between an output signal of waveform shaper 14 and an output signal of waveform shaper 15. The output signal of the detector 16 is provided to the judgment circuit 22.

The adjusting circuit 23 includes a control pulse generator 19, a pulse generator 17, a low pass filter (hereinafter, LPF) 18 and a voltage controlled monostable multivibrator (hereinafter, VCMM) 13. The control pulse generator 19 generates a control pulse corresponding to a pulse width being varied in a control time. The pulse generator 17 generates output pulses, a number of which correspond to an output signal of judgment circuit 22. The LPF 18 integrates the output pulses of the pulse generator 17 and supplies the VCMM 13 with a control voltage. The VCMM 13 is triggered by the output signal of the trigger circuit 12 and generates a pulse signal, the pulse width of which corresponds to the control voltage from the LPF 18.

The operation of this embodiment will be explained referring to signal waveforms shown in FIGS. 9A to 9L. The waveforms of the collector voltage of the driving transistor 1 and the output signal of the driving circuit 20 are shown in FIGS. 9A to 9B, respectively. These signals are provided to the waveform shapers 14 and 15 and become signal waveforms shown in FIGS. 9C and 9D, respectively. The storage period detector 16 compares the output signal shown in FIG. 9C with the output signal shown in FIG. 9D and generates a storage period pulse shown in FIG. 9E. The storage period pulse corresponds to the carrier storage time of the output transistor 5 as shown in FIG. 3C.

The judgment circuit 22 compares the pulse width of the storage period pulse in this control time with the pulse width of the storage period pulse in a former control time, which represents the last occurring control time; in the case of increasing pulse width, the circuit 22 outputs a high level signal "H". In the case of decreasing pulse width, it outputs a low level signal "L". FIG. 9I shows a waveform of the output signal of the judgment circuit 22, which has a high level. In the judgment circuit 22, the pulse widths are converted to voltages and the voltages are compared to each other.

The output signal of the judgment circuit 22 is supplied to the pulse generator 17. In response to the output signal of the judgment circuit 22, the pulse generator 17 generates an output signal which is made by adding or subtracting the control pulse to or from a basic pulse signal having a predetermined frequency. Namely, the pulse generator 17 holds the output signal of the judgment circuit 22 in the former time or another signal indicating whether the control pulse is added or subtracted and determines whether the control pulse should be added or subtracted in the present control time according to Table 1. Both the pulse generator 17 and the control pulse generator 19 provide the pulse signals in synchronization with the output pulse of the waveform shaper 15.

The output signal of the pulse generator 17 is integrated and converted to the control voltage by the LPF 18. The VCMM 13 receives the horizontal deflection signal processed by the AFC circuit 11 and the trigger circuit 12 and the output signal of the LPF 18. The VCMM 13 is triggered by the output signal of the trigger circuit 12, generates the output signal having the pulse width corresponding to the voltage level of the output signal of the LPF 18 from a leading edge point of the trigger signal and supplies the base of the transistor 1 with it. The VCMM 13 is constructed so that the pulse width of the output pulse becomes narrower when the output voltage of the pulse generator 17 increases and it becomes broader when the output voltage decreases.

Next, the operation of the pulse generator 17 will be explained by referring to Table 1.

An example, in which the output signal of the judgment circuit 22 indicates "H", will be mentioned concerning Table 1.

(1) When the control pulse is added during the former control time in the pulse generator 17, the minimum value t.sub.sm shown in FIG. 4 exists in the direction for decreasing the pulse width W.sub.p. Therefore, the control pulse is added to the basic pulse signal in the pulse generator 17, so that the pulse width of the output pulse of the VCCM 13 decreases.

(2) When the control pulse is subtracted during the former control time, the minimum value t.sub.sm exists in the direction for increasing the pulse width W.sub.p. Therefore, the control pulse is subtracted, so that the pulse width increases.

Further, another example, in which the output signal of the judgment circuit 22 indicates "L", will be explained. In this case, the minimum value t.sub.sm exists in the reverse direction to an increase or a decrease of the pulse width W.sub.P in the former control time. Accordingly, an addition or a subtraction operation opposite to one executed in the former control time is done in the present control time.

In this way, the storage period t.sub.tg is held nearly at the minimum value t.sub.sm, that is, a value on which the output signal of the judgment circuit 22 alternatively changes between "H" and "L".

As a result, the decreasing duration t.sub.f is constantly held on a minimum value at the same pulse width as the storage period t.sub.stg.

Referring to FIGS. 6 to 11, an embodiment of each circuit element will be explained. FIG. 6 shows an example of the storage period detector 16. The detector 16 includes a D-type flip-flop (hereinafter, DFF) 161 and an invertor 162 connected to a set terminal C.sub.p of the DFF 161. The inpout terminal of the inverteor 162 is connected to the output terminal of the waveform shaper 14 and supplied with the pulse shown in FIG. 9C. The rest terminal R of the DFF 161 is connected to the output terminal of the waveform shaper 15 and supplied with the pulse shown in FIG. 9D. The output signal of the DFF 161 is supplied to the judgment circuit 22. The DFF 161 is set by the trailing edge of the pulse shown in FIG. 9C, reset by the leading edge of the pulse shown in FIG. 9D and provides the output pulse indicating the storage period shown in FIG. 9E.

FIG. 7 shows an example of the judgment circuit 22. The judgment circuit 22 includes a DFF 221, a wave generator 222, sample hold circuits (hereinafter SH circuits) 223 and 224, AND gates 225 and 226, a comparator 227 and an exclusive OR 228. The DFF 221 operates as a divider for generating a driving pulse. The wave generator 222 generates an output signal shown in FIG. 9G by using the pulse shown in FIG. 9C from the wave shaper 14. The wave generator 222 is constructed with transistors 71 and 72, resistors 73, 74, 75 and 76 and a condenser 77.

Now, presume that "L" state periods of the driving pulse shown in FIG. 9F correspond to even periods n, and "H" state periods thereof correspond to odd periods n+1. The output signal of the AND gate 225 becomes "L" at the periods n and "H" at the periods n+1. On the other hand, the output signal of the AND gate 226 becomes "H" at the periods n and "L" at the periods n+1. The SH circuits 223 and 224 alternately receive the voltage signal shown in FIG. 9G from the wave generator 222. The SH circuit 224 holds the voltage signal V.sub.stn corresponding to the storage period t.sub.stn during the periods n, in response to the output signal of the AND gate 226. The SH circuit 223 holds the voltage signal V.sub.stn+1 corresponding to the storage period t.sub.stn+1 during the periods n+1, in response to the output signal of the AND gate 225. The storage periods t.sub.stn and t.sub.stn+1 held in the SH circuits 223 and 224 as a voltage amplitude are compared in the comparator 227 and the exclusive OR 228 in order to decide whether the storage period should be increased or decreased.

During the even periods n, the output signal of the AND gate 225 is always "L", because the "L" state signal is supplied to the input terminal 2 of the AND gate 225, as shown in FIG. 9F. Therefore, during the periods n, the SH circuit 223 does not operate. On the contrary, during the even periods n, as a terminal Q of the DFF 221 is connected to the input terminal 2 of the AND gate 226, the "H" state signal is always supplied to the input terminal 2 of the AND gate 226. The input terminal 1 of gate 226 receives the output signal of the storage period detector 16 shown in FIG. 9E. Therefore, the AND gate 226 provides the same signal as the storage period pulse and the SH circuit 224 holds the signal shown in FIG. 9G at the trailing edge of the storage period pulse. Here, the input signal to the SH circuit 224 is a voltage of the condenser 77 in the wave generator 222. As the transistor 71 becomes an OFF state at the leading edge of the storage period and charges stored in the condenser 77 are consumed by a constant current circuit constructed by the resistors 74, 75 and 76 and the transistor 72, the voltage decreases linearly as shown in FIG. 9G. The output signal of the AND gate 226 becomes "L" at the trailing edge of the storage period pulse. Therefore, the voltage V.sub.stn is held by the SH circuit 224.

Next, the operation during the odd periods n+1 will be explained. The output signal Q of the DFF indicates "H" and the output signal Q is "L". Therefore, the AND gate 226 always provides an "L" level signal and the SH circuit 224 does not sample the output signal of the wave generator 222 during the odd periods n+1. On the contrary, the AND gate 225 provides the same signal as the storage period pulse. The SH circuit 223 holds the input signal shown in FIG. 9G in the same manner as the SH circuit 224 during the even periods n. A sampled voltage is the voltage V.sub.stn+1 shown in FIG. 9G.

Further, the operations of the comparator 227 and the exclusive OR 228 will be explained. Presume that the storage period during the even periods n is longer than the storage period during the odd periods n+1, that is, t.sub.stn >t.sub.stn+1. In comparison with the input signal to the input 1 of the comparator 227, the input signal to the input 2 thereof is lower. As a result, the output signal of the comparator 227 becomes "H" as shown in FIG. 9H. As the input signal of the input 1 of the exclusive OR is an "L" level signal during the odd periods n+1, the output signal of the judgment circuit 22 becomes "H". When the storage period on one of the periods is shorter than one on the former period and the even periods n are replaced with the odd periods n+1, the output signal of the comparator 227 becomes "L", but the output signal of the judgment circuit 22 becomes "H" as shown in FIG. 9I because the input signal to the input 1 of the exclusive OR 228 is "H". Namely, when the storage period of the following period is shorter than one of the former period, the output signal of the judgment circuit 22 becomes "H" from the trailing edge of the storage period to a point, at which the output Q reverses the polarity. In contrast, when the storage period of the following period is longer than the former one, with the same algorithm as explained above, the output signal of the judgment circuit 22 becomes "L" during the same period.

Next, an example of the adjusting circuit 23 will be explained referring to FIG. 8. The pulse generator 17 comprises a DFF 171, an AND gate 172, a NAND gate 173, a coincidence circuit 174, a NOT gate 175 and diodes 176 and 177. The LPF18 is constructed by resistors 181 and 192 and a condenser 183. The control pulse generator 19 is formed by a monostable multivibrator (hereinafter MM). The DFF 171 memorizes information concerning add or subtract of the control pulse in the former control time.

Now, consider the case when the pulse width decreases after adding the control pulse in the period n and the judgment circuit 22 decides that t.sub.stn >t.sub.stn+1 in the period n+1. As the storage period t.sub.stn is longer than the storage period t.sub.stn+1, the input pulse of the coincidence circuit 174 becomes "H". In this case, the output Q of the DFF 171 is "H" as shown in FIG. 9J, because the control pulse increases in the period n. Therefore, the input D of the DFF 171 is supplied with an "H" level signal. The terminal Cp of the DFF 171 receives an inverted pulse from the NOT gate 175. The DFF 171 holds the input signal to the input D at the trailing edge, that is, "H". The AND gate 172 receives the output signal from the output Q of the DFF 171 and the output signal of the MM 191. Therefore, the output signal of the AND gate 172 becomes "H" in the period that the control pulse shown in FIG. 9K is " H". As a result, the diode 176 has a "pass" state during the period in which the control pulse is "H", and charges corresponding to the pulse width of the control pulse are stored in the condenser 183. That is, charges corresponding to one of the control pulses increases and the potential of an output terminal 184 rises.

Next, consider the case when the pulse width decreases after adding the control pulse in the period n, but the judgment circuit 22 decides that t.sub.stn >t.sub.stn+1. As the storage period t.sub.stn is shorter than the storage period t.sub.stn+1, the input pulse of the coincidence circuit 174 becomes "L". In this case, the output Q of the DFF 171 is "H", because the control pulse increases in the period n. Therefore, the output signal of the coincidence circuit 174 becomes "L", and the DFF 171 holds "L" during the period n+1. As the input of the AND gate 172 always receives an "L" level signal from the output Q of the DFF 171, the AND gate 172 provides an "L" level signal. On the contrary, the output Q of the DFF 171 rises to "H" level and the output of the NAND gate 173 provides a "L" level signal during a period in which the control pulse from the MM 191 is "H" level. During the same period, the diode 177 has a "pass" state and the charges corresponding to the pulse width of the control pulse are discharged from the condenser 183. That is, the charges corresponding to one control pulse decrease and the potential of the output terminal 184 goes down.

Further, during the periods n, in the case where the output signal of the output Q of the DFF 171 is "L" level, if the output signal of the judgment circuit 22 is "H", the charge is discharged from the condenser 183, and if the output signal of the judgment circuit 22 is "L", the charge is stored in the condenser 183. Namely, in the case where the output signal of the judgment circuit 22 does not vary, the output signal of the output Q of the DFF 171. In the case where the output signal of the judgment circuit 22 varies, the output signal of the output Q changes to a reverse state in comparison with the former state.

Finally, VCMM 13 varies the pulse width in response to the output signal of the LPF 18. FIG. 10 shows one example of the VCMM 13. A transistor 134 is triggered one time per each horizontal period by an output signal of the trigger circuit 12. The trigger signal is differentiated by a condenser 13 and resistors 132 and 132'. The transistor 134 changes to a "pass" state at the leading edge of the trigger signal, so that a condenser 137 is instantaneously charged to V.sub.cc. After that, a constant current circuit constructed by a transistor 134' and resistors 133, 133' and 135 discharges condenser 137 and the terminal voltage of the condenser 137 decreases linearly. An output signal of a comparator 138 becomes "H" level at the leading edge of the trigger signal and becomes "L" level at a time in which a voltage of an input 1 of the comparator 138 becomes lower than a voltage (V cont.) of another input 3 thereof. The voltage (V cont.) of the input 2 is a divided voltage of the output signal of the LPF 23 bt.) of another input 3 thereof. The voltage (V cont.) of the input 2 is a divided voltage of the output signal of the LPF 23 by resistors 136, 136' and 139. As a result, the VCMM 13 has the characteristic shown in FIG. 11. Referring to FIG. 11, a two-coordinate graph, an abscissa axis indicates the voltage (V cont.) and an ordinate axis indicates the pulse width (T.sub.P) of the output pulse.

FIG. 12 illustrates a circuit diagram of another embodiment of the present invention. In this embodiment, the drive supply voltage E.sub.d is controlled for keeping the storage period t.sub.stg at the minimum value t.sub.sm. Referring to FIG. 12, several of the same circuit elements as shown in FIG. 5, for example, the detecting circuit 21 and the judgment circuit 22, are used. The numeral 31 denotes a drive voltage control circuit. The drive voltage control circuit 31 includes a control transistor 311, amplifying transistors 312 and 313, dividing resistors 314 and 315, load resistors 317 and 318 and an emitter resistor 316. The control transistor 311 adjusts a voltage of an input terminal P of the driving circuit 20 corresponding to a control voltage, which is an output signal of a control voltage generator 30. The control voltage generator 30 is constructed with the pulse generator 17, the control pulse generator 19 and the LPF 18 as shown in FIG. 5. Therefore, the output signal of the control voltage generator 30 is the same signal as the output signal of the LPF 18 shown, in FIG. 5. The drive voltage control circuit 31 determines the voltage of the input terminal P, a voltage at a point Q, (which is a divided voltage of the voltage of the input terminal P), becomes equal to a voltage at a point R, that is, equal to the output signal of the LPF 18. As a result, the driving supply voltage is controlled in response to the output signal of the LPF. In FIG. 12, E.sub.D ' and E.sub.C are direct current supplies. It is no problem that E.sub.C is equal to E.sub.D '.

The operation of the other elements 17-19, 21 and 22 of the circuit shown in FIG. 12 is the same as that shown in FIG. 5. Therefore, a detailed explanation thereof need not be repeated.

In the above embodiments, the polarities of the pulse signal, the sampling signal and the output signals will not be restricted to the ones described hereinbefore. Further, for the convenience of explanation, the time constant of the LPF 18 has been set to be adequately smaller than the horizontal period, and the stable state of the present drive circuit has been mentioned as the state where the condenser 183 of the LPF 18 alternately charges and discharges. However, by selecting the time constant of the LPF at such a value that is adequately longer than the horizontal period, there is no non-stability of the circuit by a repetition of charge and discharge.

Therefore, it is possible to hold the fall time at the minimum value by detecting the storage period t.sub.stg and controlling one of the signals supplied to the primary coil to keep the storage period t.sub.stg at the minimum value t.sub.sm. As a result, in this invention, it becomes possible to suppress a generation of energy losses during the fall time and prevent thermal runaways.

According to the driving circuit of the present invention, it becomes possible to continuously maintain the fall time of the output transistor at its minimum value, even if the ambient temperature increases, and provide a high speed switching circuit without thermal runaway.