Low Side Switch Integrated Circuit

This application contains subject matter which is common to subject matter disclosed in patent application Ser. No. 866,805 U.S. Pat. No. 4,703,390 filed concurrently herewith.

This invention relates, in general, to semiconductor integrated circuits, and more particularly, to a low side switch integrated circuit.

A very common device for switching power to a load has been the relay. However, one disadvantage of using relays for switching high currents to a load is that the contacts tend to pit and corrode which results in poor coupling of the current to the load. Another disadvantage is that contacts will tend to bounce when current is first applied or first removed. To overcome these disadvantages transistors have been used to switch the power to a load. More recently, the technology has advanced to a point to where field effect transistors can be used as switches. Field effect transistors are easily integrated and lend themselves to be easily controlled by MOS circuits.

Accordingly, it is an object of the present invention to provide an improved integrated circuit switch for controlling power to a load.

Another object of the present invention is to provide a single monolithic integrated circuit capable of switching power to a load in response to an analog or a digital input and having diagnostic circuitry available for fault indication.

Another object of the present invention is to provide an integrated circuit switch which has over current as well as over temperature limit indication.

The above and other objects of the present invention are provided by an integrated circuit having a field effect transistor for switching current to a load which is connected in series with the field effect transistor. Also provided are means for sensing current to the load which is amplified and then compared against a reference. If the current exceeds the reference, a fault notice is provided. The fault notice is also used to inhibit a control means which controls an enable signal to the field effect transistor.

The subject matter which is regarded as the invention is set forth in the appended claims. The invention itself, however, together with further objects and advantages thereof, may be understood by referring to the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 illustrates, in block diagram form, the integrated circuit switch of the present invention; and

FIG. 2 illustrates the fault indicating circuitry of FIG. 1.

FIG. 1 illustrates an integrated circuit 10 which uses CMOS circuitry to control a high voltage, high power MOS field effect transistor 16 which is connected as an open drain, grounded source. This configuration of field effect transistor 16 is commonly referred to as a low side switch since a switch (field effect transistor 16) is located in the return current path for the load, which is connected to terminal 15 in an operating circuit. The load would be connected between a power supply and terminal 15. Integrated circuit 10 receives an ON-OFF command which is connected to an input of a comparator 11. A second input of comparator 11 is connected to a reference voltage VR. The output of comparator 11 is connected to the D input of flip-flop 12. The Q output of flip-flop 12 is connected to a buffer driver 13. The output of buffer driver 13 is connected to the gate electrodes of field effect transistors 14 and 16.

In a preferred embodiment, transistor 14 can be a single cell or single transistor while transistor 16 can comprise more than a 1000 transistors all connected in parallel similar to transistor 14. The source electrode of transistor 16 is connected to ground while the source electrode of transistor 14 is connected to node 19. A current sense resistor is connected between node 19 and ground. Field effect transistor 14 and resistor 17 are in parallel with field effect transistor 16 and only a very small portion of the current flowing through the load connected to terminal 15 would flow through transistor 14 and resistor 17 which serve to sense current flow. The majority of the current flows through transistor 16. Resistor 17 is typically a small resistor on the order of 40 ohms. Accordingly, a very small voltage is developed at node 19 which is coupled to an amplifier 18. Amplifier 18 amplifies this small voltage at node 19 and outputs this amplified voltage to a comparator 21. Comparator 21 serves as an current limit comparator and also receives a reference voltage VR.

If the amplified signal from amplifier 18 exceeds the reference voltage VR, comparator 21 will toggle to provide an output which is connected to an input of a dual input OR gate 22. Optionally the output of comparator 21 is also connected to an input of fault circuitry 23. Connected to a second input of dual input OR gate 22 is an output from a temperature limit circuit which is a portion of reference voltage generator 26. In a preferred embodiment reference generator 26 is a bandgap voltage generator and provides a reference voltage output VR. Bandgap voltage generators made by a CMOS process are well known. One such bandgap voltage generator is disclosed in U.S. Pat. No. 4,287,439 which issued to Leuschner in September 1981. Another bandgap voltage generator which can be made by a CMOS process is disclosed in U.S. Pat. No. 4,380,706 which issued to Wrathall in April 1983.

OR gate 22 provides an output if over current comparator 21 toggles or if over temperature limit 26 senses a temperature in excess of a predetermined value. The predetermined value can be in the range of 135.degree. C. in a preferred embodiment. The temperature sensed is the temperature of the die having integrated circuit 10 thereon. This temperature is approximately the same as the junction temperature of transistor 16 since everything is on the same die. Fault circuitry 23 uses the output of OR gate 22 to provide a composite failure or fault indication F. The output of over temperature limit circuitry 26 can also be connected to fault circuitry 23 to cause fault circuitry 23 to generate an over temperature fault indication F2. Fault circuitry 23 uses the output of over current comparator 21 to generate an over current fault indication F1. Fault circuitry 23 has a latch on each input to latch the fault signal received. Each one of these latches is reset when both the ON/OFF input and the CE are present in a valid form. Both of these signals are ANDed by an AND gate 20 which provides a reset signal R to fault circuitry 23.

The output of OR gate 22 is also connected to the reset input of flip-flop 12. Therefore, when OR gate 22 provides an output due to an over current condition or over temperature condition, flip-flop 12 will be reset thereby removing the enabling signal from field effect transistors 14 and 16. Integrated circuit 10 also receives a chip enable not signal CE which is connected to an input of a comparator 24. A second input of comparator 24 is connected to reference voltage VR. The output of comparator 24 is connected to the clock input C of flip-flop 12. The output of comparator 24 is also used as a CE out signal which is connected to fault circuitry 23 to enable the output of the fault circuitry as will become more apparent hereinafter.

An optional embodiment will have the output of buffer driver 13 brought to an outside pin of integrated circuit 10 and the connection to the gate electrodes of transistors 14 and 16 will also be brought out to an outside pin. This will provide for the addition of a resistor or a resistor capacitor network to be used for controlling the switching speeds of transistors 14 and 16. This option is useful where slowing the operation of the transistors helps reduce noise and voltage spikes.

By now it should be appreciated that there has been provided an integrated circuit 10 which can be made totally by using CMOS processes. The ON-OFF input and the chip enable inputs are received by comparators in case these command signals operate in a voltage range which is not typically compatible with CMOS integrated circuit 10. Note that as illustrated, fault circuitry 23 can provided three different fault indications. If it is desired to package integrated circuit 10 in a small package having a limited number of interface pins then either composite fault signal F could be eliminated of if F is used then fault signals F1 and F2 could be eliminated. If fault signal F is eliminated then there would be no need for the connection from the output of OR gate 22 to fault circuit 23. Another option that can be provided on integrated circuit 10 is to connect node 19 to an outside pin so that an additional resistor can be connected in parallel with resistor 17 to thereby change the over current limit setting. It will be noted that if a chip enable signal is not required then a simple RS flip-flop could be used for flip-flop 12.

FIG. 2 illustrates, in schematic form, internal circuitry of one embodiment of fault circuit 23. Fault circuit 23 contains three open drain field effect transistors 31, 32, and 33. Each one of the transistors has its source connected to ground. The drain of transistor 31 is connected to fault indication F1, the drain of transistor 32 is connected to F, and the drain of transistor 33 is connected to F2. The fault outputs are open drain field effect transistors capable of using various supply voltages and since the ON/OFF and CE signals require only TTL levels, any external interfacing device can be operated at any voltage level from TTL high to VDD.

The gate electrode of transistor 31 is connected to the output of an AND gate 34. One input of AND gate 34 receives CE out from the output of comparator 24; the other input of AND gate 34 is connected to the output of an RS latch 38. RS latch 38 receives a set input S1 from the output of comparator 21 and reset R from the output of AND gate 20. The gate electrode of transistor 32 is connected to the output of AND gate 35. AND gate 35 receives inputs CE out and the output of an RS latch 39. Latch 39 receives reset R and a set input S2 from the output of OR gate 22. The gate electrode of transistor 33 is connected to the output of AND gate 36. AND gate 36 receives CE out and the output from RS latch 40. RS latch 40 receives reset R and a set input S3 from the output of temperature limit 26.