3-Input Exclusive-or Gate Circuit

The present invention relates to an Exclusive-OR gate circuit and more particularly to a 3-input CMOS type Exclusive-OR gate circuit which is particularly adapted for combining with other like circuits in a parity checking circuit configuration.

Parity checking circuits verify the correct operation of a data processing system by completing the count for a group of bits such that a correct group of bits and the parity bit will always be, for example, an even count. A single bit error will make the count odd, thereby indicating the existence of the error. Generally speaking, a data processing system is designed to operate on groups of 8 bits, each commonly called a byte. Each group of 8 bits has 1 parity bit appended to it, such that each group of 9 error free bits always includes an even or an odd number of 1's depending on the type of parity convention designed into the processor.

Traditional implementations of parity circuits use 8, 2-input Exclusive-OR gates for processing a byte (8 bits) and an associated parity bit (1 bit). The present inventive circuit is configured to receive three input signals. The traditional implementations experience a significant delay in signal processing because of the large number of gates used. It is therefore, highly desirable to use the least number of gates to accomplish the desired Exclusive-OR function with the least amount of signal delay.

A patent of particular interest for its teaching of an Exclusive-OR circuit that may be used in a parity checking circuit and for an extensive listing of prior art publications is U.S. Pat. No. 4,430,737 entitled, "Exclusive-OR Circuit and Parity Checking Circuit Incorporating the Same" by H. Beranger et al.

Another patent of interest is U.S. Pat. No. 4,319,148, entitled, "High Speed 3-Way Exclusive-OR Logic Circuit" by S. D. Malaviya wherein is disclosed a circuit which performs an OR function with a delay essentially equal to that experienced in a single logic stage.

Another patent of interest is U.S. Pat. No. 4,417,161 entitled, "Complemetary Channel Type MOS Transistor Exclusive-OR/NOR Logic Gate Circuit" by M. U. Kadoma wherein is disclosed a two input Exclusive-OR gate which is implemented in CMOS with a reduced number of transistors from that of conventional circuits.

Other patents of interest are U.S. Pat. Nos. 4,651,296 entitled, "High Speed CMOS FET Full-Adder Circuit" by H. Koike which is implemented in CMOS logic and 4,626,711, entitled, "Exclusive-OR Gate Circuit", by G. M. Li which discloses an Exclusive-OR gate that is suitable for use as a parity bit generator.

In the preferred circuit embodiment of the present invention, there is provided a first inverting means for receiving three input signals and for providing three inverted input signals; a pair of current switches serially connected together at a juncture defining a first node; a means for receiving a first of the provided three inverted input signals and for outputting signals to the pair of current switches corresponding to the inverted input signal; and the complement of the inverted input signal, such that only one of the pair of current switches is turned on at any time. Additionally, there is provided a second inverting means for receiving the signal at the first node and for having an output providing the circuit's output signal; a means of a first type responsive to the second and the third of the provided three inverted input signals for gating the signals to one current switch of the pair of current switches; and means of a second type, complementary to the first type, responsive to the second and the third of the provided three inverted input signals for gating the signals to the other current switch of the pair of current switches.

From the foregoing it can be seen that it is a primary object of the present invention to provide a 3-input Exclusive-OR gate circuit which utilizes a minimum number of transistor gates.

It is another object of the present invention to provide an Exclusive-OR circuit which may be combined with other like circuits to form a parity generator.

These and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein like characters indicate like parts, and which drawings form a part of this disclosure.

FIG. 1 is a schematic diagram of the preferred embodiment of the present invention; and

FIG. 2 is a block logic diagram illustrating the configuration of a parity checking circuit incorporating four of the circuits shown in FIG. 1.

Referring to FIG. 1, the Exclusive-OR gate circuit embodiment of the present invention is shown having three inputs labeled A, B and C, and one output labeled D. Three pairs of CMOS transistors, M1-M2, M3-M4 and M5-M6, form first, second and third inverters, respectively. Each of the inverters is connected to one of the labeled inputs. The inverters function to invert the logic level of the signals on their inputs. The inverted signals are taken from the juncture of the respective pairs of CMOS transistors. Each of the inverters is connected between a power potential terminal labeled VDD and a reference potential terminal which in the preferred embodiment is ground. The output from the first inverter is connected to a first pair of MOS gates of first channel type, M11-M12, and to a second pair of MOS gates, M7-M8, of second channel type. In a like manner, the output signal from the third inverter is connected to the first pair and the second pair of MOS gates, M11-M12 and M7-M8, respectively. The gates are formed of MOS transistors each having a source, drain and gate electrode. The source and drain electrodes constitute a current path which path is controlled by the potential on the gate electrode. A circle on the gate electrode of the MOS devices, shown in the drawings, indicates a P-channel device and the absence of a circle indicates an N-channel device. The first pair of MOS gates, being of the P-channel type, and the second pair of MOS gates, being of the N-channel type, makes the first pair of MOS gates responsive to signals which are complementary to those to which the second pair of MOS gates would be responsive.

In the preferred embodiment, there is a cross coupling such that the gate electrode of M7 is connected to the output of the third inverter while the gate electrode of M8 is connected to the output of the first inverter. In a like manner, the gate electrode of M11 is connected to the output of the third inverter and the gate electrode of M12 is connected to the output of the first inverter. The first and second pair of MOS gates connect to the remainder of the circuit via their current paths at nodal points NA and NC, respectively. A first P-channel, MOS gate M13, connects the nodal point NA to a power potential terminal denoted VDD. The gate electrode of MOS device M13 is connected to the reference potential. A second N-channel, MOS gate M18, connects the nodal point NC to the reference potential and has its gate electrode connected to the power potential terminal VDD. A first pair of parallel connected complementary MOS gates, M14 and M15 (commonly called a transmission gate), is connected between the nodal point NA and a nodal point NB. In a like manner, a second pair of parallel connected complementary MOS gates, M16 and M17, are connected between the nodal point NB and NC. These transmission gates operate as current switches in response to the signals appearing on their gate electrodes. These signals are generated by a modified inverter circuit comprises of complementary MOS transistors M9 and M10. The gate electrodes of devices M9 and M10 are coupled to the output of the second inverter circuit formed from devices M3 and M4. The first output is taken from the junction point of devices M3 and M4 and is directed to the gate electrode of device M9 and to the gate electrode of device M10 and to the gate electrode of device M17 and to the gate electrode of device M14. The second output, which is complementary to the first output, is taken from the junction point of devices M9 and M10 and is directed to the gate electrode of device M15 and to the gate electrode of device M16. The signal resulting at the node NB is directed to a fourth inverter circuit formed from the MOS devices M19 and M20. The circuit output is taken from the juncture of the device M19 and M20.

In the following truth table, labeled TABLE 1, there is disclosed the relationship between the logic level of the signals on the inputs labeled A, B and C and the logic level of the signals on the internal nodes NA, NB and NC, and finally their relationship to the logic level of the signal on the output labeled D. In the nomenclature used in Table 1, L stands for a low level signal and H stands for a high level signal. For those knowledgeable in this art, it can be quickly deduced that the logic level of the signal on the output D is an Exclusive-OR function of the logic level of the signals on the inputs A, B and C.

In the following state table, labeled TABLE 2, there is disclosed the "ON" and "OFF" states for each of the MOS gates labeled M1-20 for the full range of logic possibilities for the signals applied to the inputs A, B and C.

The circuit of FIG. 1, thus far described, finds particular utility as a building block for a parity circuit.

Referring to FIG. 2, four of the Exclusive-OR gates of FIG. 1 are shown interconnected so as to form a parity checking circuit which circuit receives as inputs 8-bits (byte) of data with the ninth input being the parity check bit. The output of the parity checking circuit will be of a first logic level when the 8 bits and the check bit are in a correct relationship and will be of a second logic level when any of the 8 bits are in error.

Although the invention has been described and illustrated in detail, it is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only by the terms of the appended claims.