US 4,749,885 AGrant
Nonsaturating Bipolar Logic Gate Having a Low Number of Components and Low Power Dissipation
Issue Date:1988-06-07
•10 Claims
•4 Drawing Sheets
Abstract
A two input nonsaturating bipolar logic gate consists of just two bipolar transistors plus a pair of resistors plus two voltage buses. One resistor has a resistance R.sub.C and it is connected from one of the voltage buses to the collector of both transistors. The second resistor has a resistance R.sub.E and it is connected from the other voltage bus to the emitter of both transistors. Those resistances R.sub.C and R.sub.E are selected such that R.sub.C /R.sub.E >1 and 0.1<(V.sub.CC -V.sub.BE)R.sub.C /R.sub.E <0.8 V.sub.BE where V.sub.BE is the base to emitter voltage at which each transistor turns on and V.sub.CC is the voltage between the two voltage buses.
Metadata
Assignee
- Unisys Corporation
Inventor
- Laszlo V. Gal
Application Information
Application Number:US 0153826
Filing Date:1987-02-17
Priority Date:1987-02-17
Art Unit:254
Classifications
IPC:
H03K 19088H03K 19086H03K 19082H03K 19013
Field of Search:
307454;455;456
Patent Drawings (4 sheets)
Description
Background of the Invention
This invention relates to logic gate circuitry; and more particularly, it relates to those logic gate circuits that are made of nonsaturating bipolar transistors.
In the prior art, bipolar transistors are used to make both T.sup.2 L logic circuits and ECL logic circuits T.sup.2 L logic circuits consume less power the ECL logic circuits; however, T.sup.2 L logic circuits operate at a slower speed since their bipolar transistors are interconnected such that they saturate. By comparison, ECL logic circuits operate at a high speed; but they consume a large amount of power since their bipolar transistors are interconnected such that they do not saturate.
All of the circuitry of a conventional ECL logic gate is shown in FIG. 1. It receives two high or low input signal V.sub.i1 and V.sub.i2 ; then the left-hand portion of the gate forms a signal S.sub.1 of an intermediate voltage which represents the logical NOR of the input signals; and then the right-hand portion of the gate restores the voltage level of signal S.sub.1 to the high and low input signal levels. This gate has a switching speed of about 0.4 nanoseconds, a power dissipation of about 10 milliwatts, and it is commercially available in the MCA II gate array series from Motorola.
One problem, however, with the FIG. 1 ECL logic gate is that it includes a large number of components. Specifically, it includes five transistors T1, T2, T3, T4, and T5; four resistors R1, R2, R3, and R4; and four voltage buses B1, B2, B3, and B4. Each of these components occupies a certain amount of space on a semiconductor chip; and thus they limit the number of gates that can be integrated into the chip.
Another problem with the FIG. 1 ECL logic gate is that it consumes too much power. That power which is dissipated in the left-hand portion of the FIG. 1 gate can be expressed as V.sub.EE I.sub.O, and that power which is dissipated in the right-hand portion of the FIG. 1 gate can be expressed as (1/2)(I.sub.0 +0.81.sub.0)V.sub.EE.
Current I.sub.0 in the left-hand term is a constant current which always flows through either transistor T1, T2, or T3; and it is generated by the current source which is formed by the combination of transistor T4 and resistor R3. In the right-hand term, the current 1/2(I.sub.0 +0.81.sub.0) is the average current which flows through transistor T5. Current I.sub.0 flows when the output signal V.sub.0 is high, and current 0.8 I.sub.0 flows when the output V.sub.0 signal is low.
Accordingly, in an effort to overcome the above problem, a primary object of the invention is to provide an improved nonsaturating bipolar logic gate which operates at essentially the same speed as an ECL logic gate but which requires substantially fewer components and dissipates substantially less power.
Brief Summary of the Invention
With the present invention, a two input nonsaturating bipolar logic gate consists of just two bipolar transistors plus a pair of resistors plus two voltage buses. One resistor has a resistance R.sub.C and it is connected from one of the voltage buses to the collector of both transistors. The second resistor has a resistance R.sub.E and it is connected from the other voltage bus to the emitter of both transistors. Those resistance R.sub.C and R.sub.E are selected such that R.sub.C /R.sub.E >1 and 0.1<(V.sub.CC -V.sub.BE)R.sub.C /R.sub.E <0.8V.sub.BE where V.sub.BE is the base to emitter voltage at which each transistor turns on a V.sub.CC is the voltage between the two voltage buses.
Brief Description of the Drawings
Various features and advantages of the invention are described in the Detailed Description in conjunction with the accompanying drawings wherein:
FIG. 1 illustrates, for comparison purposes, an ECL logic gate of the prior art;
FIG. 2 illustrates a preferred embodiment of a logic gate that is constructed in accordance with the invention;
FIG. 3 includes a set of equations which impose constraints on the FIG. 2 logic gate;
FIG. 4 is a plot of the constraint equations in FIG. 3;
FIG. 5 shows a comparison of the space that is occupied by the logic gates of FIGS. 1 and 2;
FIG. 6 shows a comparison of the power that is dissipated by the logic gates of FIGS. 1 and 2; and
FIG. 7 shows a comparison of the time delay through the logic gates of FIGS. 1 and 2.
Detailed Description of the Invention
Referring now to FIG. 2, a preferred embodiment of the invention will be described in detail. This embodiment is a two-input logic gate which is made of just two transistors 11 and 12 plus two resistors 13 and 14. Both of the transistors 11 and 12 have their collectors coupled through resistor 13 to a bus 15 which carries a voltage V.sub.CC, and both of the transistors have their emitters coupled through resistor 14 to a bus 16 which is at ground. In operation, input signals V.sub.i1 and V.sub.i2 are applied to conductors on the base of transistors 11 and 12, and an output signal V.sub.0 is generated on a conductor from the collectors of those transistors.
Also in the FIG. 2 logic gate, certain constraints are placed on the resistors 13 and 14. Those constraints are developed by a set of equations which are shown in FIG. 3. Beginning with equation 1, it says that if both of the input signals are at a low logic level V.sub.0L, then both of the transistors 11 and 12 are turned off. Consequently, as stated by equation 2, the output signal will be at a high voltage level V.sub.OH which equals V.sub.CC.
Next, equation 3 states that if one of the input signals is at the high voltage level V.sub.0H, then the corresponding transistor will turn on. Thus, as stated by equation 4, the output signal will be at the low voltage V.sub.0L. Voltage V.sub.0L equals the bus voltage V.sub.CC minus the voltage drop across resistor 13. In equation 4, the term R.sub.C is the resistance of resistor 13 and I.sub.C is the collector current.
Equation 5 then says that when one of the transistors is on, the collector current I.sub.C is approximately equal to the emitter current I.sub.E, and the emitter current is equal to the emitter voltage V.sub.E divided by the resistance R.sub.E of resistor 14. However, the emitter voltage V.sub.E is equal to the base voltage minus V.sub.BE, where V.sub.BE is the base to emitter drop which occurs when the transistor is on. By virtue of equation 2, the base voltage equals V.sub.CC. So substituting equation 5 into equation 4 yields equation 6.
Equation 7a says that the low level output voltage V.sub.0L must be less than V.sub.BE. This constraint insures that transistors 11 and 12 in the FIG. 2 logic gate do not turn on when their input signals are low. Inspection of equation 6 shows that to meet this constraint, the ratio of the resistances R.sub.C and R.sub.E must be greater than one, and this constraint is stated by equation 7b.
Equation 8a says that the maximum forward voltage, V.sub.f, across the base to collector junction in transistors 11 and 12 must be less than (0.8)(V.sub.BC) where V.sub.BC is the base to collector turn-on voltage. This constraint of equation 8a keeps the transistors 11 and 12 from going into saturation; and that in turn makes the switching speed of those transistors fast.
By symmetry, V.sub.BC equals V.sub.BE. And for a silicon transistor, V.sub.BE is 0.7 volts; for a germanium transistor, V.sub.BE is 0.3 volts; and for a gallium arsenide transistor, V.sub.BE is 0.9 volts. Also, voltage V.sub.f equals the collector current I.sub.C times resistance R.sub.C, and the collector current I.sub.C can be expressed in terms of equation 5. Consequently, the constraint of equation 8a can be rewritten as equation 8b.
Equation 9a states that the difference between the two output voltage level V.sub.0H and V.sub.0L must be greater than 0.1 volts. This constraint of equation 9a ensures that the swing of the output voltage will be larger than the amount of noise which typically occurs in an integrated circuit chip. Both of the voltage levels in equation 9a are given by equation 2 and equation 6. Thus, the constraint of equation 9a and can be rewritten as equation 9b.
Turning now to FIG. 4, it contains respective plots of the equations 7b, 8b, and 9b for the case where silicon transistors are used (i.e., V.sub.BE is 0.7 volts). Curve 21 is a plot of equation 7b; curve 22 is a plot of equation 8b; and curve 23 is a plot of equation 9b. These three plots form the boundary of an area 24; and in order for the FIG. 2 logic gate to operate properly, the parameters R.sub.C, R.sub.E, V.sub.CC and V.sub.BE must be chosen to lie within that area.
For example, suppose that the desired operating point in FIG. 4 is given by reference numberal 25. In that case, suitable values for R.sub.C, R.sub.E, and V.sub.CC respectively are 200 ohms, 100 ohms, and 0.9 volts.
One important feature of the FIG. 2 logic gate is that the chip space which is occupied by the gate is small. This is evident from equations 1, 2, and 3 in FIG. 5. Equation 1 says that the chip space S.sub.2 which the FIG. 2 gate occupies is equal to the space 2T that is occupied by two transistors plus the space 2R that is occupied by two resistors plug the space 2V that is occupied by two voltage buses. By comparison, equation 2 says that the space S.sub.1 which is occupied by the FIG. 1 logic gate is equal to the space 5T of five transistors plus the space 4R of four resistors plus the space 4V of four voltage buses. Comparing equation 1 and equation 2 yields equation 3 which says that the FIG. 2 logic gate occupies less than half the space of the FIG. 1 logic gate.
Another important feature of the FIG. 2 logic gate is that the amount of power which it dissipates is small. This is evident by inspection of equations 1, 2 and 3 in FIG. 6. Equation 1 says that the power P2 which the FIG. 2 logic gate dissipates is equal to the voltage V.sub.CC across the gate V.sub.CC times the average current 1/2I.sub.C through the gate. This average current is arrived at by assuming that the output voltage is at V.sub.0L and at V.sub.0H for equal time durations.
By comparison, equation 2 in FIG. 6 gives an expression for the power P1 which is dissipated by the FIG. 1 logic gate. In that equation, the left-hand term gives the power that is dissipated in components R1, R2, R3, T1, T2, T3, and T4; and the right-hand term gives the power that is dissipated in components R4 and T5. Equation 2 also says that the voltage V.sub.EE is about two times the voltage V.sub.CC.
In the FIG. 1 circuit, transistors T3 and T4 are stacked on top of one another (i.e. they are serially) connected between the V.sub.EE and ground voltage buses). Thus in the FIG. 1 circuit, V.sub.EE must be at least twice V.sub.BE to ensure that both of the serially connected transistors can turn on. But in the FIG. 2 circuit, V.sub.CC can be less than twice V.sub.BE. In fact, FIG. 4 shows V.sub.CC can nearly equal V.sub.BE. Comparing then equation 1 with equation 2 in FIG. 6 yields equation 3 which says that the power dissipation of the FIG. 2 circuit is less than one-seventh of the power dissipation in the FIG. 1 circuit.
Even though the power dissipation of the FIG. 2 logic gate is substantially less than that of the FIG. 1 logic gate, the speed of operation of the two gates is substantially the same. This is evident from equations 1, 2, and 3 of FIG. 7. Equation 1 says that the time delay TD.sub.2 thru the FIG. 2 logic gate is equal to the turn-on time or turn-off time of transistor 11 (or transistor 12). By comparison, equation 2 says that the time delay TD.sub.1 thru the FIG. 1 logic gate is approximately equal to the turn-on or turn-off time of one of the transistors T1 and T2 in the differential pair plus some additional delay which is caused by transistor T5. If one assumes the delay through transistor T5 is relatively small since it is always on, then comparing equation 1 with equation 2 yields equation 3 which says that the time delays thru the FIG. 1 and FIG. 2 logic gates are nearly equal.
A preferred embodiment of the invention has now been described in detail. In addition, however, many changes and modifications can be made to these details without departing from the nature and spirit of the invention. For example, the transistors 11 and 12 in the FIG. 2 circuit are shown as NPN transistors; but they can also be PNP transistors. In that case, the voltage V.sub.CC would be negative instead of positive.
Accordingly, it is to be understood that the invention is not limited to just one embodiment but is defined by the appended claims.
Claims
What is claimed is:
1. An improved N input logic gate which consists of just N bipolar transistors having respective bases for receiving two level input signals, plus a pair of resistors, plus two voltage buses; a first resistor of said pair having a resistance R.sub.C and being connected from one of said voltage buses to the collector of all N transistors for generating output signals thereon; a second resistor of said pair having a resistance R.sub.E and being connected from the remaining voltage bus to the emitter of all N transistors; and wherein to reduce power dissipation in said gate and to generate said output signals with the same two levels as said input signals, the improvement comprises said resistance R.sub.C and R.sub.E being selected such that R.sub.C /R.sub.E >1 and 0.1<(V.sub.CC -V.sub.BE)R.sub.C /R.sub.E <0.8V.sub.BE where V.sub.BE is the base to emitter voltage at which each transistor turns on and V.sub.CC is the voltage between said two voltage buses.
2. A logic gate according to claim 1 wherein said transistors are NPN transistors.
3. A logic gate according to claim 1 wherein said transistors are PNP transistors.
4. A logic gate according to claim 1 wherein said transistors are silicon transistors.
5. A logic gate according to claim 1 wherein said transistors are germanium transistors.
6. A logic gate according to claim 1 wherein said transistors a gallium arsenide transistors.
7. A logic gate according to claim 1 wherein said voltage V.sub.CC is less than 2V.sub.BE.
8. An integrated circuit which includes a plurality of N input logic gates that are interconnected to each other without any level shifters between the gates; wherein each logic gate consists essentially of: N bipolar transistors, which are of a single conductivity type throughout said integrated circuit; said transistors having collectors that are connected through a first resistor of resistance R.sub.C to a first voltage bus; said transistors having emitters that are connected through a second resistor of resistance R.sub.E to a second voltage bus; and said resistance R.sub.C and R.sub.e being selected such that R.sub.C /R.sub.E >1 and 0.1<(V.sub.CC -V.sub.BE)R.sub.C /R.sub.E <0.8V.sub.BE where V.sub.BE is the base to emitter voltage at which each transistor turns on and V.sub.CC is the voltage between said first and second bus.
9. An integrated circuit according to claim 8 wherein all of said transistors are NPN transistors.
10. An integrated circuit according to claim 8 wherein said voltage V.sub.CC is less than 2V.sub.BE.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3450896 | 1969-06-01 | Taniguchi et al. |