US 4,747,083 AGrant
Semiconductor Memory With Segmented Word Lines
Issue Date:1988-05-24
•7 Claims
•5 Drawing Sheets
Abstract
A semiconductor memory device including at least word lines and bit lines with memory cells located at each cross point therebetween. Each of the word lines is divided to form segmented word lines and each of the word line segments is driven by an individual private word driver. The individual private word drivers are activated together in response to a word selection signal. Level shifting diodes are employed in the bit line drivers to offset a voltage level change caused by the segment word drivers.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Tetsuya Nakajima
- Masaki Nagahara
Application Information
Application Number:US 6256740
Filing Date:1984-06-28
Priority Date:1983-06-29
Art Unit:233
Classifications
IPC:
G11C 800
Field of Search:
365230;174;226;242;155;179;63;72;227
Patent Drawings (5 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a semiconductor memory device (hereinafter "memory"), more particularly to a memory of a static random access memory (S.RAM) type composed of emitter-coupled-logic (ECL) memory cells.
Various types of memories have been developed and put into practical use. Recent research and development has concentrated in achieving greater miniaturization of memory patterns, i.e., increasingly higher densities of packaging of integrated circuit (IC) memories. To fabricate a denser IC memory, however, it is not sufficient merely to miniaturize the memory cells and wiring. Miniaturization creates additional problems which themselves must be solved.
2. Description of the Prior Art
In a prior art ECL-type S.RAM, increased miniaturization and higher integration create the problem of electromigration. More specifically, when the current density of, for example, aluminum wiring exceeds a predetermined threshold level, since the aluminum wiring is made narrower in width upon miniaturization, the aluminum in a solid state is transformed by heat into a molten state and will flow elsewhere.
When electromigration takes place, the desired memory function cannot be guaranteed. Therefore, excessive current density must be prevented, not only for aluminum wiring but all other wiring of other conductive materials, to suppress electromigration.
Summary of the Invention
It is an object of the present invention to provide a semiconductor memory device, particularly an ECL-type S.RAM, which can reduce the current density of wiring, even for narrow-width wiring used in miniaturized memories.
Consideration is given to reducing the current density of all word lines of a memory since there is considerable likelihood of electromigration in each word line due to their inherent roles. Each word line is divided into a plurality of segmented word lines. Each segmented word line is connected to an individual word driver and provided with memory cells, etc. Each of the segmented word lines carries an individual word current from an individual word driver when the word line is in a selection state.
Brief Description of the Drawings
The present invention will be more apparent from the ensuing description with reference to the accompanying drawings, wherein:
FIG. 1 is a circuit diagram representing a part of a typical semiconductor memory device;
FIG. 2A is a partial view of a semiconductor memory device equivalent to that of FIG. 1, but drawn somewhat more simply;
FIG. 2B is a diagram depicting the distribution of current density in and along a word line of FIG. 2A;
FIG. 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example;
FIG. 4A is a circuit diagram of a part of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 4B is a diagram depicting the distribution of current density in and along the word line segments of FIG. 4A;
FIG. 5 illustrates a detailed example of a known memory cell in FIG. 1;
FIG. 6 is a more detailed circuit diagram of the semiconductor memory device based on the device illustrated in FIG. 4A;
FIG. 7 is a circuit diagram of a part of a semiconductor memory device according to a second embodiment of the present invention; and
FIG. 8 is a circuit diagram of a part of a semiconductor memory device according to a modification of the second embodiment shown in FIG. 7.
Description of the Preferred Embodiments
Before describing the preferred embodiments, a discussion will be made of a prior art device for reference purposes.
FIG. 1 is a circuit diagram representing a part of a typical semiconductor memory device. The memory illustrated in FIG. 1 is specifically an ECL-type S.RAM. In FIG. 1, reference characters MC indicate memory cells which cooperate with each word line pair WL. Each pair is comprised of word lines W.sub.+ and W.sub.-. Many identical sets of word line pairs WL and memory cells MC are arranged in the direction along which bit line pairs (BL, BL) extend. Thus, many memory cells MC are located at cross points of the word lines and the bit line pairs. These memory cells MC constitute a memory cell array having rows and columns, indicated by MCA.
In a usual S.RAM, each word line W.sub.- is arranged with a respective word line W.sub.+ as a pair. Each pair of these word lines W.sub.+ and W.sub.- is connected to an individual hold current source HI. The hold current of each source HI maintains the logic "1" or "0" stored in each memory cell MC. Each word line W.sub.+ is selected by a corresponding word selection signal WS supplied by a word decoder DEC in accordance with an address input AD. The selection is achieved by turning on an individual word driver Q.sub.wd connected to the word line W.sub.+ at its end. On the other hand, similar drivers, i.e., bit drivers (mentioned hereinafter) are provided for respective bit line pairs BL, BL, in the memory.
In FIG. 1, there is significant electromigration in the word lines W.sub.+. A relatively large current may flow through each word line W.sub.+ due to, first, the hold current continually supplied to all the memory cells MC of each word line W.sub.+ and, second, a discharge current flowing to each discharge current source (DI) every time the word line pair WL is selcted. In other words, the above-mentioned large current along the word line W.sub.- is the sum of the hold current (I.sub.h) and the discharge current (I.sub.d) and is generated every time the word line W.sub.- is in a selection state. It should be noted that of the various types of memories, a bipolar ECL-type S.RAM exhibits the largest I.sub.h and I.sub.d currents. Incidentally, as is well known, the discharge current is useful to effect a quick change from the selection state to the nonselection state.
FIG. 2A is a partial view of a semiconductor memory device equivalent to that of FIG. 1, but drawn somewhat more simply. FIG. 2B is a diagram depicting the distribution of current density in and along the word line WL of FIG. 2A. The memory cell array MCA of FIG. 1 is represented simply as a block "MCA" in FIG. 2A. Also, both the hold current source HI and the discharge current source DI are represented simply as a block "IS" in FIG. 2A. In FIG. 2B, the abscissa denotes positions on and along the same word line WL as that of FIG. 2A, and the ordinate denotes a current I flowing therethrough. As illustrated in FIGS. 2A and 2B, the peak current density is I.sub.max, which iss produced at a current supply side of the word line, i.e., the end of the word line to which the word driver Q.sub.wd is connected.
FIG. 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example. As seen from FIG. 3, the word line WL is divided to form, along its length, a plurality of segmented word lines. Each of the word line segments WL.sub.1, WL.sub.2, WL.sub.3, . . . , WL.sub.n, except for the first segment WL.sub.1 activated directly by the word driver Q.sub.wd1, is provided with an individual private word driver, i.e., WD.sub.2, WD.sub.3 . . . WD.sub.n. When the corresponding word selection signal WS is used to supply a current individually to the memory cells in MCA.sub.1 for the word line segment WL.sub.1, the second private word driver WD.sub.2 is operated in response to the word line signal appearing at the first word line segment WL.sub.1. At the same time, the third and following private word drivers WD.sub.3, . . . , WD.sub.n are operated in response to the word line signals appearing at preceding word line segments WL.sub.2, WL.sub.3, . . . , WL.sub.(n-1) (not shown), respectively. In this regard, the memory cell array MCA and the drive current source IS, both shown in FIG. 2A, are segmented as MCA.sub.1, IS.sub.1 ; MCA.sub.2, IS.sub.2 ; MCA.sub.3, IS.sub.3 ; . . . and so on.
FIG. 4A is a circuit diagram of a part of a semiconductor memory device according to a first embodiment of the present invention. FIG. 4B is a diagram depicting the distribution of current density in and along the word line segments of FIG. 4A. Incidentally, in this specification, reference characters which are the same as in different figures represent the same components in each figure.
The explanation of FIGS. 4A and 4B will, for simplicity, be made taking as an example a case where the memory is segmented into two blocks. That is, the word line WL is divided to form first and second word line segments WL.sub.1 and WL.sub.2. Therefore, the memory cells and the current source are also segmented to form MCA.sub.1, IS.sub.1 and MCA.sub.2, IS.sub.2. In a first block, the word driver Q.sub.wd1 is connectedd to the first word line segment WL.sub.1. The word driver WD.sub.2 of FIG. 3 is specifically comprised of a word driver Q.sub.wd2. Other word drivers WD.sub.3, . . . , WD.sub.n of FIG. 3 are identical to the word driver WD.sub.2 shown in FIG. 4A, i.e., a single transistor Q.sub.wd2. In the example of FIG. 4A, the distribution of current density is as illustrated in FIG. 4B. It is important to note that the peak current density in each of the word line segments WL.sub.1 and WL.sub.2 is approximately halved to I.sub.max /.sub.2, the value I.sub.max being that obtained in the prior art device illustrated in FIGS. 2A and 2B.
According to the first embodiment of FIG. 4A, the word driver transistor Q.sub.wd2 is directly connected, at its base, to the preceding word line segment, i.e., WL.sub.1, so as to activate the transistor Q.sub.wd2 in response to the word selection signal WS. That is, when the signal WS is received by the word driver Q.sub.wd1, the word line signal appears with an "H" (high) level on the segment WL.sub.1. The "H" level signal is immediately transferred, via the transistor Q.sub.wd2, to the following word line segment, i.e., WL.sub.2. Thus, the whole corresponding word line WL is selected. The above construction has the advantage that no separate control line is needed to activate the word driver transistor Q.sub.wd2.
Referring to FIG. 4A, the word line WL is segmented into WL.sub.1 and WL.sub.2 with the use of the word driver transistor Q.sub.wd2. In this case, the voltage level at the word line segment WL.sub.2 is lowered by V.sub.BE from that of the word line segment WL.sub.1. The character V.sub.BE denotes a base-emitter voltage of the word driver transistor Q.sub.wd2. The thus lowered voltage of the segment WL.sub.2 has a deleterious effect on the operation of the memory cell array MCA.sub.2 which will be further explained with reference to FIG. 5.
FIG. 5 illustrates a detailed example of the known memory cell MC in FIG. 1. As seen from FIG. 5, each memory cell MC is comprised of multiemitter transistors Q.sub.1 and Q.sub.2 and loads L.sub.1 and L.sub.2. Each of the loads comprises a resistor and a Schottky barrier diode connected in parallel. Assuming here that the transistor Q.sub.1 is now on (the problem occurs when the transistor Q.sub.2 is on), the voltage V.sub.WB between the word line Q.sub.+ and the bit line BL must be higher than a predetermined level to maintain the transistor Q.sub.1 in a conductive state during the selection state of the corresponding word line. The predetermined level V.sub.WB mentioned above is equal to the sum of a voltage drop across the load L.sub.2 and the base-emitter voltage of the transistor Q.sub.1. Even though the predetermined level V.sub.WB is assured for the selected memory cell MC in the first memory cell array MCA.sub.1, it is not assured for the second memory cell array MCA.sub.2. Hence, the level V.sub.WB is lowered to V'.sub.WB. The level V'.sub.WB is here expressed as V'.sub.WB =V.sub.WB -V.sub.BE, where V.sub.BE denotes the above-mentioned base-emitter voltage of the word driver transistor Q.sub.wd2. In this case, an output voltage of each bit driver (mentioned hereinafter) is increased relative to the lowering of V.sub.WB, which output voltage is used to determine the voltage of the bit line BL. Due to the relative increase of the output voltage, a bit line driver transistor (mentioned hereinafter) can become saturated. In the saturated state, the read operation speed is reduced. To counter this, a level shifting means is employed in each of the bit drivers connected to the memory cell array MCA.sub.2. This also applies to other bit drivers connected to the memory cell arrays MCA.sub.3, . . . , MCA.sub.n following thereafter. Thus, the voltage V'.sub.WB =(V.sub.WB -V.sub.BE) is shifted upward in level by V.sub.BE. The above-mentioned voltage V.sub.WB assured in the memory cell array MCA.sub.1 can thereby also be assured in the memory cell array MCA.sub.2.
FIG. 6 is a more detailed circuit diagram of the semiconductor memory device based on the device shown in FIG. 4A. In FIG. 6, the bit drivers are specifically illustrated with reference characters BD.sub.11 through BD.sub.1n and BD.sub.21 through BD.sub.2n. The bit driver transistors in each of the bit drivers are specifically illustrated with reference characters Q.sub.BD. The level shifting means is represented by reference characters LS in the block containing the second MCA.sub.2. It should be understood that only two blocks B.sub.1 and B.sub.2 are illustrated for simplicity and to conform to the example of FIG. 4A. In the first block B.sub.1, each of the first bit drivers BD.sub.11 through BD.sub.1n includes a resistor R, transistor Q, diode D, and a constant current source I. This is true for each bit driver in the second block B.sub.2.
In the second block B.sub.2, as previously mentioned, the bit line voltage has a voltage difference of V'.sub.WB =(V.sub.WB -V.sub.BE) relative to the word line voltage. The thus lowered voltage V'.sub.WB must be restored to the nominal voltage V.sub.WB, as in the first block B.sub.1. For this, the level shift means LS is employed. The level shift means LS can be realized by diodes, as exemplified in the bit drivers BD.sub.21 through BD.sub.2n. As is well known, diodes inherently function to shift the voltage level with a level equal to V.sub.BE. Therefore, the bit line level can be lowered by V.sub.BE with the use of the diode LS, and the relative voltage V'.sub.WB can thereby be increased to V.sub.WB. In this regard, it will be apparent that, in a third block (B.sub.3), which is not shown but may follow the block B.sub.2, a similar level shifting means LS should comprise two diodes connected in series for producing a shift level of about 2 V.sub. BE.
FIG. 7 is a circuit diagram of a part of a semiconductor memory device according to a second embodiment of the present invention. FIG. 7 displays only two blocks for simplicity, as in FIG. 4A. In the second embodiment, the word driver transistor Q.sub.wd2 is not directly connected at its base to the first word line segment WL.sub.1, but is connected thereto via a buffer gate circuit BG.sub.1 (T, T' and I). This also applies to the following word driver transistors. Each of the buffer gate circuits BG.sub.1 is a differential transistor pair T and T' and a constant current source I commonly connected to transistor emitters. The base of one (T) of the differential transistor pair is connected to the preceding word line segment, i.e., WL.sub.1, while the base of the other (T') receives a reference voltage V.sub.ref and its collector is connected to the base of the word driver transistor Q.sub.wd2. Due to the presence of the buffer gate circuit BG.sub.1, the voltage at the second word line segment WL.sub.2, i.e., the emitter voltage of the word driver transistor Q.sub.wd2 is not lowered by V.sub.BE, but the word line voltage level of the segment WL.sub.1 is tranferred as it is to the word line segment WL.sub.2. That is, the "H" level of WL.sub.1 during the selection state is the same as the "H" level of the segment WL.sub.2.
The operations are as follows. When the word line WL is not selected, the word driver transistor Q.sub.wd1 is not activated. Accordingly, the level of the segment WL.sub.1 is maintained at the "L" (low) level. Therefore, the transistor T of the differential transistor pair is also not activated. Conversely, the other transistor T' is activated. Thus, the word driver transistor Q.sub.wd2 is not activated. Accordingly, the word line segment WL.sub.2 is also left in the nonselection state and is of the "L" level.
On the other hand, when the corresponding word line WL is selected, the word driver transistor Q.sub.wd1 is activated to increase the voltage level of the segment WL.sub.1 toward the "H" level. Due to the "H" level of the segment WL.sub.1, the transistor T is activated, while the transistor T' is not activated. At this time, the base voltage of the transistor Q.sub.wd2 increases approximately up to the power source level V.sub.cc. Therefore, the voltage level ("H") of the segment WL.sub.2 reaches as high as the voltage level ("H") of the segment WL.sub.1 to hold the selection state i.e. V.sub.cc -V.sub.BE. Thus, each of the word line segments WL.sub.2, WL.sub.3, . . . provides a sufficiently high level of "H" during the selection state. This is true regardless of the number of the segments.
FIG. 8 is a circuit diagram of a part of a semiconductor memory device according to a modification of the second embodiment illustrated in FIG. 7. In the modification, instead of the circuit BG.sub.1 of FIG. 7, a buffer gate circuit BG.sub.2 is used. The circuit BG.sub.2 performs an identical role as the circuit BG.sub.1 mentioned above. That is, the "H" level at the word line segment WL.sub.1 can be transferred, as it is, to the segment WL.sub.2. As seen from FIG. 8, each of the buffer gates BG.sub.2 is comprised of a PNP transistor T.sub.1 and an NPN transistor T.sub.2. The PNP transistor T.sub.1 is connected, at its base, to the preceding word line segment, i.e., WL.sub.1. The output of the PNP transistor T.sub.1 is connected to the NPN transistor T.sub.2 at its base. The output of the NPN transistor T.sub.2 is supplied to the base of the word driver transistor Q.sub.wd2.
When the word line WL is not selected, the word driver transistor Q.sub.wd1 is not activated. Accordingly, the level of the segment WL.sub.1 is maintained at the "L" (low) level. Therefore, the PNP transistor T.sub.1 is activated. Accordingly the NPN transistor T.sub.2 is also activated, and thus the word driver transistor Q.sub.wd2 is not activated. Thus, the word line segment WL.sub.2 is also left in the nonselection state and is of the "L" level.
On the other hand, when the corresponding word line WL is selected, the word driver transistor Q.sub.wd1 is activated to increase the voltage level of the segment WL.sub.1 toward the "H" level. Due to the "H" level of the segment WL.sub.1, the PNP transistor T.sub.1 and the NPN transistor T' are not activated. At this time, the base voltage of the transistor Q.sub.wd2 increases approximately up to the power source level V.sub.cc. Therefore, the voltage level ("H") of the segment WL.sub.2 reaches as high as the voltage level ("H") of the segment WL.sub.1 to hold the selection state i.e. V.sub.cc -V.sub.BE. Thus, each of the word line segments WL.sub.2, WL.sub.3, . . . provides a sufficiently high level "H" during the selection state. This is true regardless of the number of the segments.
As explained above in detail according to the present invention, the current density in each word line can be considerably reduced. Therefore, the width of each word line can be narrowed further. This enables further miniaturization of an IC memory. It should be noted that the introduction of the individual private word drivers and the buffer gate circuits (BG.sub.1 or BG.sub.2) into the IC memory does not obstruct miniaturization because the word lines usually extend in the IC memory with a considerably large length and considerable space can be saved when reducing the widths of such lengthy word lines. The thus saved space is enough to accommodate the word drivers and the buffer gate circuits.
Claims
We claim:
1. A semiconductor memory device, operatively connected to a word decoder which generates a word selection signal at a memory selection time, said memory device comprising: a plurality of memory cells, each of said memory cells comprising a pair of bipolar transistors cross-coupled to form a flip-flop; a plurality of initial word drivers, each operatively connected to the word decoder and activated by the word selection signal from the word decoder; a plurality of bit line pairs operatively connected to said memory cells; a plurality of bit drivers, each operatively and respectively connected to one of said bit line pairs, for specifying a desired one of said memory cells in combination with the word selection signal; a plurality of word lines, operatively and respectively connected to said initial word drivers and said memory cells, forming cross points with said bit line pairs, said memory cells being located at the cross points, each of said word lines being divided into a plurality of word line segments, a first word line segment of each of said word lines being directly activated to carry a word line signal by one of said initial word drivers in dependence upon the word selection signal; segment word drivers operatively connected between the word line segments, one of said segment word drivers being activated when the word selection signal activates a corresponding initial word driver operatively connected via a corresponding first word line segment to the one of said segment word drivers, each of said segment word drivers being formed by a single word driver transistor operatively connected to a following second word line segment and having a base operatively connected to the corresponding first word line segment; and level shifting means, operatively connected to said bit line pairs, for shifting downward bit line voltage levels corresponding to the second word line segments, so that a voltage difference between each of the word line segments and each of said bit lines forming cross points therewith does not vary due to the single word driver transistor in each of said segment word drivers.
2. A device as set forth in claim 1, wherein said level shifting means are provided only in said bit drivers operatively connected to the second word line segments.
3. A device as set forth in claim 2, wherein each of said level shifting means connected to bit line pairs crossing the second word line segments immediately following the first word line segments comprises a single diode operatively connected and corresponding to said bit line pairs crossing the second word line segments immediately following the first word line segments.
4. A device as set forth in claim 3, wherein each of said bit drivers including one of said level shifting means further includes a first bit driver transistor operatively connected to one bit line pair in said bit line pairs crossing the second word line segments and having a base operatively connected to said single diode in said level shifting means included therein.
5. A semiconductor memory device operatively connected to receive a word selection signal, comprising: memory cells arranged in an array having rows and columns, each of the rows being divided into first and second segments; first and second bit selection means, operatively connected and corresponding to the first and second segments in each of the rows of said memory cells, respectively, for selecting one of the columns of said memory cells; word selection means, each of said word selection means operatively connected to an associated one of the rows of said memory cells, for selecting the associated one of the rows of said memory cells in dependence upon the word selection signal, each of said word selection means comprising: a first segment word driver, operatively connected to the first segment of the associated one of the rows of said memory cells and to receive the word selection signal, for driving the first segment of the associated one of the rows of said memory cells in dependence upon the word selection signal; and a second segment word driver, operatively connected to the first and second segments of the associated one of the rows of said memory cells, for driving the second segment of the associated one of the rows of said memory cells when the first segment of the associated one of the rows of said memory cells is driven; and level shift means, operatively connected to said bit selection means corresponding to the columns of said memory cells in the second segment in each of the rows of said memory cells, for changing a voltage level supplied to said bit selection means to adjust for a voltage level change caused by said second segment word driver.
6. A semiconductor memory device as set forth in claim 5, wherein said first segment word driver comprises a first word driver transistor having a base operatively connected to receive the word selection signal and an emitter operatively connected to the first segment of the one of the rows of said memory cells, and wherein said second segment word driver comprises a second word driver transistor having a base operatively connected to the first segment of the one of the rows of said memory cells and an emitter operatively connected to the second segment of the one of the rows of said memory cells.
7. A semiconductor memory device as set forth in claim 6, wherein said bit selection means comprises: first bit drivers, operatively connected to the first segment in each of the rows of said memory cells, for driving the memory cells in the first segment; and second bit drivers, operatively connected to said level shift means and the second segment in each of the rows of said memory cells, for driving said memory cells in the second segment.
Patent Citations (7)
Non-Patent Literature (1)
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