Digital Optical Receiver Circuit

This invention relates to digital optical receiver circuits, and more particularly to such circuits which operate over a wide input dynamic range (e.g. from 3 microwatts/cm.sup.2 to 1.5 watts/cm.sup.2, or 56.9 db) without distorting its output signal. In general, digital optical receiver circuits are designed to operate over a very narrow input dynamic range e.g., 10 db, or with fixed input power level. Such design is commonly used because most optical communications links communicate between fixed distances. Consequently such circuits have a relatively high input sensitivity to permit operation on a low power budget. However, such circuits also tend to overload at input power only slightly greater than the minimal required input because of the large amplification used. An example of such circuit is shown in FIG. 1. Such circuits when overloaded result in seriously distorted output signals due to amplifier saturation. In some cases, such circuits will latch into one logic state for an unpredictable time period, or give an unpredictable, unintelligible output when the specified input levels are exceeded. However, in the case of weapons training systems utilizing laser transmitters mounted on the weapon to simulate the firing of the weapon, such weapon laser may fire at a target over a wide range of distances from point blank range to a range beyond the useful limits of the weapon sight. Under such circumstances, the receiver circuit is inherently subject to a wide dynamic range of incident power levels while a large amount of information is being transmitted by the laser beam. Thus any distortion of the received signal, particularly if it becomes latched-up, will likely cause incorrect decoding or a failure to decode the signal.

Consequently an object of the present invention is a digital optical receiver circuit adapted to operate over a wide input dynamic range without distorting its output signal. Another object of the present invention is such receiver circuit which can operate in full sunlight with a low false output rate due to sun-induced noise. Still another object of the present invention is such receiver circuit which operates from a single power supply with low power consumption. Still another object of the present invention is such receiver circuit which provides a high capacitance output drive capability but permits multiple units to be connected in parallel without affecting its operating characteristics.

In general the present invention involves a digital optical receiver circuit having a first circuit means for receiving and converting high level input signals into output digital signals of extended pulse width similar to those produced by lower level input signals. A second circuit means then receives said similar extended pulse width signals and generates output digital signals of the same pulse width based only on the initial portion of the digital signal received. Preferably the invention includes (a) circuit means for receiving a photodiode generated input signals and passing substantially only output signals to said first circuit means in a selected pulse width range, (b) having the first circuit means include means initiating pulse at a higher voltage than the voltage for terminating the output digital signal pulse and (c) circuit means for buffering the output digital signals of the second circuit means from the load.

In order to facilitate understanding of the present invention, reference will now be made to the drawings showing a preferred specific embodiment of the present invention and a specific example thereof. Such example, like the preceding summary, should not be construed as limiting the present invention which is properly set forth in the appended claims.

FIG. 1 is a schematic drawing of a typical prior out digital optical receiver circuit.

FIG. 2 is a schematic drawing of the preferred embodiment of the digital optical receiver circuit of the present invention.

FIG. 3 is a graph on an illustrative digital signal at various points in the circuit of FIG. 2 when processing a low level input signal.

FIG. 4 is a graph of an illustrative digital signal at various points in the circuit of FIG. 2 when processing a high level input signal.

As shown in FIG. 2, the preferred embodiment of the present invention receives input signal at node A (illustrated in FIG. 3) generated by a photodiode circuit which converts an incoming laser light signal into a complex electrical current pattern whose peaks vary in proportion to the strength of the light signal. Such photodiode circuit, per se, is not part of the present invention but is shown to illustrate an application of the present invention, i.e., a weapon training system digital optical receiver circuit.

Between node A and node B in FIG. 2, the input signal first passes through a high pass filter circuit of R3-C2 wwhich passes only signals above a desired frequency. Next the signal passes through a first amplifier A1, a tuned high-pass network R8-C6 and then a second amplifier A2. The loop from A2 to A1 containing R6A (which may be shorted out) and R6B sets the power consumption of the A1 and A2 combination at a desired minimum level. The resistances R4 and R7 set gain for A1 and A2, respectively to a desired level while C3 and C5 in combination with R4 and R7, respectively, limit the bandwidth of A1 and A2 to form a cutoff frequency above which signals are highly attenuated. The combination of such cutoff circuits and the high pass circuit causes the circuit portion between node A and node B to operate as a bandpass circuit to pass substantially only output in a selected pulse width or input frequency range (e.g. the weapon laser frequency illustrated in FIG. 3). Such circuit portion attenuates all other frequencies including noise voltage signals resulting from current induced by sunlight incident on the photodiode.

Between node B and node C in FIG. 2, the input signal first passes through C8 to remove the direct current offset voltage present at node B. Next the input signal enters the negative input of amplifier A3 and when it is greater than the voltage present at the positive input of amplifier A3, determined by the input biasing circuit including R9, R10 and R11, and the hysteresis action of R13, a negative-going output signal of digital logic amplitude (illustrated in FIG. 3) is produced at node C thereby switching node C from its high logic state to its low logic state and causing the discharge of C10 through amplifier A3. When the input signal terminates, the amplifier A3 then switches "off" and node C slowly returns to its high voltage state as C10 is charged through R14 from the power supply. The resulting digital pulse signal then enters amplifier A4 through C11; however the C11-R15 circuit fully passes only the leading edge of such pulse signal and sharply differentiates (decreases) the remaining portion of such pulse signal. The abbreviated pulse entering A4 causes A4 to produce a normal square digital output pulse at node D (illustrated in FIG. 3).

The foregoing description of the circuit of the present invention describes its operation when a low power input signal is applied. In the case of a high power input signal at node A (illustrated in FIG. 4) the peak signal level is so high that it exceeds the output capability of the combination of A1 and A2 which is limited by their power supply voltage and the internal characteristics of A1 and A2. Consequently, the output signal at node B has a voltage "plateau" near such limit, i.e., the peak portion of the output signal above such limit is "clipped off" and the saturation of the amplifiers A1 and A2 usually "stretches" the output signal pulse width and may cause more than one pulse to appear as illustrated in FIG. 4. Such distorted output signal is transformed by A3 into similar digital logic pulses at node C; however the R14-C10 circuit described above causes the multiple pulses to appear as a single elongated pulse. In turn, the R15-C11 circuit described above passes only the leading edge of such single elongated pulse so that the output signal at node D after passing through A4 is a substantially normal square digital pulse. Such pulse is virtually indistinguishable from the output pulse caused by the low power input signal described above.

Amplifier A4 serves as a buffer which permits the output of the receiver to be connected to a high capacitance load without affecting the operation of the preceding portions of the circuit.

A specific example of the circuit shown as in FIG. 2 is set forth in Table 1 below:

A1 and A2 are the first and second one-half stages, respectively, of the National Semiconductor P/N LM 159 integrated circuit chip. A3 and A4 are the first and second one-half stages, respectively, of the National Semiconductor P/N LM 193 or P/M LM 119 integrated circuit chips. The power supply is 5 volts to 15 volts.

There are many features in the present invention which clearly show the significant advantage which the present invention achieved over the prior art. Consequently only a few of the more outstanding features will be pointed out to illustrate the unexpected and unusual results obtained by the present invention. One feature is that as illustrated by the circuit shown in FIG. 1, the prior art digital optical receiver circuits overload at levels of input only moderately above the power level at which they are designed to operate. When overloaded such circuits may latch-up and provide no intelligible output. The present invention however, can operate over a wide power input dynamic range without distorting its output signal. Another feature of the present invention is that it can operate in full sunlight with a low false output signal rate due to sun-induced noise. Still another feature of the present invention is its high capacitance drive capability and its capability of permitting multiple units to be wired in parallel without affecting the other features of the system. Still another feature of the present invention is its capability of operating from a single power supply voltage with low power consumption.

It will be understood that the foregoing description is only illustrative of the present invention and it is not intended that the invention be limited thereto. All substitutions, alterations, and modifications of the present invention, which come within the scope of the following claims or to which the present invention is readily susceptible without departing from the spirit and scope of this disclosure are considered part of the present invention.