CMOS Precision Voltage Reference Generator

1. Field of the Invention

This invention relates to integrated circuit technology in general, and more particularly, to circuits that generate reference voltage in said technology.

2. Prior Art

Rapid improvements in the development of integrated circuit technology have made it possible for analog and digital circuits to be combined on the same chip. In the past, separate integrated circuit modules were used to package analog and digital circuits, respectively. With separate packaging, one would select a process that optimizes the fabrication of a particular circuit type. However, by combining the two types of circuits on a single chip, it becomes necessary to select a process that at least optimizes the fabrication of the circuits that dominate the chip.

In addition, each type of circuit usually requires unique functions that may not be needed by the other type of circuit. Thus, it is desirable to use a process that optimizes the implementation of these functions.

It has been determined that a "digital CMOS process" is effective in the implementation of mixed circuit (i.e., digital and analog) integrated chips. Usually, the analog circuits in CMOS are a small part of a predominantly digital circuit chip. Thus, the "digital CMOS process" optimizes the implementation of devices that are needed to implement the digital portion of the chip. Devices that are needed to implement analog functions are not available. Thus, a circuit designer is faced with the awesome task of using digitally friendly devices to implement analog functions. Among the many analog functions which a designer must provide is a stable reference voltage.

The generation of a reference voltage using CMOS technology has been done in the past. Known prior art implementation uses two FETs with different threshold voltages. The differential voltage resulting from the different thresholds is the reference voltage. The prior art also teaches that the device threshold voltages can be controlled by ion implantation and different device geometrics. Examples of the prior art teachings are set forth in U.S. Pat. Nos. 4,442,398; 4,305,011; 4,464,588; 4,100,437; 4,327,320; 4,472,871 and 4,453,094.

Even though the prior approach is a step in the right direction it suffers from several defects which the present invention will address and correct. Except for U.S. Pat. No. 4,305,011, the prior art patents do not teach how to convert the differential voltage to a single ended voltage. For most applications, the differential voltage has to be converted to a single-ended voltage before it can be used.

Although U.S. Pat. No. 4,305,011 converts the differential voltage to a single-ended voltage, the magnitude of the single-ended voltage cannot be adjusted. In other words, the single-ended voltage has the same magnitude as the differential voltage. Another problem which is evident in the conversion technique is that switching transients and unwanted clockfeed through signals are present in the single-ended voltage signal.

Other publications addressing CMOS reference voltage generators are:

1. Gray, P. R. and Meyer, R. G., "Analysis and Design of Analog Integrated Circuits," 2nd edition, Wiley, N.Y., 1983, Chapter 12.

2. Blauschild, R. A., et al, "A New NMOS Temperature-Stable Voltage Reference," IEEE JSSC, December, 1978, pp. 767-773.

3. Song, B. S. and Gray, P. R., "A Precision Curvature-Connected CMOS Bandgap Reference," Digest of Papers, 1983, ISSCC.

4. Liu, S., and Nagel, L. W., "Small-Signal MOSFET Models for Analog Circuit Design," IEEE JSSC, December, 1982, pp. 983-998.

5. Gregorian, R. et al, "Switched-Capacitor Circuit Design," IEEE Proceedings, August, 1983, pp. 941-966.

A common problem faced by these designs is that there is a wide variation in the range of threshold voltages. It is believed that the wide variation in threshold voltages is caused by variation in the process used to fabricate the chip. Another common problem is that non-CMOS structures such as bipolar structures are fabricated in the LSI chip. This requires additional process steps which increase the cost of the chip.

It is therefore the primary object of the present invention to provide a CMOS circuit arrangement which establishes an accurate single-ended voltage level that is independent of temperature, power supply voltage, and is minimally affected by process variations.

It is another object of the present invention to drive the CMOS circuit arrangement with a positive power supply.

The circuit arrangement is comprised of a reference voltage generator formed from two enhancement FETs. One of the enhancement FETs has a natural (i.e., unaltered) threshold and the other FET has an altered threshold. The generator provides a double-ended differential voltage signal which is scaled by a switched capacitor amplifier circuit arrangement and is filtered by a supply dependent circuitry to provide an accurate single-ended reference voltage.

The foregoing features and advantages of this invention will be more fully described in the accompanying drawings.

FIG. 1 shows a block diagram of the voltage reference generator circuit according to the teachings of the present invention.

FIG. 2 shows a circuit schematic for a threshold difference generator.

FIG. 3 shows a circuit schematic for a switched capacitor amplifier.

Fig. 4 shows clock pulses which control the amplifier of FIG. 3 and pulses generated by the amplifier.

FIG. 5 shows a circuit schematic of the supply dependent remover.

FIG. 1 shows a block diagram of the voltage reference generator circuit according to the teachings of the present invention. The voltage reference generator circuit includes a threshold difference generator 10, a switched capacitor amplifier 12 and a supply dependent remover 14. The threshold difference generator 10 provides a differential voltage V.sub.RII at nodes A and B, respectively. As will be explained subsequently, the differential voltage at node A and node B is a fixed value set by threshold tailoring implant. The fixed differential voltage (V.sub.RII) is amplified by switched capacitor amplifier 12 and appears at node C as a voltage level proportional to the amplified V.sub.RII. Clocks C1 and C2 are used to switch capacitors (to be described hereinafter) in the switched capacitor amplifier. As will be explained subsequently, the voltage at node C is dependent on the power supply voltage, V.sub.DD. This dependency is removed by the supply dependent remover 14, leaving a voltage that is dependent only on V.sub.RII and component matching characteristics.

FIG. 2 shows a circuit schematic of the threshold difference generator. The threshold difference generator is comprised of a pair of N-channel enhancement mode FET devices Q1 and Q2, a matched pair of current sources 16 and 18 and operational amplifier (op amp) 20. FET device Q1 is connected in series with current source 16. Likewise, FET device Q2 is connected in series with current source 18. The current sources 16 and 18 are connected to the power supply V.sub.DD. The gate electrode of FET device Q1 is connected to the drain electrode and the drain electrode is connected to the inverting input of operational amplifier 20. Likewise, the drain of FET device Q2 is connected to the positive input of amp 20. The differential voltage V.sub.RII which appears at nodes A and B, respectively, is formed by the difference in threshold between transistors Q1 and Q2, respectively. To provide this difference in threshold voltages, the threshold voltage of Q1 is maintained at its natural level while the final threshold voltage of device Q2 is tailored so that digital circuit performance is optimized. As is used in this document, "natural threshold" means the threshold voltage existing before a device is subjected to a threshold tailoring implant process. The threshold tailoring is a process step in which ions are implanted to shift the threshold voltage of a device. It should be noted that the threshold shift could have been implemented on Q1 rather than Q2. In other words, the threshold tailoring implant may be practiced on either Q1 or Q2.

Still referring to FIG. 2, it can be proven mathematically that the voltage difference between nodes A and B is the threshold difference between the natural FET device and the implanted FET device. This is done by writing a set of current equations for Q1 and Q2 and solving them. To write these equations it is assumed that this circuit operates so that Q1 and Q2 are operating in their respective saturation regions and, therefore, their current can be written as:

where:

I.sub.DS =drain-to-source current

V.sub.GS =gate-to-source voltage

V.sub.T =device threshold voltage

V.sub.DS =drain-to-source voltage

.lambda.=channel-shortening coefficient

B.sub.o =(.mu.s K.sub.ox E.sub.o T.sub.ox) (W/L)

.mu.s=surface mobility

K.sub.ox =relative dialectic constant of gate oxide

E.sub.o =permitivity in free space

T.sub.ox =gate oxide thickness

W=channel width

L=channel length

When this equation is used for Q1 and Q2 assuming that the W/L ratio is the same for both transistors and that the operational amplifier has sufficient gain to make the drain voltages of the two FETs equal, we get:

where I.sub.1 and I.sub.2 represent current flowing through Q1 and Q2, respectively. Since I.sub.1 =I.sub.2 =I, we can set the right side of (2) and (3) equal getting:

It should be noted that I represents the current in current sources 16 and 18, respectively.

FIG. 3 shows a circuit diagram for the switched capacitor amplifier 12 (FIG. 1.). The switched capacitor amplifier is comprised of operational amplifier 22. The differential voltage V.sub.RII (FIG. 2) is coupled via switches SW1 and SW2, and capacitor C.sub.I to the negative terminal of the operational amplifier. As will be described subsequently, switch SW1 is driven by clock pulses C1 (FIG. 4) while switch SW2 is driven by the negative phase of clock C1. A voltage divider circuit formed from identical series connected resistors R is connected to V.sub.DD and form a bias voltage at node V.sub.ACG. As will be explained subsequently, node V.sub.ACG is effectively an A.C. ground at voltage level V.sub.DD /2. The output of operational amplifier 22 is tied to node X and a feedback circuit comprising of capacitor C.sub.f and switch SW.sub.3 interconnects node X of the operational amplifier to the negative input terminal. Likewise, switch SW4 interconnects node X to capacitor C.sub.s and output node C.

FIG. 4 shows a graphical representation of clock pulses that are used for driving the switches in FIG. 3 and voltage waveforms that are generated at selected nodes of FIG. 3. In particular, curve A is a representation of clock C1 which is used for driving switch SW1 (FIG. 3). Likewise, curve B represents clock C2 which is used for driving switch SW4 (FIG. 3). Curve C is a graphical representation of the voltage waveform which is outputted at node X (FIG. 3). Finally, curve D shows a graphical representation of the steady state level voltage signal which is outputted at node C (FIG. 3).

Usually, only two voltage levels (V.sub.DD and ground) are available in a digital process such as CMOS. In order for the circuit of FIG. 3 to provide proper amplification, operational amplifier 22 must operate in its linear region. The linearity is assured by biasing the non-inverting input of the operational amplifier between the V.sub.DD and ground levels. This effectively creates an A.C. ground (V.sub.ACG) at the voltage level V.sub.DD /2. The output of the amplifier (node X, FIG. 3) is then an amplified input of (V.sub.A -V.sub.B) riding on the A.C. ground voltage. A graphical representation of this phenomenon is shown in curve C (FIG. 4).

Still referring to FIGS. 3 and 4, capacitors CI and CF must be periodically reset. The resetting procedure is necessary to prevent charge loss due to leakage on capacitors CI and CF, respectively. This is done using CI by closing switch SW3. With switch SW3 closed, CF is shorted, causing node X and the inverting input to operational amplifier 22 to be set at V.sub.ACG. Simultaneously, the voltage at node B is connected to the left plate of capacitor CI via SW2. During the C1 time, switch SW3 and switch SW2 are opened while switch SW1 is closed. The voltage on node A is transferred to the left plate of capacitor C1. The difference between V.sub.A and V.sub.B causes a charge flow in capacitor CF and a resulting output voltage change from V.sub.ACG of:

A graphical representation of .DELTA.V.sub.out is shown in curve C (FIG. 4). Because there is a finite time for node X (FIG. 3) to settle to its final value, the C2 clock is delayed for a period (T2-T1) before turning on. This ensures that the node C voltage is free of glitches. The voltage at node C is shown in curve D (FIG. 4). The voltage may also be described by the following mathematical expression:

Substituting (4) above for (V.sub.A -V.sub.B) gives:

From (7) it is seen that V.sub.C is V.sub.DD dependent. This dependency is removed with the circuit of FIG. 5.

FIG. 5 shows a circuit for removing the V.sub.DD component of the output signal. The circuit is comprised of voltage follower network 26, current mirror network 28 and current mirror network 30.

The voltage follower network 26 includes op amplifier 32 and N-channel FET device Q1. The gate of Q1 is connected to the output of op amplifier 32. The source of Q1 is tied to the inverting input of op amplifier 32 and to ground via resistor R. The configuration ensures that an input voltage V.sub.c appearing at node C is reflected across resistor R.

Still referring to FIG. 5, the drain electrode of FET device Q1 is tied to current mirror network 28. Current mirror network 28 includes P-channel FETs Q2 and Q3. The source electrodes of Q2 and Q3 are tied to supply voltage (V.sub.DD). The current mirror has a gain of two. Other gain ratios may be used without departing from the spirit and scope of the present invention. The gain is achieved by making the width to length (W/L) ratio of Q3 twice the width to length ratio of Q2. Thus, the current (I.sub.1) flowing in Q2 is one-half the current I.sub.2 flowing in Q3. The source drain electrode of Q3 is tied to current mirror network 30. Current mirror network 30 includes N-channel FETs Q4 and Q5. The source electrodes of Q4 and Q5 are tied to ground. The drain electrode of Q5 is coupled through resistor R to supply voltage V.sub.DD and output voltage V.sub.o. Current mirror 30 has a gain of 1. This is achieved by making the width to length ratio of FET devices Q4 and Q5 identical.

The fact that the circuit of FIG. 5 removes the V.sub.DD component of the output voltage V.sub.o can be shown mathematically. With reference to FIG. 5, the input voltage (V.sub.c) is reflected at the source electrode of FET Q1. Thus, the current (I.sub.1) is given by:

because the W/L ratio of Q3 is twice that of Q2.

Transistors Q4 and Q5 form a current mirror made of N-channel FETs such that:

The output voltage is:

Thus, it is shown that V.sub.o is dependent only upon the capacitors ratio and a threshold tailoring implant. These variables can be tightly controlled within the CMOS process.

It is worthwhile noting that best current matching is achieved when the drain voltages of the current mirrors are approximately the same. For example, best matching for I2 and I3 occurs when the drain to source voltage (V.sub.ds4) of Q4=V.sub.o. Cascade stages can also be used to increase the output impedance of the current mirrors.

Although a preferred embodiment of the present invention has been described and disclosed in detail, other modifications and embodiments thereof which would be apparent to one having ordinary skills are intended to be covered by the spirit and scope of the appended claims.