Anisotropic Silicon Etching in Fluorinated Plasma

The present invention relates to the fabrication of integrated circuit devices such as LSI or VLSI semiconductor chips, and more particularly to plasma etch processes designed to define microscopic patterns in such devices.

Many dry etching processes for etching silicon are known, typically involving plasmas in the reactive ion etch (RIE) regime of relatively low pressure, approximately 30-100 microns, and low power density, about 0.01-0.5 watt/cm.sup.2. Recently, much attention has been directed in the semiconductor industry to plasma etching using high pressure, 1 torr and above, and high power density, 2-10 watt/cm.sup.2, resulting in substantially higher etch rates than previously possible.

In plasma etch processes, two removal components contribute to form the resulting etch profile in the target film: a chemical component, due to the chemical reaction of the plasma generated species with the surface material to be removed, and a physical component, due to the momentum transfer of the charged particles formed in the plasma and accelerated through the sheath to the target material. Plasma etch processes carried out in the high pressure regime are distinguished by the much greater importance of the chemical component in etching than in the low pressure RIE processes.

In the conventional fluorinated gas chemistry, as exemplified by U.S. Pat. No. 4,310,380 to Flamm et al., etching is isotropic in nature, with comparable lateral and vertical etch rates in silicon. In the disclosed process the chemical component of the readily dissociated NF.sub.3 ambient is very strong, even in the low pressure RIE type process, where one would normally expect a greater vertical etch rate than lateral rate due to the strength of the physical bombardment. In a high pressure regime, such a gas chemistry will become even more isotropic. While isotropic etching is useful in some silicon etch steps, it is not desirable where deep etching of silicon (3 to 5 microns) of small dimensions is required, such as in isolation trench etching. In such a process, a trench is etched around a transistor or other device which is then filled with a dielectric material to electrically isolate the device. The trench cuts vertically through several layers of differently doped polysilicon or silicon. An etch plasma which uses chlorinated gases to control undercut will undercut each layer a different amount depending on that layer's reactivity with fluorine and chlorine. These and other problems are overcome by the present invention.

One object of the present invention is to provide an improved plasma etching process for silicon, particularly when multiple silicon layers having different doping characteristics are present.

According to one embodiment of the invention, the etchant gas composition includes three major constituents: the etchant species, for example, NF.sub.3 or SF.sub.6 ; an inert gas, such as N.sub.2 ; and a polymerizing gas such as CHF.sub.3. Nitrogen trifluoride (NF.sub.3) readily dissociates in a plasma releasing free fluorine and fluorine-containing radicals in greater quantities than alternate fluorine sources. It is also much safer than ClF.sub.3, BrF.sub.3, or IF.sub.3 which are potentially explosive gases not suitable in a manufacturing environment. In fact, the extremely rapid dissociation of NF.sub.3 in a high pressure plasma proves to cause rather nonuniform etching without the dilution by an inert gas. Nitrogen was found to yield somewhat better uniformity than argon or helium.

The addition of a small amount of a polymerizing gas to the high pressure plasma gives the present process its anisotropic character. The choice of polymerizing gases is determined by the type of mask used. A fluorine-containing gas is preferred for photoresist, aluminum or chromium masks, while a silicon dioxide mask will necessitate the addition of a chlorine-containing gas to the fluorine etchant mixture. In the plasma, the gas will form a polymer which is subsequently conformally deposited on the target suface. In the vertical direction, the polymer is etched away leaving a polymer passivated sidewall. The sidewall is protected from lateral etching and undercutting of the silicon is thus eliminated. In the particular case of trench isolation processing, the etchant species does not attack the sidewall of the differently doped polysilicon and so there is no variable undercut such as that encountered in processes using chlorinated gases to control anisotropy.

FIG. 1 is a cross-sectional view in elevation of a high pressure single wafer reactor used to practice the process of present invention; and

FIG. 2 is a cross-sectional view of a portion of an integrated circuit device etched in accordance with the present invention, specifically, for trench isolation.

In accordance with the principles of the present invention, etching is performed in a high pressure, high plasma density single wafer reactor of the type shown in FIG. 1. The reactor is similar in design to that described in greater detail in the copending U.S. patent application of Chen et al., Ser. No. 623,670, filed June 22, 1984, now U.S. Pat. No. 4,534,816, which is assigned to the present assignee, and is incorporated herein by reference.

Referring now to the drawings, there is shown in FIG. 1 a single wafer reactor 10, wherein a circular, electrically grounded upper electrode 11 is attached to a cylindrical housing 12. Housing 12 has a gas distributing baffle 13, a reactive gas inlet 14, and a cooling fluid inlet (not shown) and outlet 15. This assembly is contained within an insulating housing 16. The lower electrode 17 includes a conductive upper section 18 and an insulating lower section 19. Upper section 18 includes cooling channels 20 and a raised portion surrounded by an insulating ring 21 having gas exhaust channels 21a. The spacing 22 between the upper 11 and lower 17 electrodes is set at approximately 4 mm. An insulating ring 23, which electrically isolates the two electrodes, is formed of conduits 24 for exhausting the gas from the inter-electrode spacing. These conduits 24 open into a gap 25 between inner housing 16 and outer housing 26. The reacted gases are exhausted from the system through a port 27.

FIG. 2 is a greatly enlarged cross-sectional representation of a portion of a silicon wafer showing a trench etched according to the principles of the present invention. A pattern mask layer 28, for example, photoresist, aluminum, chromium or silicon dioxide, is formed on the surface of a heavily n-doped layer 30 of polycrystalline silicon. The mask layer 28, of course, must be resistant to the etching gas mixture. Layer 30 overlies a lightly p-doped monocrystalline silicon layer 32 which is formed on a silicon wafer 34. According to one embodiment of the present invention, the unmasked areas of layers 30 and 32 are etched anisotropically to form a trench 36 having substantially vertical sidewalls. Trench 36 may typically have a width of about 5 microns.

Fluorine-containing polymerizing gases such as CHF.sub.3, C.sub.2 F.sub.4, C.sub.2 F.sub.6 and C.sub.3 F.sub.8 have been found to be advantageous in etching silicon or doped polysilicon through photoresist, aluminum or chromium mask layers. It has been found that a silicon dioxide mask layer required, in addition, an amount of a chlorine containing gas such as CCl.sub.4, CFCl.sub.3, CF.sub.2 Cl.sub.2 or C.sub.2 HCl.sub.3, the latter being a halogenated hydrocarbon containing one or more fluorine atoms.

It is to be understood that the specific sequence of doped or undoped layers are illustrative only, and that any sequence or number or layers of undoped polysilicon, doped polysilicon, and monocrystalline silicon may be etched utilizing the principles of this invention.

In accordance with a preferred embodiment of the present invention, a pressure of about 1 torr is established in plasma reactor 10. The etchant gas is introduced at a total flow rate of about 24 SCCM; 10 SCCM of NF.sub.3, 10 SCCM of N.sub.2, and 4 SCCM of CHF.sub.3. In the single wafer reactor, a power density of about 2 watts/cm.sup.2 is generated at the wafer surface. The upper electrode 11 temperature is maintained at about 0 degrees C., and the temperature of the lower electrode at about -10 degrees C. The silicon wafer is partially masked and placed on the lower electrode 17. For the process conditions specified above, anisotropic etch rates of about 1.6 microns/min. have been observed.

The above example is illustrative only. More generally, etching can be carried out by selecting pressures, total gas flow rates, and power densities in the ranges of 0.5 to 5 torr, 10 to 100 SCCM, and 1 to 10 watts/cm.sup.2, respectively.

While the present invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.