Up/Down Counter Device With Reduced Number of Discrete Circuit Elements

This invention relates to an up/down counter device operating in synchronism with clock signals.

One of the prior art up/down counter devices is a binary up/down counter TC4516BP manufactured by TOSHIBA. This counter TC 4516BP is configured as briefly explained below. The counter comprises one D-type flip-flop, three JK flip-flops, and three logic circuits for forming JK input signals to the JK flip-flops. Clock signals are coupled with the synchronizing signal input terminals of these flip-flops. The D-type flip-flop is short-circuited between the output terminal Q and the data input terminal to form a binary counter. The output signal Q is used as a count signal at the least significant digit, or of the 0th bit. The JK flip-flops are connected, at the JK input terminals, to the three logic circuits. The output signals of the JK flip-flops are used as the count signals of the 1st to the 3rd bits. Each logic circuit comprises two AND gates and an OR circuit coupled with the outputs of the AND gates. One of two AND gates of the first stage logic circuit receives the reversed signals of the output signal Q0 of the D-type flip-flop, and an up/down mode signal U/D while the other AND gate receives the output signal Q0 and the up/down mode signal U/D. The output signal of the OR gate of the first stage logic circuit inputs to the JK input terminal of the first stage flip-flop. The output signal Q1 of the first stage JK flip-flop, the output signal Q0 of the D-type flip-flop and the up/down mode signal U/D are separately applied to one of the AND gates of the second stage logic circuit. The signal Q1, the signal Q0 and the inverted up/down mode signal U/D are applied to the other AND gate. The output signal of the OR gate of the second stage logic circuit is supplied to the JK input terminal of the second stage JK flip-flop. One of the AND gates of the third stage logic circuit receives the output signal Q2 of the second stage JK flip-flop, the output signal Q1 of the first stage JK flip-flop, the output signal Q0 of the D-type flip-flop and the up/down mode signal U/D. The other AND gate receives the signals Q2, Q1, Q0 and U/D. The output signal from the OR circuit of the third logic circuit is supplied to the JK input terminal of the third stage JK flip-flop.

In the prior up/down counter, thus arranged, as the number of stages of logic circuits for providing input signals for the associated flip-flops becomes larger, the input terminals of the AND gates of the logic circuits increase, one by one, in number. For this reason, in constructing the multi-bit counter, the number of the circuit elements required for the logic circuits exponentially increases with an increase in the number of the logic circuits.

Accordingly, an object of this invention is to provide an up/down counter device which can avoid an abnormal increase in the number of the necessary circuit elements when the multi-bit counter is constructed.

To realize this object, an up/down counter device, according to this invention, comprises a binary counter for outputting a count signal representing a bit at the least significant digit, 1st to n-th stage flip-flops at the 1st to n-th significant digits and logic circuits associated with the flip-flops. The output terminal of the binary counter is connected to the first stage logic circuit. The output terminal of the binary counter is connected to the JK input terminals of the first stage flip-flop. An intermediate signal derived from the intermediate portion of the first stage logic circuit is applied to the input terminal of the second stage logic circuit. The output terminal of the second stage logic circuit is connected to the JK input terminal of the second stage flip-flop. The output terminal at the intermediate portion of that logic circuit is connected to the input terminal of the third logic circuit.

The output terminal of the logic circuit is coupled with the JK input terminal of the associated flip-flop. The intermediate signal of the logic circuit serves as an input signal to the next stage logic circuit. The input signal to the upper order flip-flop can be formed by supplying the intermediate signal from each logic circuit to the next stage logic circuit.

FIG. 1 shows a block diagram of an up/down counter device according to an embodiment of this invention;

FIG. 2 shows a circuit diagram of the up/down counter device of FIG. 1;

FIGS. 3 and 4, respectively, show time charts for explaining the up and down count operations of the up/down counter device of FIG. 2;

FIG. 5 shows a graph illustrating the relationship of the number of circuit elements to the number of bits;

FIG. 6 is a circuit diagram of an up/down counter device according to another embodiment of the invention;

FIG. 7 is a circuit diagram of yet another embodiment according to this invention, which is improved in its speed of operation;

FIGS. 8 and 9, respectively, show time charts for explaining the up and down count operations of the up/down counter device of FIG. 7; and

FIG. 10 is a circuit diagram of a further embodiment of this invention which is also improved in its speed of operation.

FIG. 1 illustrates the scheme of an up/down counter device according to this invention. The up/down counter device comprises a counter section 20 including a binary counter 21 and n number of flip-flops 22.sub.1 to 22.sub.n, and a logic section 24 including logic circuits 23.sub.1 to 23.sub.n. A clock signal generator 11 is connected to the counter section 20 to control the operations of the binary counter 21 and all of the flip-flops 22.sub.1 to 22.sub.n. An up/down mode signal generator 12 is connected to the first stage logic circuit 23.sub.1 in the logic section 24 to selectively set up an operation mode of this counter device, i.e., an up count mode or a down count mode. As shown, the output of the binary counter 21 is supplied to the first stage logic circuit 23.sub.1. The output of the logic circuit 23.sub.1 is supplied to the input of the first stage of the flip-flop 22.sub.1. The output of the flip-flop 22.sub.1 is supplied to the input of the second stage logic circuit 23.sub.2. In this way, the output of the n-th logic circuit 23.sub.n is supplied to the input of the n-th flip-flop 22.sub.n. The binary counter 21 frequency-divides a clock signal CK from the clock signal generator 11 into a factor of two and produces a count signal of the 0th bit, or the least significant bit. The logic circuit 23.sub.1 in the logic section 24 receives an up/down mode signal U/D from the up/down mode signal generator 12 and the output signal of the binary counter 21, and produces first and second output signals. The first output signal of the logic circuit 23.sub.1 is fed to the first stage flip-flop 22.sub.1. The second output signal is fed to the second stage logic circuit 23.sub.2. Upon receipt of the first output signal from the logic circuit 23.sub.1, the flip-flop 22.sub.1 produces first and second output signals under control of the clock signal CK from the clock signal generator 11. The first output signal from the flip-flop 22.sub.1 is used as a first bit count signal Q1. The second output signal is applied to the second stage logic circuit 23.sub.2. On the basis of the second output signals from the flip-flop 22.sub.1 and the logic circuit 23.sub.1, the second stage logic circuit 23.sub.2 produces first and second output signals. The first output signal of the logic circuit 23.sub.2 is fed to the second stage flip-flop 22.sub.2. Then, the flip-flop 22.sub.2 produces first and second output signals. The first output signal is used as a second bit signal Q2. The second output signal of the flip-flop 22.sub.2 is fed to the third stage logic circuit 23.sub.3. In this way, the subsequent bit signals Q3 to Qn are produced. The first and second output signals from each stage of the logic circuits 23.sub.1 to 23.sub.n in the logic section 24 will frequently be referred to as final and intermediate signals, respectively. The reason for this is that the final signal is derived from the final stage of each logic circuit, while the intermediate signal is derived from the intermediate portion of the logic circuit. This will be more clearly understood when reading the subsequent detailed description based on the circuit diagrams.

FIG. 2 is a circuit diagram implementing the scheme of the up/down counter device illustrated in FIG. 1. In this example, the up/down counter device is illustrated as a 4-bit counter. A D-type flip-flop is used for the binary counter 21. In the binary counter 21, the complement output terminal Q and the data input terminal are shorted. The output signal Q0 of the binary counter 21 is used as the least significant bit signal, or the 0th bit signal of this counter. The counter section 20 includes three JK flip-flops 22.sub.1 to 22.sub.3. The output signals Q1 to Q3 of the flip-flops 22.sub.1 to 22.sub.3, respectively, serve as the 1st to the 3rd bit signals of the up/down counter device.

The logic section 24 comprises three logic circuits 23.sub.1 to 23.sub.3. The first stage logic circuit 23.sub.1 comprises a first logic circuit portion 23.sub.11, including a NOR gate 31, a NAND gate 32 and an inverter 34, and a second logic circuit portion 23.sub.12 having a NAND gate 33. The second and third stage logic circuits 23.sub.2 and 23.sub.3 each comprise a first logic circuit portion 23.sub.21 (23.sub.31), including a NOR gate 31, a NAND gate 32 and inverters 34 and 35, and a second logic circuit portion 23.sub.22 (23.sub.32) having a NAND gate 33.

In the first stage logic circuit 23.sub.1, the output signal Q0 of the binary counter 21 in the counter section 20, and an up/down mode signal U/D from the up/down mode signal generator 12 (FIG. 1) are applied to the NOR gate 31. These signals Q0 and U/D are also applied to the NAND gate 32. The output signal of the NOR gate 31 is connected through the inverter 34 to the NAND gate 33. The output signal of the NAND gatae 32 is directly connected to the NAND gate 33. The output signal from the NAND gate 33 is applied as a JK input signal to the 1st bit flip-flop 22.sub.1. The output signals of the inverter 34 and the NAND gate 32 are used as the intermediate signals to be transferred to the next stage logic circuit 23.sub.2.

In the next stage logic circuit 23.sub.2, the output signal Q1 of the 1st bit flip-flop 22.sub.1, and the output signal of the inverter 34 in the first stage logic circuit 23.sub.1 are applied to the NOR gate 31. The signal Q1 is applied directly to the NAND gate 32. The output signal of the NAND gate 32 in the logic circuit 23.sub.1 is applied through the inverter 35 to the NAND gate 32. The output signal of the NOR gate 31 is supplied through the inverter 34 to the NAND gate 33. The output signal of the NAND gate 32 is supplied directly to the NAND gate 33. The output signal of the NAND gate 33 is supplied as a JK input signal to the 2nd bit flip-flop 22.sub.2. The output signals of the inverter 34 and the NAND gate 32 are transferred as the intermediate signals to the succeeding stage logic circuit 23.sub.3.

In the logic circuit 23.sub.3, the output signal Q2 of the 2nd bit flip-flop 22.sub.2, and the output signal of the inverter 34 in the second stage logic circuit 23.sub.2 are applied to the NOR gate 31. The signal Q2 is applied directly to the NAND gate 32. The output signal of the NAND gate 32 in the logic circuit 23.sub.2 is applied through the inverter 35 to the NAND gate 32. The output signal of the NOR gate 31 is supplied through the inverter 34 to the NAND gate 33. The output signal of the NAND gate 32 is supplied directly to the NAND gate 33. The output signal of the NAND gate 33 is supplied as a JK input signal to the 3rd bit flip-flop 22.sub.3.

The operation of the up/down counter device, thus arranged, will be given. This device serves as an upcounter when the up/down mode signal U/D is logical "1", and serves as a down-counter when it is logical "0".

The up count operation will be given with reference to FIG. 3, illustrating a timing chart. Since the binary counter 21 frequency divides the clock signal CK into a factor of two, the count signal Q0 has a period two times that of the clock signal CK. When the up/down mode signal U/D is logical "0", the output signal of the NAND gate 32 in the logic circuit 23.sub.1 remains in logical "1", irrespective of a logical state of the output signal of the binary counter 21. The NOR gate 31 serves as an inverter for inverting the output signal Q0 of the binary counter 21. The inverter 34 further inverts the output signal from the NOR gate 31 and applied it to the NAND gate 33. At this time, the output signal of the NAND gate 32 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the inverter 34. Accordingly, the JK input signal supplied from the first stage logic circuit 23.sub.1 to the 1st bit flip-flop 22.sub.1 is out of phase with the signal Q0, i.e., in phase with the signal Q0. When the output signal from the logic circuit 23.sub.1 is logical "1", the flip-flop 22.sub.1 inverts the output signals Q1 and Q1 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q1 of the flip-flop 22.sub.1 is logical "0", and the output signal Q1 is logical "1", the output signal Q1 changes at the trailing edge of the signal Q0, as shown in FIG. 3, and has a period two times that of the output signal Q0 of the binary counter 21.

In the next stage logic circuit 23.sub.2, the NAND gate 32 receives, through the inverter 35, the logical "0" signal output from the NAND gate 32 in the first stage logic circuit 23.sub.1. For this reason, also in this logic circuit 23.sub.2, the output signal of the NAND gate 32 remains in logical "1", irrespective of a logical state of the output signal of the flip-flop 22.sub.1. The NOR gate 31 operates as an inverter for inverting the output signal Q1 of the flip-flop 22.sub.1. The inverter 34 further inverts the output signal from the NOR gate 31 and applies it to the NAND gate 33. At this time, the output signal of the NAND gate 32 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the inverter 34. Accordingly, the JK input signal supplied from the second stage logic circuit 23.sub.2 to the second bit flip-flop 22.sub.2 is out of phase with the signal Q1, i.e., in phase with the signal Q1. When the output signal from the logic circuit 23.sub.3 is logical "1", the flip-flop 22.sub.2 inverts the output signals Q2 and Q2 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q2 of the flip-flop 22.sub.2 is logical "0", and the output signal Q2 is logical "1", the output signal Q2 changes in a logical level at the trailing edge of the signal Q1, as shown in FIG. 3, and has a period four times that of the output signal Q0 of the binary counter 21.

In the succeeding stage logic circuit 23.sub.2, the NAND gate 32 receives, through the inverter 35, the logical "0" signal output from the NAND gate 32 in the second stage logic circuit 23.sub.2. For this reason, also in this logic circuit 23.sub.3, the output signal of the NAND gate 32 remains in logical "1", irrespective of a logical state of the output signal of the flip-flop 22.sub.2. The NOR gate 31 operates as an inverter for inverting the output signal Q2 of the flip-flop 22.sub.2. The inverter 34 further inverts the output signal from the NOR gate 31 and applies it to the NAND gate 33. At this time, the output signal of the NAND gate 32 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the inverter 34. Accordingly, the JK input signal supplied from the third stage logic circuit 23.sub.3 to the third stage flip-flop 22.sub.3 is out of phase with the signal Q2, i.e., in phase with the signal Q2. When the output signal from the logic circuit 23.sub.3 is logical "1", the flip-flop 22.sub.3 inverts the output signals Q3 and Q3 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q3 of the flip-flop 22.sub.3 is logical "0", and the output signal Q3 is logical "1", the output signal Q3 changes in a logical level at the trailing edge of the signal Q2, as shown in FIG. 3, and has a period eight times that of the output signal Q0 of the binary counter 21. In this way, when the up/down mode signal U/D is logical "0", this counter operates as an up-counter, with its counted values incrementing 1, 2, 3, . . . , as shown in FIG. 3.

The down count operation will be given with reference to FIG. 4. Also in this mode, the binary counter 21 frequency-divides the clock signal CK into a factor of two, so that the count signal Q0 has a period two times that of the clock signal CK. When the up/down mode signal U/D is logical "1", the output signal of the NOR gate 31 in the logic circuit 23.sub.1 remains in logical "1", irrespective of a logical state of the output signal of the binary counter 21. Accordingly, the output signal of the inverter 34 is always kept in logical "1". The NAND gate 32 serves as an inverter for inverting the output signal Q0 of the binary counter 21. At this time, the output signal of the inverter 34 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the NAND gate 32. Accordingly, the JK input signal supplied from the first stage logic circuit 23.sub.1 to the 1st bit flip-flop 22.sub.1 is in phase with the signal Q0. When the input signal, or the output signal from the logic circuit 23.sub.1 is logical "1", the flip-flop 22.sub.1 inverts the output signals Q1 and Q1 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q1 of the flip-flop 22.sub.1 is logical "0", and the output signal Q1 is logical "1", the output signal Q1 changes in a logical level at the leading edge of the signal Q0, as shown in FIG. 4, and has a period two times that of the output signal Q0 of the binary counter 21.

In the next stage logic circuit 23.sub.2, the NOR gate 31 receives the logical "1" signal output from the inverter 34 in the first stage logic circuit 23.sub.1. For this reason, in this logic circuit 23.sub.2, the output signal of the NOR gate 31 remains in logical "0", irrespective of a logical state of the output signal of the flip-flop 22.sub.1. The output signal of the inverter 34 connecting to the NOR gate 31 is always kept logical "1". The NAND gate 32 operates as an inverter for inverting the output signal Q1 of the flip-flop 22.sub.1. At this time, the output signal of the inverter 34 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the NAND gate 32. Accordingly, the JK input signal supplied from the second stage logic circuit 23.sub.2 to the second bit flip-flop 22.sub.2 is in phase with the signal Q1. When the output signal from the logic circuit 23.sub.2 is logical "1", the flip-flop 22.sub.2 inverts the input signal or the output signals Q2 and Q2 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q2 of the flip-flop 22.sub.2 is logical "0", and the output signal Q2 is logical "1", the output signal Q2 changes in a logical level at the trailing edge of the signal Q1, as shown in FIG. 4, and has a period four times that of the output signal Q0 of the binary counter 21.

In the logic circuit 23.sub.3, the NOR gate 31 receives the logical "1" signal output from the inverter 34 in the succeeding stage logic circuit 23.sub.2. For this reason, in this logic circuit 23.sub.3, the output signal of the NOR gate 31 remains in logical "0", irrespective of a logical state of the output signal of the flip-flop 22.sub.2. The output signal of the inverter 34 connecting to the inverter 34 is always kept in logical "1". The NAND gate 32 operates as an inverter for inverting the output signal Q2 of the flip-flop 22.sub.2. At this time, the output signal of the inverter 34 is logical "1". Then, the NAND gate 33 serves as a mere inverter for inverting the output signal from the NAND gate 32. Accordingly, the JK input signal supplied from the third stage logic circuit 23.sub.3 to the third stage flip-flop 22.sub.3 is in phase with the signal Q2. When the input signal, or the output signal from the logic circuit 23.sub.3 is logical "1", the flip-flop 22.sub.3 inverts the output signals Q3 and Q3 at the leading edge of the clock signal CK. If, in the initial stage, the output signal Q3 of the flip-flop 22.sub.3 is logical "0", and the output signal Q3 is logical "1", the output signal Q3 changes in a logical level at the trailing edge of the signal Q2, as shown in FIG. 4, and has a period eight times that of the output signal Q0 of the binary counter 21. In this way, when the up/down mode signal U/D is logical "1", this counter operates as a down-counter, with its counted values decrementing 15, 14, 13, . . . , as shown in FIG. 4.

In the up/down counter device thus arranged and operated, two input terminals are provided for each of the logic circuits 23.sub.1 to 23.sub.3 in the logic section 24, to input the JK input signals to the associated flip-flops 22.sub.1 to 22.sub.3, respectively, in the counter section 20. Because of this, in the case of a multi-bit counter, the number of elements constituting the counter device is smaller than that of the prior art device. To construct the counter device of the CMOS type, the total number of elements M is expressed by

where m is the number of bits. If m is 4, for example, the formula (1) gives 164 of the elements necessary for constructing the prior art counter device. The counter device according to this invention needs 166 elements. The former is slightly smaller than the latter. When m=6, the prior device needs 276 elements, while the counter device of this invention needs 262. The former is slightly larger than the latter. For m=10, the counter device of this invention is approximately 100 elements smaller than the prior art device. That is, if the number of bits m is greater, the necessary circuit elements can be remarkably reduced, and a satisfactory effect attained.

The relationship between the number of bits m and the number of elements M is illustrated in FIG. 5. On the graph, a dotted line indicates the relationship of the prior device; a solid line indicates that of the this invention. As seen from the graph, when the number of bits m is below 4, both the counter devices require a substantially equal number of elements. When it is above 4, the number of elements M of the prior device exponentially increases with the number of bits m, while that of the counter device of this invention linearly increases.

FIG. 6 shows another circuit diagram implementing the scheme illustrated in FIG. 1. Like the counter device of FIG. 4, this counter device is also a 4-bit counter. Each of the logic circuits 23.sub.1 to 23.sub.3 is comprised of an AND gate 41, OR gates 42 and 43 and an inverter 44.

In the first stage logic circuit 23.sub.1, the output signal Q0 from the binary counter 21, and the up/down mode signal U/D are applied separately to both the AND gate 41 and the OR gate 42. The output signal of the AND gate 41 is applied directly to the OR gate 43. The output signal of the OR gate 42 is applied through the inverter 44 to the OR gate 43. The output signal of the OR gate 43 is applied as a JK input signal to the first bit flip-flop 22.sub.1. The output signals of the AND gate 41 and the OR gate 42 are supplied to the next stage logic circuit 23.sub.2 in the form of intermediate signals. In the next stage logic circuit 23.sub.2, the output signal Q1 of the flip-flop 22.sub.1, and the output signal of the AND gate 41 in the first stage logic circuit 23.sub.1 are separately applied to the AND gate 41. The signal Q1 and the output signal of the OR gate 42 in the logic circuit 23.sub.1 are separately applied to the OR gate 42. The output signal of the AND gate 41 is applied directly to the OR gate 43. The output signal of the OR gate 42 is applied to the OR gate 43 through the inverter 44. The output signal of the OR gate 43 is supplied as a JK input signal to the second bit flip-flop 22.sub.2. The output signals of the AND gate 41 and the OR gate 42 are applied to the next stage logic circuit 23.sub.3 in the form of intermediate signals. The remaining logic circuit 23.sub.3 has a circuit arrangement similar to that of the logic circuit 23.sub.2.

In the up/down counter device thus arranged, when the up/down mode signal U/D is logical "1", the output signal of the OR gate 42 in each of the logic circuits 23.sub.1 to 23.sub.3 is always in logical "1". Therefore, the Q output signal of the binary counter 21 or lower stage flip-flop, e.g., 22.sub.1 is applied through the associated logic circuit, e.g., 23.sub.1 or 23.sub.2 to the next stage flip-flop, e.g., 22.sub.1 or 22.sub.2, while keeping its logical level. Thus, in this case, the up/down counter device operates as an up-counter device. When the up/down mode signal U/D is logical "0", the output signal of the AND gate 41 in each of the logic circuits 23.sub.1 to 23.sub.3 is always kept in logical "0". Therefore, the Q output signal of the binary counter 21 or lower stage flip-flop, e.g., 22.sub.1 is inverted by the associated logic circuit, e.g., 23.sub.1 or 23.sub.2, and input to the upper stage flip-flop, e.g., 22.sub.1 or 22.sub.2. Thus, this counter device operates as a downcounter device.

Also in this counter, in each logic circuit 23.sub.1, 23.sub.2 or 23.sub.3 for supplying an input signal to the associated JK flip-flop 22.sub.1, 22.sub.2 or 22.sub.3, the AND gate 41 and the OR gate 42 each have two input terminals, situated irrespective of the bit position. Because of this feature, the multi-bit counter device constructed based on this invention requires a smaller number of circuit elements than the prior device.

For example, the up/down counter device may be a counter device of more than 4 bits, although the 4 bit counter device was used in the above-mentioned embodiment.

As seen from the foregoing description, in the up/down counter device according to this invention a count signal at the 0th bit, as the least significant bit, is obtained by frequency dividing a clock signal into a factor of 2 by a binary counter. When an input signal to the counter device is in a logical level, the logical state of the output signal from the counter device is inverted by flip-flops of n in synchronism with the clock signal, thereby obtaining count signals at the 1st to the n-th significant bits. Logic circuits of n stages are provided. The first stage logic circuit is connected between the binary counter and the first significant bit flip-flop. The remaining logic circuits are each between the adjacent flip-flops. The first stage logic circuit receives an output signal from the binary counter, and the up/down mode signal U/D to form an input signal to the next more significant bit flip-flop. Each of the logic circuits other than the first stage logic circuit receives the intermediate signal from the preceding stage logic circuit, and the output signal from the flip-flop associated with the preceding stage logic circuit. To form an input signal to the flip-flop associated with the present logic circuit. For constructing a multi-bit counter device, this invention requires a smaller number of circuit elements than the prior art.

Reference is made to FIG. 7, illustrating another circuit diagram of the up/down counter device of FIG. 1. A clock signal CK is applied to the synchronizing input terminals of a D-type flip-flop 51 and JK flip-flops 51 to 54. The output terminal Q and the data input terminal of the D-type flip-flop 51 are shorted to form a binary counter. The Q output signal Q0 is used as the 0th bit count signal, i.e., the count signal of the least significant bit. The JK flip-flops 51 to 54 receives, at the J and K input terminals, the output signals of logic circuits 55 to 57, respectively. The output signals Q1 to Q3 of the flip-flops 52 to 54 are used as the first to third bit count signals.

The logic circuit 55 is inserted between the D-type flip-flop 51 and the JK flip-flop 52. The logic circuit 55 is comprised of a NAND gate 61, a NOR gate 62, an inverter 63 and a NAND gate 64. The gates 61 and 62 receive the output signal Q0 of the D-type flip-flop 51, and an up/down mode signal U/D. The output signal of the NAND gate 61 is applied directly to the NAND gate 64. The NAND gate 64 also receives the output signal of the NOR gate 62, via the inverter 63. The output signal of the NAND gate 64 is applied as J and K input signals to the JK flip-flop 52.

The next stage logic circuit 56 is inserted between the JK flip-flops 52 and 53. The logic circuit 56 is comprised of a NOR gate 71, a NAND gate 72, an inverter 73, and a NAND gate 74. The NOR gate 71 receives the output signals of the NAND gate 61 and the JK flip-flop 52. The NAND gate 72 receives the output signals of the NOR gate 62 and the JK flip-flop 52. The NAND gate 74 is supplied with the output signal of the NAND gate 72 as well as the output signal of the NOR gate 71 through the inverter 73. The output signal of the NAND gate 74 is applied as J and K input signals to the JK flip-flop 53.

The next stage logic circuit 57 is inserted between the JK flip-flops 53 and 54. The logic circuit 57 is comprised of a NOR gate 71, a NAND gate 72, an inverter 73 and a NAND gate 74. The NOR gate 71 receives the output signal of the NAND gate 72 and the output signal Q2 of the JK flip-flop 53. The NAND gate 72 receives the output signal of first NOR gate 71 of the logical circuit 56, and the output signal Q2 of the JK flip-flop 53. The output signals of the NAND gate 72 and the NOR gate 71 are applied through the inverter 73 to the NAND gate 74. The output signal of the NAND gate 74 is applied as J and K input signals to the JK flip-flop 54.

The logic circuit 55 receives the output signal Q0 of the D-type flip-flop 51, and the up/down mode signal U/D, and forms an input signal to the JK flip-flop 52. The next stage logic circuit 56 receives the intermediate signals of the logic circuit 55, i.e., output signals of the NAND gate 61 and the NOR gate 62, and the output signal Q1 of the JK flip-flop 52, and forms an input signal to the JK flip-flop 53. The logic circuit 57 receives the intermediate signals of the logic circuit 56, i.e., output signals of the NAND gate 61 and the NOR gate 62, and the output signal Q2 of the JK flip-flop 53, and forms an input signal to the JK flip-flop 54. Thus, the output signal Q0 of the D-type flip-flop 51 is applied to the logic circuit 55. The output signal Q of the JK flip-flop 52 is applied to the logic circuit 56. The output signal Q2 of the JK flip-flop 53 is applied to the logic circuit 57. Thus, the output signals Q and Q from the flip-flops 51 to 53 are alternately applied to the logic circuits 55 to 57, as shown.

The operation of the up/down counter device, thus arranged, will be given. The up/down counter device is set to an up count mode by setting the up/down mode signal U/D to logical "1", while it is set to a down count mode by setting that signal to logical "0".

The up count operation of the counter device will be given with reference to FIG. 8. The D-type flip-flop 51 frequency-divides the clock signal CK into a factor of two. Accordingly, the output signal Q0 has a period two times that of the clock signal CK. At this time, the up/down mode signal U/D is logical "1", and in the logic circuit 55, the output signal of the NOR gate 62 remains in logical "0", irrespective of the logical state of the output signal of the flip-flop 51. The NAND gate 61 inverts the output signal Q0 of the D-type flip-flop 51 and applies it to the NAND gate 64. Since the output signal of the NOR gate 62 is logical "0", and the output signal of the inverter 63 connecting to it is logical "1", the NAND gate 64 serves as an inverter for inverting the output signal of the NAND gate 61. Accordingly, the J and K input signals to the JK flip-flop 52 are in phase with the signal Q0. The JK flip-flop 52 for producing the first bit count signal Q1 inverts its output at the leading edge of the clock signal CK when the output signal of the logic circuit 55 is logical "1". If, in the initial stage, the output signal Q1 of the JK flip-flop 52 is logical "0" , the signal Q1 changes at the trailing edge of the signal Q0, and has a period two times that of the signal Q0, as shown in FIG. 8.

In the logic circuit 56, the NAND gate 72 receives the logical "0" signal output from the NOR gate 62 in the logic circuit 55 so that the output signal of the NAND gate 72 is kept in logical "1". The NOR gate 71 serves as an inverter for inverting the complement output signal Q of the JK flip-flop 52, and connects its output for transfer to the NAND gate 74, serving as an inverter. Accordingly, the JK input signal supplied from the logic circuit 56 to the JK flip-flop 53 is out of phase with the signal Q of the JK flip-flop 52, that is, in phase with the signal Q thereof. The JK flip-flop 53 inverts its output at the leading edge of the clock signal CK when the output signal of the logic circuit 56 is logical "1". If, in the initial stage, the output signal Q2 of the JK flip-flop 53 is logical "0", the signal Q2 changes at the trailing edge of the signal Q1 and has a period four times that of the signal Q0, as shown in FIG. 8.

In the logic circuit 57, the NOR gate 71 receives the logical "1" signal output from the NAND gate 72 in the logic circuit 56. Accordingly, the output signal of the NOR gate 71 is kept in logical "0", and the output signal of the inverter 73 connecting to it is kept logical "1". The NAND gate 72 serves as an inverter for inverting the output signal Q2 of the JK flip-flop 53, with its output signal supplied to the NAND gate 74 serving as an inverter. Therefore, the J and K input signals supplied to the JK flip-flop 54 are in phase with the signal Q2. The JK flip-flop 54 inverts its output signal at the leading edge of the clock signal CK when the output signal of the logic circuit 56 is logical "1". If, in the initial stage, the output signal Q3 of the JK flip-flop 54 is logical "0", the signal Q3 changes in a logical level at the trailing edge of the signal Q2 and has a period eight times that of the signal Q0, as shown in FIG. 8.

In this way, the up/down counter device operates as an up-counter when the up/down mode signal U/D is logical "1", and its count is incremented step by step, as shown in FIG. 8.

The down count operation of the counter device will be given with reference to FIG. 9. The D-type flip-flop 51 frequency-divides the clock signal CK into a factor of two, as in the up-count operation. Accordingly, the output signal Q0 has a period two times that of the clock signal CK. At this time, the up/down mode signal U/D is logical "0", and then, in the logic circuit 55, the output signal of the NAND gate 61 remains in logical "1", irrespective of a logical state of the output signal of the NAND gate 61. The NOR gate 62 inverts the output signal Q0 of the D-type flip-flop 51 and applies it to the NAND gate 64, via the inverter 63. Accordingly, the J and K input signals supplied from the logic circuit 55 to the JK flip-flop 52 are out of phase with the signal Q0. The JK flip-flop 52 for producing the first bit count signal Q1 inverts its output at the leading edge of the clock signal CK when the output signal of the logic circuit 55 is logical "1". If, in the initial stage, the output signal Q1 of the JK flip-flop 52 is logical "0", the signal Q1 changes at the leading edge of the signal Q0 and has a period two times that of the signal Q0, as shown in FIG. 9.

In the logic circuit 56, the NOR gate 71 receives the logical "1" signal output from the NAND gate 61 in the logic circuit 55, so that the output signal of the NOR gate 71 is kept in logical "0". The output signal of the inverter 73 connecting to it is kept in logical "1". The NAND gate 72 serves as an inverter for inverting the output signal Q1 of the JK flip-flop 52, and connects its output for transfer to the NAND gate 74 serving as an inverter. Accordingly, the JK input signal supplied from the logic circuit 56 to the JK flip-flop 53 is in phase with the signal Q1. The JK flip-flop 53 inverts its output at the leading edge of the clock signal CK when the output signal of the logic circuit 56 is logical "1". If, in the initial stage, the output signal Q2 of the JK flip-flop 53 is logical "0", the signal Q2 changes at the leading edge of the signal Q1 and has a period four times that of the signal Q0, as shown in FIG. 9.

In the logic circuit 57, the NAND gate 72 receives the logical "0" signal output from the NOR gate 71 in the logic circuit 56. Accordingly, the output signal of the NAND gate 72 is kept in logical "0". The NOR gate 71 serves as an inverter for inverting the output signal Q2 of the JK flip-flop 53, with its output signal supplied, via the inverter 73, to the NAND gate 74 serving as an inverter. Therefore, the J and K input signals supplied from the D-type flip-flop 51 to the JK flip-flop 54 are out of phase with the signal Q2. The JK flip-flop 54 inverts its output signal at the leading edge of the clock signal CK when the output signal of the logic circuit 56 is logical "1". If, in the initial stage, the output signal Q3 of the JK flip-flop 54 is logical "0", the signal Q3 changes at the trailing edge of the signal Q2 and has a period eight times that of the signal Q0, as shown in FIG. 9.

In this way, the up/down counter device operates as a down-counter when the up/down mode signal U/D is logical "0", and its count is decremented step by step, as shown in FIG. 9.

With such an arrangement of the up/down counter device, in each logic circuit for applying the input signal to the associated JK flip-flop, the number of the input terminals of each of the gates 71 and 72 is two, irrespective of the bit position. Therefore, the multibit counter can be constructed without abnormally increasing the number of circuit elements.

It is further noted that the up/down mode signal U/D passes through only one NOR gate or NAND gate when it selects either the up or down count mode of the counter device. Though an erroneous operation of the counter device of FIG. 2 frequently occurs when the counter device operates under control by a high rate clock signal CK, this feature shifts the erroneous operating point to a higher frequency side. Therefore, the up/down counter device of this embodiment can be operated at a high speed.

FIG. 10 shows a further circuit diagram of the FIG. 1 circuit according to this invention. In the counter device of FIG. 10, the logic circuit 55 receives the output signal Q0 of the D-type flip-flop 51, and the up/down mode signal U/D, and forms an input signal to the JK flip-flop 52. The logic circuit 56 receives the intermediate signals of the logic circuit 55, and the output signal Q1 of the JK flip-flop 52 and forms an input signal to the JK flip-flop 53. The next stage logic circuit 57 receives the intermediate signals of the logic circuit 56, and the output signal Q2 of the JK flip-flop 53 and forms an input signal to the JK flip-flop 54. The output signal Q0 of the D-type flip-flop 51 is supplied to the logic circuit 55. The output signal Q1 of the JK flip-flop 52 is supplied to the logic circuit 56. The output signal Q2 of the JK flip-flop 53 is connected to the logic circuit 57. Thus, the output signals Q and Q of these flip-flops 51 to 53 are alternately applied to the three logic circuits 55 to 57.

This up/down counter device operates as a down counter for logical "1" of the up/down mode signal U/D, and as an up counter for logical "0" of the signal U/D. The up and down operations of this counter device will be omitted since the operations are as illustrated in FIGS. 8 and 9.