Asynchronous Demand Selector With Multi-Tape Delay Line

1. Apparatus for controlling a read-write memory having refresh requirements in response to asynchronous read, write and refresh command signals comprising first gate means responsive to the asynchronous read and write command signals, second gate means responsive to the asynchronous read, write and refresh command signals, first circuit means for simultaneously periodically enabling said first and second gate means, said first gate means deriving a first output signal in response to the first gate means being responsive to a read command signal or a write command signal while enabled, said second gate means deriving a second output signal in response to the second gate means being responsive to a read command signal or a write command signal or to a refresh command signal while enabled, multi-tap delay line means having an input terminal responsive to the second output signal and multiple output taps 2, 3, . . . k . . . n at which delayed signals are derived in sequence, where k is selectively each of plural intermediate output taps between taps 3 and n, and n is the last output tap, first and second flip-flops respectively responsive to the first output signal and the refresh command signal while the first and second gate means are enabled and simultaneously responsive to a first timing signal at output tap 2, the delay line having a delay time from the input terminal to output tap 2 commensurate with a predetermined preparation time of the first and second flip-flops, said first and second flip-flops being respectively driven to states commensurate with the first output signal and the refresh command signal while the first and second gate means are enabled at the time the first and second flip-flops respond to the first timing signal, said first circuit means being connected to tap 3 for disabling the first and second gates means in response to a second timing signal derived at tap 3, third and fourth flip-flops respectively responsive to the states of the first and second flip-flops and to a third timing signal derived at a predetermined first one of the k output taps, said third and fourth flip-flops being respectively driven to states commensurate with the states of the first and second flip-flops at the time the third timing signal is derived, third gate means responsive to the states of the third and fourth flip-flops and to a fourth timing signal at a predetermined another one of the k output taps and a fifth timing signal at tap n for deriving synchronized read, write, refresh and no refresh command signals for the memory, the synchronized to refresh signal being derived by the third gate means in response to the fourth timing signal being derived while the third and fourth flip-flops are both in first states commensurate with the unsynchronized read or write signal and the refresh signal being supplied to the apparatus, the synchronized refresh signal being derived by the third gate means in resonse to the fourth timing signal being derived while the third flip-flop is in a second state commensurate with neither the unsynchronized read nor write signal being supplied to the apparatus and the unsynchronized refresh signal being supplied to the apparatus, the synchronized write signal being derived by the third gate means in response to one of the fourth or fifth timing signals being derived while the third flip-flop is in said first state thereof, the synchronized rear signal being derived by the third gate means in response to the other of the fourth or fifth timing signals being derived while the third flip-flop is in said first state thereof, the remaining k taps deriving (k-2) timing signals having a predetermined spacing, said (k-2) timing signals being supplied as input signals to said memory to provide synchronized clocking or signals stored in the memory.

2. Apparatus for controlling a main memory unit of a data processor in response to asynchronous command signals supplied to the data processor by N processor units, where N is an integer greater than one, the main memory unit being divided into N segments so that each segment stores data for a different one of the N processor units, comprising first selectively enabled gate means connected to be simultaneously responsive to the command signals for selectively deriving while enabled (i) N first signals respectively indicative of the presence of the N command signals and (ii) a single second indicative of the presence of any one of the N command signals, first circuit means for periodically enabling said gate means, multi-tap delay line means having an input terminal responsive to the second signal and multiple output taps 2, 3, . . . k . . . n at which delayed signals are derived in sequence, where k is selectively each of plural intermediate output taps between taps 3 and n, and n is the last output tap, N first flip-flops respectively responsive to the N first signals and simultaneously responsive to a first timing signal at output tap 2, the delay line having a delay time from the input terminal to output tap 2 commensurate with a predetermined preparation time of the N first flip-flops, said first N flip-flops being respectively driven to states commensurate with values of the N first signals at the time the N first flip-flops respond to the signal at tap 2, said first circuit means connected to tap 3 for disabling the first gate means in response to a second timing signal derived at tap 3, N second flip-flops respectively simultaneously responsive to the states of the first N flip-flops and to a third timing signal derived at a predetermined first one of the k outut taps, said N second flip-flops being respectively driven to states commensurate with the states of the corresponding N first flip-flops at the time the third timing signal is derived, second gate means simultaneously responsive to N additonal signals derived in response to the states of the N second flip-flops for simultaneously deriving N further signals all of which, except one, have the same value, the excepted further signal being corresponding to the processor unit that is to be controlled by the memory unit, the second gate means being responsive to an additional timing signal derived at one of the k output taps, the N further signals being coupled to the memory unit to enable only the segment of the memory unit corresponding to the processor to be controlled, said delay line means deriving further timing signals having a predetermined spacing, said further timing signals being coupled to the memory unit to provide synchronized clocking of pograms stored in the memory unit.

3. The apparatus of claim 2 further including a priority selection circuit responsive to states of the second flip-flops for deriving multiple input signals for the second gate means.