Passive Phase Shifter Having Switchable Filter Paths to Provide Selectable Phase Shift

This invention relates generally to radio frequency circuits and more particularly to radio frequency circuits which provide a selective phase shift to a signal propagating therethrough.

As is known in the art, phase shifter circuits are employed in various radio frequency (r.f.) applications such as phased array antenna systems. One type of phase shifter, a passive phase shifter 10 is shown in FIG. 1 and includes passive elements which provide a phase lag and a phase lead network and includes a pair of signal paths provided between an input terminal RF IN and an output terminal RF OUT with the upper one of the signal paths being through a high pass filter 14 to provide phase lead or positive phase shift to a signal and the lower one of the signal paths being through a low pass filter 18 to provide phase lag or negative phase shift to a signal. Typically, a pair of switches 12, 16 are used to couple a signal between the input and output terminals through a selected one of said filter networks. Often, a pair of field effect transistors are arranged to provide active switching elements of each one of said switches. Field effect transistors are employed in these applications because they are easily formed as part of monolithic integrated circuits unlike other types of active switching devices such as pin diodes. A problem with the approach shown in FIG. 1 is that the input RF signal coupled between the input terminal and the output terminal first passes through the input switch 12 and thus a selected one of the input switching field effect transistors thereof, a first selected one of the high and low pass filter sections, and the output switch 16 and thus a selected one of the output switching field effect transistors before reaching the output terminal. That is, the input signal is cascaded through an input switching field effect transistor, a selected filter section and an output switching field effect transistor. Since each one of said field effect transistors has a finite bandwidth, the overall bandwidth of the circuit will be less than the intrinsic bandwidth of the filter section alone.

An additional problem with this approach is that in the "off state" field effect transistors generally have a very large drain-source capacitance which permits a portion of the input signal to be coupled between the input and output terminals through the "unselected" filter section. This generally causes phase distortion in the output signal. Generally, therefore, this large capacitance must be compensated for by tuning or resonating the capacitance. However, this solution generally reduces the bandwidth of the phase shifter from that of the theoretical bandwidth of the passive network.

Further, with this approach, impedance matching networks (not shown) are generally required at the input and output of each FET. This results in a loss in bandwidth, increased insertion loss and increased complexity and size of the phase shifter circuit.

In accordance with the present invention, two sets of field effect transistors is provided, each set of field effect transistors comprising three field effect transistors connected in a T-configuration. Two of the field effect transistors in each set has a drain electrode of one transistor coupled to a source electrode of the other transistor to provide a series element of the T-configured set. The third transistor has a first one of the drain and source electrodes coupled to the common connection of the pair of transistors and the second one of drain and source electrodes coupled to ground to form a shunt element of the T-configured set. The series element of a first one of the sets of field effect transistors is capacitively coupled between input and output terminals of the network, and the series element of the second set of field effect transistors is inductively coupled between the input and output terminals of the network. One of a pair of complementary control signals is fed to each one of the gate electrodes of each field effect transistor. Gate electrodes of the series element of a first one of the sets of field effect transistors and the gate electrode of the shunt element of the other one of the pair of sets of field effect transistors are each fed the same one of the pair of complementary control voltage signals. In response to a first state of said pair of control signals, the network is configured to provide a low pass filter having a first phase shift characteristic as a function of frequency over a predetermined operating frequency range. In response to a second, different state of said set of control signals, the network is reconfigured to provide a high pass filter section having a second, different predetermined phase shift characteristic as a function of frequency over a predetermined operating frequency range. The difference in phase characteristic of the network configured as a low pass filter and as a high pass filter is provided to be relatively constant over the predetermined frequency range. With this arrangement, a phase shift bit having a relatively constant phase shift over the predetermined frequency range is provided. Further, by providing the field effect transistors in two sets of T-configured transistors, the external switching circuits are eliminated and concomitant loss in bandwidth generally associated with such external switches in passive phase shifters is substantially reduced. Further, the capacitance in the "off state" of the field effect transistors becomes part of the phase shift network eliminating tuning circuitry also associated with external switching. Further still, by eliminating the external switches, at least one impedance matching network is eliminated at the input and output of the phase shifter.

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which:

FIG. 1 is a schematic diagram of a typical prior art passive phase shifter having high and low pass filter sections;

FIG. 2 is a schematic diagram of a phase shifter having a reconfigurable phase shift network in accordance with the present invention;

FIG. 3 is an equivalent circuit of the phase shift network of FIG. 2 provided in response to a first state of a pair of control signals fed to the network;

FIG. 4 is a simplified equivalent circuit of FIG. 3;

FIG. 5 is a second equivalent circuit of the phase shift network of FIG. 2 provided in response to a second, different state of the pair of control signals;

FIG. 6 is a simplified equivalent circuit of FIG. 5; and

FIG. 7 is a typical plot of the variation of phase with respect to frequency of the phase shifter of FIG. 2 when configured as a high pass filter section and when configured as a low pass filter section.

Referring now to FIG. 2, a phase shifter 20 is shown to include a reconfigurable network 30. The reconfigurable network 30 is coupled between an input impedance matching network 22 and an output impedance matching network 24. The reconfigurable network 30 includes a plurality of here six field effect transistors, FET 1 to FET 6, each field effect transistor having drain electrodes D.sub.1 to D.sub.6, source electrodes S.sub.1 to D.sub.6 and gate electrodes G.sub.1 to G.sub.6, respectively. Each one of the field effect transistors FET 1 to FET 6 is connected in a resistive switching mode, that is, one of a pair of complementary bias signals is applied to the gate electrodes G.sub.1 to G.sub.6 of FET 1 to FET 6 to bias the gate electrode and to change the impedance between the drain and source electrodes of the respective FET. The drain electrodes D.sub.1 to D.sub.6 and source electrodes S.sub.1 to S.sub.6, however, are left unbiased. In this manner, the FET provides in response to the gate bias signal applied to the gate electrode, a relatively high impedance between source and drain electrodes in response to a first state of such signal, or alternatively, a relatively low impedance between source and drain electrodes in response to a second, different state of such bias signal. Network 30 includes a pair of terminals, an input terminal 32 (RF.sub.IN) and an output terminal 34 (RF.sub.OUT). A pair of electrical signal paths 31a, 31b are provided to electrically couple terminals 32 and 34. Electrical signal path 31a includes a capacitor C.sub.1 coupled at a first end to terminal 32, and further includes FET 1 and FET 2 and a capacitor C.sub.2 serially coupled together between the second end of capacitor C.sub.1 and terminal 34. That is, the drain electrode D.sub.1 of field effect transistor FET 1 is coupled to the second end of capacitor C.sub.1, source electrode S.sub.1 of FET 1 is coupled to drain electrode D.sub.2 of FET 2, and source electrode S.sub.2 of FET 2 is coupled to a first end of the capacitor C.sub.2 with the second end of capacitor C.sub.2 being coupled to output terminal 34. The electrical signal path 31a also includes a first shunt path having FET 3 with drain D.sub.3 and source S.sub.3 electrodes coupled between the common connection of FET 1, FET 2 and a common reference potential, here ground. Therefore, FET 1, FET 2 and FET 3 are arranged in a first T-section with FET 1, FET 2 coupled in series and FET 3 coupled in shunt between the common connection of FET 1, FET 2 and ground. A second shunt path having a section of transmission line T.sub.1 with a predetermined inductance per unit length is provided between the common connection of FET 1 and FET 2 and ground, as shown.

Electrical signal path 31b includes a transmission line T.sub.2 having a predetermined inductance per unit length coupled between terminal 32 and drain electrode D.sub.4 of FET 4. FET 4, FET 5 and FET 6 are similarly arranged in a T-section configuration with FET 4 and FET 5 coupled in series, and FET 6 coupled in shunt between the common interconnection of FET 4 and FET 5 and ground, as shown. Further, FET 4 and FET 5 are each connected in shunt across one of a pair of transmission line sections T.sub.3 and T.sub.4, each having a predetermined inductance per unit length, as shown. A transmission line section T.sub.5 having a predetermined inductance per unit length is coupled between output terminal 34 and the interconnection of transmission line section T.sub.4 and source electrode S.sub.5 of FET 5, as shown.

The input impedance matching circuit 22 is here a ladder network having three shunt paths to ground through capacitors C.sub.3 , C.sub.4 and C.sub.5, with transmission lines T.sub.6, T.sub.7 and T.sub.8 forming series inductive elements of such ladder network. The input impedance matching circuit 22 is adapted for coupling to an input source 21 of radio frequency energy (V.sub.s). Similarly, the output impedance matching circuit 24 is a ladder network having three shunt paths to ground, here via capacitors C.sub.6, C.sub.7 and C.sub.8, with transmission lines T.sub.9, T.sub.10 and T.sub.11 here forming the series inductive elements of such ladder network. The output matching circuit is adaptable for coupling to a load 25. All of the transmission line sections T.sub.1 -T.sub.11 are here microstrip type transmission lines. Each one of such microstrip transmission lines is selected to provide a predetermined inductive reactance, as is known in the art.

Gate electrodes G.sub.1 -G.sub.6 of FET 1-FET 6 are each fed by one of a pair of complementary control signals provided on lines V.sub.1, V.sub.1 from a bias control source V.sub.B. Gate electrodes G.sub.1, G.sub.2 and G.sub.6 are coupled through corresponding ones of gate bias resistors R.sub.G1, R.sub.G2, R.sub.G6 to the control signal line V.sub.1. A control signal on line V.sub.1 selectively places FET 1, FET 2 and FET 6 in an "on" or in a relatively low impedance state between corresponding drain and source electrodes in response to a first state of such signal or alternatively places FET 1, FET 2 and FET 6 in a "pinch-off" or in a relatively high impedance state in response to a second, different state of the control signal. The gate electrodes G.sub.3, G.sub.4 and G.sub.5 of FET 3, FET 4 and FET 5, respectively, are coupled through resistors R.sub.G3, R.sub.G4, R.sub.G5 to the bias control signal line V.sub.1. Similarly, in response to complementary control signal V.sub.1, FET 3 to FET 5 are placed either in an "on" or a relatively low impedance state or a "pinch-off" or a relatively high impedance state, as described above. Operation of the phase shifter 20 will now be described in conjunction with FIGS. 3-7.

Referring now to FIGS. 3 and 4, an equivalent circuit 30a (FIG. 3) of phase shift section 30 (FIG. 2) is shown. This configuration 30a of network 30 (FIG. 2) is provided by feeding a signal on bias control signal line V.sub.1 to gate electrodes G.sub.1, G.sub.2 and G.sub.6 to switch the corresponding FET 1, FET 2 and FET 6 into an "off" or a relatively high impedance state. In such state, FET 1, FET 2 and FET 6 are represented by capacitors C.sub.X1, C.sub.X2, and C.sub.X6 having a relatively low capacitance and hence a relatively high impedance over the operating frequency band. Conversely, a signal is fed on control line V.sub.1 to gate electrodes G.sub.3 to G.sub.5 of FET 3 to FET 5 to place FET 3 to FET 5 in an "on" or a relatively low impedance state. In such state, FET 3 to FET 5 are represented by resistors R.sub.X3 to R.sub.X5. The equivalent resistance of FET 3-FET 5 represented by resistors R.sub.X3 to R.sub.X5 are relatively low in impedance (approximately equal to 0 ohms), and equivalent capacitors C.sub.X1, C.sub.X2 and C.sub.X3 are of relatively low capacitance such that the reactance of C.sub.X1, C.sub.X2, and C.sub.X3 are of a relatively high impedance at the frequency of the input signal. Therefore, the equivalent circuit 30a of FIG. 3 may be simplified to an equivalent circuit 30a' as shown in FIG. 4. That is, resistor R.sub.X3 will provide a low impedance path to ground, substantially shorting out transmission line T.sub.1, and providing a first shunt path to ground through series connected capacitors C.sub.1 and C.sub.X1, and a second shunt path to ground through series connected capacitors C.sub.2 and C.sub.X2. On the other hand, resistors R.sub.X4 and R.sub.X5 will provide relatively low impedance paths (approximately equal to 0 ohms) across transmission line sections T.sub.3 and T.sub.4, thereby providing a relatively low impedance path between transmission line T.sub.2 and transmission line T.sub.5, as shown. A third shunt path to ground is provided by capacitor C.sub.X6 as shown in FIG. 4. The equivalent circuit 30a' as shown in FIG. 4 is that of a five element low pass filter. By properly selecting the values of capacitance of C.sub.1 and C.sub.2, the capacitance values of the equivalent capacitance of the FETS C.sub.X1, C.sub.X2 and C.sub.X6, and the inductances provided by transmission line section T.sub.2 and T.sub.5, a low pass filter section providing a first predetermined phase variation with respect to frequency is provided, such as shown in FIG. 7, curve 44.

Referring now to FIGS. 5 and 6, an equivalent circuit 30b of the phase shift network 30 is shown. This configuration 30b of network 30 (FIG. 2) is provided by feeding a signal on control voltage line V.sub.1 which places FET 1, FET 2 and FET 6 in an "on" or relatively low impedance state, and by feeding a signal on control voltage line V.sub.1 which places FET 3, FET 4 and FET 5 in a "pinch-off" or relatively high impedance state. Series coupled field effect transistors FET 1, FET 2 are thus shown replaced by the equivalent resistors R.sub.X1 and R.sub.X2 having a relatively low resistance (approximately equal to 0 ohms) and shunt mounted FET 6 is shown replaced by a shunt mounted resistor R.sub.X6 again having a relatively low resistance (approximately equal to 0 ohms). Further, FET 3 to FET 5 are shown replaced by capacitors C.sub.X3 to C.sub.X5. The equivalent circuit 30b (FIG. 5) may be simplified to an equivalent circuit 30b' shown in FIG. 6. A relatively low impedance path is provided between capacitor C.sub.1 and capacitor C.sub.2 through resistors R.sub.X1 and R.sub.X2. The relatively low impedance of resistor R.sub.X6 provides relatively low impedance paths to ground for transmission lines T.sub.3 and T.sub.4. Three shunt paths to ground are thus provided in network 30b'. A first shunt path includes transmission lines T.sub.2 and T.sub.3 serially connected together, with capacitor C.sub.X4 coupled in shunt with transmission line T.sub.3. A second shunt path includes transmission line T.sub.1, and equivalent capacitor C.sub.X3 coupled in shunt with transmission line T.sub.1, and the third shunt path includes transmission lines T.sub.4 and T.sub.5 serially connected together with capacitor C.sub.X5 coupled in shunt with transmission line T.sub.4. The equivalent circuit 30b' as shown in FIG. 6 is that of a five element high pass filter network which provides a second, predetermined variation in phase as a function of frequency over a predetermined frequency range, as shown in FIG. 7, curve 42.

Accordingly, as FET 1 to FET 6 are arranged to provide the switching functions as indicated in FIGS. 2-6, the two signal paths between input terminal 32 and output terminal 34 of network 30 are configured in response to a first one of a pair of states of control signals V.sub.1, V.sub.1 to provide a high pass filter (network 30b') having a first predetermined amount of phase lead with respect to the phase of an input signal as a function of frequency over a predetermined frequency range, and are configured in response to a second, different state of the control signals V.sub.1, V.sub.1 to provide a low pass filter (network 30a') having a second, different predetermined amount of phase lag with respect to the phase of an input signal as a function of frequency over a predetermined frequency range. By selecting the values of the capacitors C.sub.1, C.sub.2 and of transmission line sections T.sub.1 -T.sub.5, and further, by selecting the field effect transistors to have a relatively low resistance (approximately equal to 0 ohms) in the "on" state and a relatively low capacitance in the "off" state, the phase shift network can be provided to have a substantially constant relative phase shift difference between each one of said states over a predetermined operating frequency range. The values of capacitance of the field effect transistors must be selected to be substantially small such that they will provide a relatively high impedance path shunting transmission line sections T.sub.1, T.sub.3, T.sub.4 as shown in FIG. 6, and similarly, the field effect transistors must be selected to provide a relatively low impedance in the "on" state to reduce the resulting insertion loss which otherwise would be provided by the circuit.

Referring now to FIG. 7, a plot of a typical frequency characteristic as a function of frequency for a low pass filter having a predetermined phase lag characteristic 44 over an operating frequency range and a high pass filter having a predetermined phase lead characteristic 42 over the operating frequency range are shown. The difference in the phase of the high pass filter characteristic 42 and the low pass filter characteristic 44 is substantially constant over the operating frequency range. Therefore, while phase as a function of frequency varies in a first predetermined manner for the high pass section, and in a second predetermined manner for the low pass section, the difference in phase represented by .DELTA..phi. is substantially invariant with changes in frequency over the operating frequency range. By selecting values of capacitance for capacitors C.sub.1 and C.sub.2, values of equivalent inductance for transmission line sections T.sub.1 -T.sub.5 as well as controlling the value of resistance of FET 1 to FET 6 in the "on" state to be relatively low and the value of capacitance of FET 1 to FET 6 in the "off" state to be relatively low such that the impedance of the equivalent capacitance of FET 1 to FET 6 at the operating frequency is relatively high, the reconfigurable phase shift network is provided which has a relatively high bandwidth approaching the theoretical bandwidth of the passive elements, since the input signal which is shifted in phase is not cascaded through a pair of transistors as in prior passive phase shifters and the reactive component of such FETS, FET 1 to FET 6 become part of the network 30. The phase shift difference .DELTA..phi. provides a first phase shift bit for a 360.degree. phase shifter, for example. A plurality of such networks may be provided therefore to provide additional phase shift bits such as, but not limited to, 22.5, 45, 90 and 180.degree.. By cascading these stages together, a phase shifter having a selectable phase shift between 0 and 360.degree. is provided.

Further, in accordance with the frequency of the signal as well as the desired phase shift, the values of the components of the network 30 can be selected such that the impedance matching networks 22 and 24 are eliminated.

Further still, it should be appreciated that the phase shifter is preferably fabricated as a monolithic integrated circuit using techniques well-known in the art.

Having described preferred embodiments of the invention, it will now be apparent to one of skill in the art that other embodiments incorporating its concept may be used. It is felt, therefore, that this invention should not be restricted to the disclosed embodiment, but rather should be limited only by the spirit and scope of the appended claims.