Semiconductor Memories

This invention relates to static random access memories and in particular to a bit-line load for use in such memories.

The conventional diode bit-line load commonly used in static random access memories suffers from two serious disadvantages. The first of these is the so called V.sub.dd bump problem whereby a fall in the V.sub.dd voltage e.g. from V.sub.1 to V.sub.2 traps the bit-line at a voltage equal to V.sub.1 -V.sub.T1 (where V.sub.T1 is the diode threshold voltage) rather than the desired voltage V.sub.2 -V.sub.T1. On a subsequent access the memory cell must then discharge the bit-line by an additional voltage equal to V.sub.1 -V.sub.2 resulting in a slow access on this particular cycle.

The second problem with conventional diode loads in the relatively high V.sub.dd current associated with the write cycle. For example, in a conventional memory, the current flowing through a bit-line can be increased by two orders of magnitude over the current flowing during a read cycle. This problem is of course accentuated with wide memories where many bit-lines may be written to causing a large current drain, for example byte wide memories where eight bit-lines will be written to simultaneously.

The object of the present invention is to minimise or to overcome these disadvantages.

According to the invention there is provided a static random access memory, including an array of memory cells, and a plurality of bit-lines whereby the cells are accessed to effect reading and writing of data, wherein each bit-line is provided with a load comprising a diode or diode equivalent, current limiting means in series with the diode, and a current source in parallel with the diode and limiting means.

An embodiment of the invention will now be described with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a static random access memory;

FIG. 2 is a schematic diagram of the bit-line load of the memory of FIG. 1;

FIG. 3 shows a circuit construction of the bit-line load of FIG. 2, and

FIG. 4 shows a reference voltag generator for use with the load of FIGS. 2 and 3.

Referring to FIG. 1, the memory includes a cell array 11 of which an individual cell is shown at 110. The cell 110 typically comprises a four transistor bistable circuit and is accessed via a word line 12 and bit lines 13, 13a. Access to the cell array is provided via an access logic circuit 14 having a write input and a read output. Each bit-line is coupled to the circuit V.sub.dd rail via a load 15, 15a. As shown in FIG. 2, each bit-line load includes a diode D1 coupled in series with a current limiting device 11 to the memory supply rail (V.sub.dd). The diode clamps the bit-line low voltage during a memory read cycle. The series arrangement of the diode and limiter is shunted by a current source 12. This current source serves to pull the bit-line to a high level equal to V.sub.dd. The combination of the current source, diode and limiter ensures that the bit-line current that flows during a memory write cycle is closely similar to the current that flows during a read cycle. The net result is an enhancement of the operating speed of the memory.

A typical load circuit construction is shown in FIG. 3. The diode is provided by an n-channel transistor TR1 whose gate is maintained at a voltage V.sub.1. This voltage V.sub.1 defines the bit-line low voltage which would therefore be V.sub.1 -V.sub.T1, as described earlier. V.sub.1 is typically equal to V.sub.dd. Current flow through the transistor TR1 is limited by a series connected p-channel transistor TR2 connected to the drain of TR1. The gate of transistor TR2 is supplied with a voltage V.sub.2. Optionally V.sub.2 is chosen such that transistor TR2 is biassed into its resistive mode, i.e. into the linear operating region, or into its constant current mode, i.e. the saturated operating region.

A further p-channel transistor TR3 is coupled between the supply line and the source of transistor TR1 such that the current path of TR3 shunts the diode and limiter. The transistor TR3 is biassed by a voltage V.sub.3 applied to its gate. Preferably V.sub.3 is chosen so as to bias transistor TR3 into the constant current mode, i.e. the saturated operating region. Typically V.sub.3 would be a common reference mode used by all bit-line loads, a suitable circuit for generating this reference is shown in FIG. 4. A p-channel transistor TR4 is biassed with its source connected to the memory supply rail (V.sub.dd) and its gate and drain connected together to the reference supply rail (V.sub.3). The transistor is biassed on by the network 13 connected between the reference supply rail (V.sub.3) and the memory ground rail (V.sub.ss).

Transistor TR3 (FIG. 3) performs the secondary function of solving the so called V Bump problem. Should V.sub.dd rise from, for example, V.sub.2 to V.sub.1, then the bit line high level will rise from V.sub.2 to V.sub.1 through transistor TR3, and the bit line low level will rise from V.sub.2 -V.sub.T1 through transistor TR1 and TR2. Should V.sub.dd fall from, for example, V.sub.1 to V.sub.2 then the bit line high level will fall from V.sub.1 to V.sub.2 through transistor TR3, and the bit line low level will fall from V.sub.1 -V.sub.T1 to V.sub.2 -V.sub.T1 through the accessed memory cell.