IC Chip Error Detecting and Correcting Method Including Automatic Self-Checking of Chip Operation

My concurrently filed, commonly asssigned, copending application Ser. No. 750,439 for "IC Chip Error Detecting and Correcting Apparatus With Automatic Self-Checking of Chip Operation" contains subject matter which is related to the present invention. Also containing related subject matter are my commonly assigned copending patent applications U.S. Ser. No. 740,678 and U.S. Ser. No. 740,679, both filed Jun. 3, 1985.

This invention relates generally to improved apparatus and methods for implementing data processing operations in a data processing system, and particularly to those data processing operations involving error checking and correction. Modern day data processing systems are typically implemented using integrated circuit (IC) chips. One of the problems presented by the use of IC chips is that the outputs provided by an IC chip are often limited in number and/or may have special restrictions with regard to their use. Gate array IC chips often are limited in this manner. For example, an IC chip might provide for 48 data inputs while providing a maximum of only 28 outputs. Furthermore, some of these outputs may be restricted, such as with regard to power handling capability.

When an IC chip provides an insufficient number of outputs, one possible solution is to employ two IC chips in a manner such that the required number of outputs are obtained by combining outputs from both IC chips. However, this use of two IC chips can have the disadvantageous result of requiring that the two IC chips have different designs because of differences in the functions they are to perform in response to the inputs applied thereto. This would typically be the case, for example, for error checking and correcting operations. It will be appreciated that increasing the number of differently designed IC chips which have to be provided can have a significant impact on the cost and complexity of the overall system.

One way of avoiding having to provide two differently designed chips where they perform differently is to include on each IC chip the capability of performing the functions required by both IC chips, the particular function to be performed by each IC chip in the system then being selected by applying a control signal to selection logic provided on the chip. However, the use of such an approach can significantly add to the cost and complexity of each such IC chip and could not in any event be employed for an IC chip which does not have sufficient logic to provide both functions.

Accordingly, a broad object of the present invention is to provide improved apparatus and methods for implementing data processing operations using IC chips.

Another object of the invention is to provide improved apparatus and methods for implementing error checking and/or correction operations on IC chips.

Still another object of the invention is to achieve one or more of the foregoing objects for an implementation in which a plurality of chips are used in order to provide sufficient outputs to accommodate processing results produced in response to input signal bits.

A further object of the invention in accordance with the foregoing object is to provide an implementation in which each of the plurality of IC chips has the same design.

A still further object of the invention in accordance with one or more of the foregoing objects is to provide for automatic self-checking of the detecting operation of each chip.

An additional object of the invention is to provide the implementations of the foregoing objects in a relatively simple and inexpensive manner.

The above objects are accomplished in a particular preferred embodiment of the invention in which 48 input bits (including 40 data bits and 8 check bits) are applied to two identical IC chips which use the check bits to detect errors, correct any single bit errors which may be detected, and provide 40 outputs (20 from each IC chip) respectively corresponding to the 40 input data bits. In addition, single bit and multiple bit error indication outputs are also provided for each IC chip.

In order to obtain the advantage of being able to employ two identical IC chips in this particular preferred embodiment, the 8 check bits are provided with values determined based on a specially chosen modified Hamming code having a predetermined symmetry, and the 48 inputs are wired in a different manner to each of the IC chips based on this predetermined symmetry so that the required 40 data outputs are obtained (20 from each chip) even though each IC chip operates identically in response to its applied inputs. In addition, the single bit and multiple bit error indication outputs provided by each IC chip are logically combined to provide for automatic self-checking of the error detecting operations performed by the chips.

The above summarized approach can also be extended to the performance of additional or other types of processing using a plurality of IC chips where the symmetry of the processing can be chosen in conjunction with the wiring of the input signals so that IC chips of like design can be used.

The specific nature of the invention as well as other objects, advantages, features, and uses thereof will become evident from the following description of a preferred embodiment in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram illustrating the IC chip employed in the particular preferred embodiment of the invention described herein.

FIG. 2 illustrates the input and output wiring arrangements and designations employed for two identical IC chips of the type shown in FIG. 1 when used in a particular preferred embodiment of the invention.

FIG. 3 illustrates the specially chosen inversely symmetrical Hamming code employed in a particular preferred embodiment of the invention.

FIG. 4 illustrates another example of an inversely symmetrical Hamming code.

FIG. 5 is a schematic electrical diagram illustrating the generation of check bits for a plurality of data bits.

FIG. 6 is a schematic electrical diagram illustrating the operation of the error detecting and correcting circuitry provided on IC chip 10 in FIG. 2.

FIG. 7 is a table indicating the meanings of particular values of the syndrome bits S.sub.o -S.sub.7 produced by the syndrome generator 42 in FIG. 6.

FIG. 8 is a schematic electrical diagram illustrating the operation of the error detecting and correcting circuitry provided on IC chip 10' in FIG. 2.

FIG. 9 is a schematic electrical diagram illustrating error logic circuitry which may be employed for providing automatic self-checking of the error detecting operation of the embodiment shown in FIG. 2.

FIG. 10 is a table illustrating the operation of the error logic circuitry of FIG. 9.

FIG. 11 illustrates a logic circuit implementation of FIG. 9.

FIG. 12 illustrates inter-chip connections for an implementation in which the circuitry of FIG. 9 is incorporated on the chips.

Like numerals and characters refer to like elements throughout the figures of the drawings.

One well known way of detecting and correcting errors in data bits involves the use of an error code for generating check bits in response to the data bits. Typically, these check bits are included with the data bits and permit the detection and correction of one or more data errors depending on the type of code and the number of check bits provided. Data errors may occur, for example, after transmission of the data and check bits to other circuitry or another device. Further information with regard to error detecting and correcting can be found, for example in the article by R. W. Hamming, "Error Detecting and Error Correcting Codes", Bell Systems Technical Journal, 29, 1950, pp. 147-160; and in U.S. Pat. No. 4,375,664, D. R. Kim, inventor.

For the purposes of the particular preferred embodiment to be described herein, the basic operations to be implemented will be assumed to be: (1) The detecting of the presence of one or more errors in a 48 bit input signal having 40 data bits and 8 check bits, wherein the 8 check bits have been generated in accordance with a Hamming type code, (2) the correction of a single bit error, (3) the provision of 40 correct output data bits where no error or only a single bit error is present, (4) the provision of 40 unchanged output bits where a multiple bit error is detected, and (5) the additional provision of error output signals indicating whether an error was detected and also whether the detected error was a single bit error or a multiple bit error. Although this assumed implementation example is rather specific, the description to be provided herein illustrating how the present invention provides for implementation of this assumed example will adequately demonstrate how the present invention may also be applied to other applications.

Initially, it is to be noted that the above described operations could readily be implemented in a conventional manner using a single IC chip if sufficient inputs and outputs were available. However, certain types of chips, such as a gate array chip (for example, the Motorola MCA 2500 ECL Macrocell Array chip), would not be able to provide sufficient outputs. It is assumed that such a type of gate array IC chip is to be used for the particular preferred embodiment being described, in which case two such gate array IC chips are employed to obtain sufficient outputs. The novel manner in which the particular preferred embodiment is designed in accordance with the invention to permit two identical ones of the gate array IC chips to be employed for implementing the functions summarized above will now be described.

Referring to FIG. 1, illustrated therein is a schematic diagram of a gate array IC chip 10 (such as a Motorola MCA 2500 ECL Macrocell Array chip) which has been designed to provide the error detecting and correcting operations set forth above for the particular preferred embodiment being described.

As shown in FIG. 1, the chip 10 provides 48 input terminals IT.sub.o -IT.sub.47 which are applied to error detecting and correcting circuitry 15. The error detecting and correcting circuitry 15 is designed to operate in a conventional manner to detect the presence of an error in the input signal bits applied to input terminals IT.sub.o -IT.sub.47, and for this purpose assumes that the 8 bits applied to input terminals IT.sub.40 -IT.sub.47 are check bits. Circuitry 15 is also designed in a conventional manner to provide error indication signals SBE and MBE respectively indicating whether a single bit error or a multiple bit error was detected. These signals are applied to chip output terminals E.sub.1 T and E.sub.2 T as shown in FIG. 1.

The error detecting and correcting circuitry 15 illustrated in FIG. 1 is further designed to include the conventional capability of operating in response to a true or "1" SBE signal (indicating the detection of a single bit error) to correct the bit in error in the applied input signal. However, since each IC chip 10 need provide only 20 of the required 40 output signals in the particular preferred embodiment being described, the error detecting and correcting circuitry 15 is designed to provide for correcting a single bit error only if it occurs in one of the 20 input bits applied to input terminals IT.sub.o -IT.sub.19. As shown in FIG. 1, the resulting 20 output bits provided by the error detecting and correcting circuitry 15 are applied to the IC chip output terminals OT.sub.o -OT.sub.19. If there is no error in the 20 input bits applied to the 20 chip input terminals IT.sub.o -IT.sub.19, or if a multiple bit error is detected (MBE is true or "1"), these 20 input bits are passed to the output terminals OT.sub.o -OT.sub.19 unchanged.

As further illustrated in FIG. 1, the IC chip 10 also includes a clock input terminal C and may also include other conventional inputs (not shown) for control and/or other purposes.

Next to be considered is the manner in which two identical ones of these IC chips shown in FIG. 1 are employed in the preferred embodiment in accordance with the invention to provide the previously set forth error detecting and correcting operations in response to an applied 48-bit input signal so as to produce the desired 40 output data bits. It has been discovered that the key to successfully achieving this result is to provide an implementation such that the manner in which the error detecting and correcting circuitry 15 on the chip 10 is caused to respond to the input bits is chosen in conjunction with the provision of different wiring arrangements for the input bits applied to each chip so that the composite outputs from the two IC chips provide the required outputs even though the two IC chips are the same.

The above described discovery is implemented in the particular preferred embodiment of the invention by specially choosing the response of the error detecting and correcting circuitry 15 on the IC chip 10 to the input bits so that: (1) For a first wiring arrangement of the input bits to the chip input terminals IT.sub.o -IT.sub.47, the resulting output bits produced at the 20 chip output terminals OT.sub.o -OT.sub.19 will correspond to 20 of the input data bits, and (2) for a second wiring arrangement of the input bits to the chip input terminals IT.sub.o -IT.sub.47, the resulting output bits produced at these 20 chip output terminals OT.sub.o -OT.sub.19 will correspond to the remaining 20 of the 40 required output bits. Thus, by employing two IC chips 10 and wiring the input bits to the input terminals IT.sub.o -IT.sub.47 of one IC chip using the first wiring arrangement, and wiring the input bits to the input terminals IT.sub.o -IT.sub.47 of the second IC chip using the second wiring arrangement, the resulting 40 output bits obtained from the 20 output bits provided by each IC chip at the chip output terminals OT.sub.o -OT.sub.19 will provide the required 40 output bits.

The specific manner in which the response of the error detecting and correcting circuitry 15 on each chip 10 is chosen in conjunction with the first and second wiring arrangements of the 48 input bits to the chip input terminals of IT.sub.o -IT.sub.47 will now be described with reference to FIGS. 2-4. The chip wiring arrangements will be considered first with reference to FIG. 2. The reason why these particular wiring arrangements are chosen will become evident when the Hamming code response chosen for the error detecting and correcting circuitry 15 is considered in connection with FIG. 3.

As shown in FIG. 2, the lower IC chip 10' (which in the particular preferred embodiment is identical to the upper chip 10) and its associated components have been given the same numeral designations as used for the upper IC chip 10 with the addition of a prime (') for distinguishing purposes. It will be seen in FIG. 2 that the 48 input bits comprise the 40 input data bits ID.sub.o -ID.sub.39 and the associated 8 check bits CB.sub.o -CB.sub.7. For the upper IC chip 10, the input data bits ID.sub.o -ID.sub.39 are applied to the chip input terminals IT.sub.o -IT.sub.39, respectively, and the associated check bits CB.sub.o -CB.sub.7 are applied to the chip input terminals IT.sub.40 -IT.sub.47, respectively. For the lower IC chip 10', an inverse wiring arrangement is employed, the input data bits ID.sub.o -ID.sub.39 being applied to the chip input terminals IT'.sub.39 -IT'.sub.o, respectively, and the associated input check bits CB.sub.o -CB.sub.7 being applied to the chip input terminals IT'.sub.47 -IT'.sub.40, respectively. The desired 40 data output bits OD.sub.o -OD.sub.39 are then obtained from the composite of the 20 outputs produced by terminals OT.sub.o -OT.sub.19 of chip 10 and the 20 outputs produced by terminals OT'.sub.o -OT'.sub.19 of chip 10', wherein terminals OT.sub.o -OT.sub.19 provide data output bits OD.sub.o -OD.sub.19, respectively, and terminals OT'.sub.o -OT'.sub.19 provide data output bits OD.sub.39 -OD.sub.20 respectively (note inverse order).

The basis for the choice of the wiring arrangements illustrated in FIG. 2 will now be described in connection with FIG. 3 which illustrates the special Hamming code chosen for the error detecting and correcting function, which in turn determines how the error detecting and correcting circuits (designated as 15 on IC chip 10 and 15' on IC 10') are connected to their respective chip input terminals IT.sub.o -IT.sub.39 and IT'.sub.o -IT'.sub.39.

FIG. 3 diagramatically illustrates the specially chosen Hamming code employed in the particular preferred embodiment being described by showing the encoding relationship between each of the eight input check bits CB.sub.o -CB.sub.7 and the 40 input data bits ID.sub.o -ID.sub.39. Each check bit is generated by EXCLUSIVE ORing the binary values of those input data bits marked with an "X" in the respective check bit column. The particular logical equations representing this FIG. 3 encoding relationship between the 8 input check bits CB.sub.o -CB.sub.7 and the 40 input data bits ID.sub.o -ID.sub.39 are set forth on the bottom of FIG. 3, wherein ".sym." represents an EXCLUSIVE OR operation.

It will be seen from FIG. 3 that the illustrated Hamming code is inversely symmetrical about its center--that is, the logical equations for check bits CB.sub.o -CB.sub.3 have the same pattern as for check bits CB.sub.7 -CB.sub.4, respectively, except that the corresponding patterns for each check bit are in an inverse order relative to the input data bits ID.sub.o -ID.sub.39.

FIG. 3 illustrates an inversely symmetrical Hamming code for 40 data bits IO.sub.o -ID.sub.39 and an even number of check bits, namely check bits CB.sub.o -CB.sub.7. As another example, FIG. 4 illustrates an inversely symmetrical Hamming code (along with the corresponding logical equations) for 32 data bits ID.sub.o -ID.sub.31 and an odd number of check bits, namely the seven check bits CB.sub.o -CB.sub.6. In such a case, the pattern for the middle check bit CB.sub.3 is chosen so that it is symmetrical relative to the data bits ID.sub.o -ID.sub.31 --that is (as shown in FIG. 4) it has the same pattern with respect to the upper 16 data bits ID.sub.o -ID.sub.15 as it does with respect to the lower 16 bits ID.sub.31 -ID.sub.16.

It should now be understood that the choice of an inversely symmetrical Hamming code, such as illustrated in FIGS. 3 and 4, permits use of the identical designed IC chips 10 and 10' so long as the input data bits ID.sub.o -ID.sub.39 and the input check bits CB.sub.o -CB.sub.7 are inversely connected on the two IC chips and the data outputs OD.sub.o -OD.sub.39 are appropriately designated as shown in FIG. 3. In other words, by use of an inversely symmetrical Hamming code, the same error detecting and correcting circuitry can be used to detect and correct errors for both the upper and lower halves of the input bits. Therefore, by connecting the input data bits ID.sub.o -ID.sub.39 and the input check bits CB.sub.o -CB.sub.7 in inverse order relative to the IC chip input terminals as shown in FIG. 2, one chip 10 can be used to produce one-half of the data output bits (OD.sub.o -OD.sub.19) and the other chip 10' can be used to produce the other half of the data bits (OD.sub.20 -OD.sub.39).

Further details will now be presented of a preferred construction and operation of the error detecting and correcting circuitry (indicated in FIG. 1 as 15 on chip 10). For this purpose, it will be assumed that, as shown in FIG. 2, there are 48 input bits of which the 40 bits ID.sub.o -ID.sub.39 are data bits and the 8 bits CB.sub.o -CB.sub.7 are check bits having values chosen in accordance with the inversely symmetrical Hamming code illustrated in FIG. 3.

It will be understood that these eight check bits CB.sub.o -CB.sub.7 may be generated in a conventional manner in response to the data bits ID.sub.o -ID.sub.39, such as illustrated in FIG. 5. As shown in FIG. 5, the data bits ID.sub.o -ID.sub.39 are applied to a check code generator 30 which generates the check bits CB.sub.o -CB.sub.7 based on the equations set forth in FIG. 3. These check bits CB.sub.o -CB.sub.7 are then combined with the data bits ID.sub.o -ID.sub.39 to constitute the 48 input bits which are inversely applied to the input terminals IT.sub.o -IT.sub.47 and IT'.sub.o -IT'.sub.47 of IC chips 10 and 10' as shown in FIG. 2.

Referring next to FIG. 6, shown therein is an electrical block diagram illustrating a preferred implementation of detecting and correcting circuitry 15 and 15' of IC chip 10 and IC chip 10'. The operation indicated in FIG. 6 is for the input bit wiring arrangement of IC chip 10 shown in FIG. 2. The operational differences resulting from the inverse input bit wiring arrangement used for IC chip 10' will be described later.

As shown in FIG. 6, the error detecting and correcting circuitry comprises a syndrome generator 42, a syndrome decoder 44 and a single bit error corrector 46. The 40 input data bits ID.sub.o -ID.sub.39 are applied to input terminals IT.sub.o -IT.sub.39, respectively, of IC chip 10 and the 8 input check bits CB.sub.o -CB.sub.7 are applied to input terminals IT.sub.40 -IT.sub.47, respectively. The chip input terminals IT.sub.o -IT.sub.47 containing both the data and check bits are coupled to the input of the syndrome generator 42, while the input terminals IT.sub.o -IT.sub.19 corresponding to the input data bits ID.sub.o -ID.sub.19, respectively, are also coupled to the input of the single bit error corrector 46. The syndrome generator 42 operates in a conventional manner in response to the input data bits ID.sub.o -ID.sub.39 to generate a second group of 8 check bits in accordance with the same inversely symmetrical Hamming code illustrated in FIG. 3, this second group of 8 check bits then being EXCLUSIVELY ORed with the 8 input check bits CB.sub.o -CB.sub.7 to produce 8 corresponding syndrome bits S.sub.o -S.sub.7 at the output of the syndrome generator 42. As is well known, the values obtained for these syndrome bits S.sub.o -S.sub.7 provide error information with regard to the input data bits ID.sub.o -ID.sub.39 as well as the input check bits CB.sub.o -CB.sub.7.

FIG. 7 is a table summarizing the meanings of the 256 possible combinational values of the 8 syndrome bits S.sub.o -S.sub.7 provided at the output of the syndrome generator 42 for the inversely symmetrical Hamming code illustrated in FIG. 3. As will be understood from FIG. 7, the all zero value 00000000 (indicated by "*") for 8 syndrome bits S.sub.o -S.sub.7 indicates that there are no bits in error in the input data bits ID.sub.o -ID.sub.39 or in the input check bits ICB.sub.o -ICB.sub.7 . Single bit errors are indicated in FIG. 7 by the number of the bit in error. For example, a value of 10000011 for the syndrome bits S.sub.o -S.sub.7 shows a number "36" in FIG. 7, which indicates that there is a single bit error and that input data bit ID 36 is the bit in error.

Errors in the check bits CB.sub.o -CB.sub.7 are also shown in FIG. 7, these being indicated by the numbers 40-47, respectively, which are a result of the input check bits CB.sub.o -CB.sub.7 being connected to input terminals IT.sub.40 -IT.sub.47 of IC chip 10 as shown in FIG. 2. For example, a value of 00010000 for the syndrome bits S.sub.o -S.sub.7 shows the number "43" which indicates that there is a single bit error and that check bit CB.sub.3 (which is applied to input terminal IT.sub.43 of chip 10) is the bit in error.

Multiple bit errors are indicated in FIG. 7 by "M" and "D", "M" indicating that there are an odd number of bits in error, and "D" indicating that there are an even number of bits in error.

Returning to FIG. 6, it will be seen that the syndrome bits S.sub.o -S.sub.7 produced at the output of the syndrome generator 42 are applied to a syndrome decoder 44 which operates to decode particular ones of the combinational values of the syndrome bits S.sub.o -S.sub.7, depending on which of the FIG. 7 indications are to be employed. In the particular preferred embodiment being described herein, the syndrome decoder 44 provides a single bit error output signal SBE and a multiple bit error output signal MBE for application to corresponding output terminals E.sub.1 T and E.sub.2 T as shown in FIG. 1. It will be understood from FIG. 7 that the decoding provided by the syndrome decoder 44 is such that SBE will be true or "1" if the input syndrome bits S.sub.o -S.sub.7 have values corresponding to any of the single bit error indications (numbers 00 to 47) in FIG. 7, while the MBE signal will be true or "1" if the syndrome bits S.sub.o -S.sub.7 have values corresponding to any of the "M" or "D" indications in FIG. 7.

It will be remembered that each of the IC chips 10 and 10' need provide only one-half of the required data outputs, as shown in FIG. 2. Accordingly, each chip provides for correcting single bit errors for only one half of the input data bits ID.sub.o -ID.sub.39, these being the input data bits connected to input terminals IT.sub.o -IT.sub.19. Accordingly, in order to provide for correcting half or 20 of the input data bits ID.sub.o -ID.sub.39, the syndrome decoder 44 additionally provides 20 correcting bits C.sub.o -C.sub.19 which are applied to the single bit error corrector 46 along with the input data bits connected to chip input terminals IT.sub.o -IT.sub.19, which for chip 10 are input data bits ID.sub.o -ID.sub.19, respectively. The outputs of the error corrector 46 will thus correspond to output data bits OD.sub.o -OD.sub.19. (The manner in which IC chip 10' provides for correcting the remaining input data bits ID.sub.20 -ID.sub.39 will be explained shortly.)

The operation of the syndrome decoder 44 in FIG. 6 in producing the correcting bits C.sub.o -C.sub.19 is such that, if a single bit error is detected, a correcting bit will be true or "1" if its corresponding input data bit is the one which is in error. For example, if a single bit error is detected and the bit in error is input data bit ID.sub.14, then correcting signal C.sub.14 will be true or "1". If there are no errors in any of the input data bits ID.sub.o -ID.sub.19, or if there is a multiple bit error, then all of the correcting bits C.sub.o -C.sub.19 will be false or "0".

The single bit error corrector 46 in FIG. 6 thus passes the applied input data bits ID.sub.o -ID.sub.19 unchanged unless the single bit error signal SBE is "true" or "1", in which case, the bit in error is corrected by the error corrector 46. This may be accomplished, for example, simply by EXCLUSIVE ORing the corresponding data and error bits. For example, if correcting signal C.sub.14 is a "1", indicating an error in input data bit ID.sub.14, then the value of OD.sub.14 at the output of the error detector 46 will be the inverse of ID.sub.14 --that is, if ID.sub.14 applied to the error detector 46 is "0", then OD.sub.14 will be "1", and if ID.sub.14 is "1", OD.sub.14 will be "0".

From the description of FIG. 6 provided above, it should now be understood how IC chip 10 in FIG. 2 produces the output data bits OD.sub.o -OD.sub.19 at chip output terminals OT.sub.o -OT.sub.19. The manner in which the IC chip 10' produces the remaining output data bits OD.sub.20 -OD.sub.39 will now be explained with reference to FIG. 8 which is the same as FIG. 6, except for differences in the input and output data bit designations resulting from the inverse wiring employed for the input data bits applied to IC chip 10' as shown in FIG. 2. Thus, the error corrector 46 will provide output data bits OD.sub.39 -OD.sub.19 which are respectively applied to the output terminals OT'.sub.o -OT'.sub.19 of chip 10' and, together with the output data bits OD.sub.o -OD.sub.19 produced by IC chip 10, provide the 40 required output data bits OD.sub.o -OD.sub.39.

It will also be understood with respect to IC chip 10', that the signals C.sub.o -C.sub.19 produced by the syndrome decoder 44 in response to the syndrome bits S.sub.0 -S.sub.6 produced by the syndrome generator 42 will properly indicate the presence of errors in input data bits ID.sub.39 -ID.sub.20, respectively (as well as single and multiple bit errors) because of the inverse wiring of the input data bits ID.sub.o -ID.sub.39 and input check bits CB.sub.o -CB.sub.7 to the input terminals IT'.sub.o -IT'.sub.47 terminals, as shown in FIG. 2, coupled with the use of the inversely symmetrical Hamming code shown in FIG. 3. This will become evident by noting that, for chip 10', the input data bits ID.sub.o -ID.sub.39 and the input check bits CB.sub.o -CB.sub.7 are applied to the syndrome generator 42 in an inverse manner relative to chip 10. Thus the syndrome generation and coding operations performed by chip 10 with respect to input data bits ID.sub.o -ID.sub.39 will be performed in the same manner for chip 10' with respect to the input data bits ID.sub.39 -ID.sub.o since the Hamming code is inversely symmetrical, as shown in FIG. 3. Furthermore, the error correcting operations performed with respect to input data bits ID.sub.o -ID.sub.19 for chip 10 will be the same as performed with respect to input data bits ID.sub.39 -ID.sub.20, respectively, of chip 10'. Thus, output data bits ID.sub.o -ID.sub.19 will be produced at output terminals OT.sub.o -OT.sub.19, respectively, of chip 10 while output data bits ID.sub.39 -ID.sub.20 will be produced at output terminals OT'.sub.o -OT'.sub.19, respectively of chip 10'.

An additional feature of the present invention resides in the manner in which automatic self-checking of the operation of the IC chips is advantageously provided. This additional feature will now be described with reference to FIGS. 9-12.

It will be evident from FIGS. 2, 6 and 8 that the single bit error and multiple bit error signals SBE and MBE produced by each of the chips 10 and 10' are applied to the respective chip output terminals E.sub.1 T, E.sub.2 T and E.sub.1 T' and E.sub.2 T'. In FIG. 9, the single bit and multiple bit error signals appearing at the respective terminals E.sub.1 T and E.sub.2 T of chip 10 are designated as SBE and MBE, and the single bit and multiple bit error signals appearing at the respective terminals E.sub.1 T' and E.sub.2 T' of chip 10' are designated as SBE' and MBE'.

When the error detection operations of the chips 10 and 10' are performing properly, it is to be expected that SBE and SBE' will be the same as also will MBE and MBE', since each IC chip determines single and multiple bit errors using the same input data signals ID.sub.o -ID.sub.39 and the same check bit signals ICB.sub.40 -ICB.sub.47. The fact that these input data and check bit signals are wired to the chip input terminals in inverse order will not affect the values of these single and multiple bit errors. In accordance with the present invention, the existence of this redundancy in the single bit and multiple bit signals is advantageously exploited to provide for automatic self-checking of the error detecting operations performed by the chips, as will now be illustrated with reference to FIGS. 9 and 10.

As shown in FIG. 9, the SBE, SBE', MBE and MBE' signals produced by IC chips 10 and 10' are applied to error logic circuitry 50 for producing error output signals E.sub.O, E.sub.SB, E.sub.MB and E.sub.CH in response thereto. The logical operations performed by the error logic circuitry 50 for producing these error output signals will be apparent from the table of FIG. 10. It will be appreciated that appropriate logical circuitry for implementing the logic illustrated in this table may readily be provided by those skilled in the art.

It will be understood from the table of FIG. 10 that only one of the error outputs from the error logic circuitry 50 in FIG. 9 will be true or "1" at any one time. More specifically, E.sub.O will be true or "1" when no error of any type is present; E.sub.CH will be true or "1" when a chip error is present (which is indicated when the values of the inputs are inconsistent with proper chip operation, such as if SBE and SBE' are different or if MBE and MBE' are different, or if both a single bit error and a multiple bit error are produced); E.sub.SB will be true or "1" when a single bit error is detected by both chips and there is no chip error and no multiple bit error; and E.sub.MB will be true or "1" when a multiple bit error is detected by both chips and there is no chip error and no single bit error.

One example of an implementation which may be employed for the error logic circuitry 50 in FIG. 9 is illustrated in FIG. 11 wherein numerals 52 and 54 designated EXCLUSIVE OR gates, numerals 56, 58 and 60 designate AND gates, numerals 62 and 64 designate OR gates, and a circular dot at an output (such as shown for gates 62 and 64) indicates an inverse output. It will be understood that error logic circuitry 50 such as illustrated in FIGS. 9 and 11 may be implemented on a separate IC chip and the signals SBE, SBE', MBE and MBE' applied thereto. Alternatively, such circuitry could be incorporated on each of the IC chips 10 and 10' and the single bit and multiple bit signals of each chip coupled to the other, such as illustrated, for example, in FIG. 12. Error outputs E.sub.O, E.sub.CH, E.sub.SB and E.sub.MB would then be provided for each chip, as shown, either of which outputs could be used.

Although the present invention has been described in connection with a particular preferred embodiment, it is to be understood that many modifications and variations may be provided in the structure, arrangement and use thereof without departing from the true spirit of the inventive contribution.

For example, although the particular preferred embodiment of the invention described herein does not provide for correcting or outputting any check bits, it will be understood that this could readily be provided in basically the same manner as provided for the data input bits, in which case, each IC chip would additionally provide 4 of the 8 output check bits.

It will also be understood that the present invention is not limited to use for detecting and correcting operations, but could also be employed for other types of processing operations where an appropriate cooperative relationship can be provided between the input wiring arrangements and the chip response capability. Furthermore, the invention could also be employed with more than two IC chips.

Also, it is to be understood that the described self-checking feature could also be used for implementations in which the IC chips are not identical.

Accordingly, the present invention is to be considered as including all possible modifications and variations coming within the scope of the invention as defined in the appended claims.