Data Transmission Arrangement Including a Reconfiguration Facility

1. Field of the Invention

The invention relates to an apparatus for the transmission of data between a number of interconnection units. Data receiving and/or data transmitting apparatus are connected to the interconnection units. Each interconnection unit comprises at least two physically separate data connections. Each data connection comprises at least two connection lines corresponding to respective transmission paths of opposite directions. The interconnection units are interconnected via the transmission paths so that in a non-disturbed state at least one data transmission path is formed which successively passes through all interconnection units in the apparatus. The apparatus includes a synchronization device which generates synchronization information in order to form a continual data stream. Each interconnection unit comprises a detector device for monitoring the data stream on the data transmission path. Upon detection of a disturbance of the data stream, the detector device interconnects the data connections so that there is again formed a transmission path which interconnects the interconnection units, avoiding the location of disturbance.

2. The Prior Art

Such an apparatus is known from U.S. Pat. No. 4,109,821. Therein, a number of interconnection units and a central station for generating synchronization information are connected so as to form a closed loop. Each interconnection unit comprises two data connections for an incoming line and an outgoing line. These lines between the data connections interconnect the interconnection units in such a manner that two separate, closed data transmission paths are obtained in which the direction of transmission is opposed. Only one of the two data transmission paths is used for data transmission, when all connections between all interconnection units are non-disturbed. The other data transmission path serves as a spare for disturbances. Data transmission from a first arbitrary interconnection unit to a second arbitrary interconnection unit takes place when the first interconnection unit inserts a message in a free location in the data stream. The message contains the address of the second interconnection unit. All interconnection units constantly monitor the data stream checking for their own address. If their address is found, the relevant message is taken up and the data stream is transmitted further, preferably without the relevant message. In an extreme case, an interconnection unit can thus transmit a message to the directly preceding interconnection unit in the data stream. In such a case a delay occurs because the message traverses substantially the entire data transmission path. The messages are generally transmitted in a frame structure which is fixed in time and which is determined by the synchronization information. Therefore delay time compensation in the prior art is performed by means of buffer memories, notably in the central station. This compensation is made in order to ensure that the shortest delay time, via the complete transmission path, amounts to at least one frame period.

A disturbance may occur in the data transmission path used for the data transmission due to an interruption of the connections between the interconnection units or a disturbance in the data transmission path inside an interconnection unit. Such a disturbance will be noticed by the next interconnection unit when data no longer arrive and especially when there is no synchronization information within given, fixed time intervals. This next interconnection unit then interrupts the unused data transmission path and connects the input thereof to the output for the original data transmission path. The non-disturbed state of the path which is not used for data transmission is also constantly monitored by constant transmission of monitoring data. The interconnection unit preceding the disturbed location detects the absence of this monitoring information and connects the input of the data transmission path used thus far to the output of the other data transmission path. The disturbed location is thus bridged by the other data transmission path. The delay times of transmitted messages are thus approximately doubled, but transmission of messages from a first arbitrary interconnection unit to a second arbitrary interconnection unit outside the disturbed location is still possible.

When a further disturbance occurs in another location in the data transmission path, the overall loop of interconnection units break down into two sections. A reconfiguration of the section comprising the central station for the synchronization information is then similarly possible. However, in the remainder of the interconnection units data transmission is then no longer possible. Moreover, in the section in which reconfiguration has taken place the delay time compensation must be adapted to the possible shortening of the transmission path.

It is the object of the invention to provide an arrangement of the described kind in which an extensive reconfiguration of all data transmission paths which still exist can be performed in a simple manner, even when several disturbances occur in the data transmission path.

This object is achieved in accordance with the invention as follows. Each interconnection unit comprises a synchronization device. The detector device in each interconnection unit activates, upon detection of a disturbance of the data stream, the synchronization device. Thus test information is transmitted to at least one neighbouring interconnection unit. The detector device also reads all test information received from any other interconnection unit. The detector device in each interconnection unit subsequently connects the data connections to one another or to the synchronization device, depending on the data connection on which test information was received and on the content of the test information.

When each interconnection unit is provided with a comparatively simple synchronization device and when a test procedure is initiated in the case of disturbances, each interconnection unit itself can in all circumstances unambiguously determine the state of the connections of other interconnection units. Each interconnection unit can subsequently determine, independently of the other interconnection units, which data connections are to be connected to one another or to the synchronization device. Notably an arrangement of interconnection units, which was originally in closed loop, may break down into several sections due to a plurality of disturbances. Each section itself can then form a complete arrangement for data transmission where all interconnection units present can exchange messages with one another.

Only when external connections are in order does a first interconnection unit correctly receive test information transmitted by other interconnection units upon detection of a disturbance of the data path. Therefore one interconnection unit can also determine whether a connection, dedicated to test information from another interconnection unit, is in order. However, when the connection dedicated to test information from one interconnection unit to another interconnection unit is interrupted, the one interconnection unit cannot easily detect the interruption. In order to ensure that each interconnection unit is informed about all lines within its data connections, the detector device in each interconnection unit preferably initiates the transmission of acknowledge information in response to each piece of test information correctly received by the interconnection unit. The detection device also evaluates subsequent acknowledge information at least on all incoming lines on which test information from another interconnection unit has appeared. Thus, the acknowledge information informs each interconnection unit whether the transmitted test information has been correctly received by another interconnection unit. Consequently, in each interconnection unit the condition of the external connections is fully known, so that subsequently the interconnections for the reconfiguration can be unambiguously established.

When each interconnection unit transmits its own test information via each outgoing line, usually an appreciable amount of time will be required. This is because the transmission of the test information via various lines, and also the evaluation of the test information arriving via several incoming lines, generally can only be performed consecutively instead of simultaneously. To limit the required amount of time, in a further embodiment of the invention, the detector device in each interconnection unit preferably connects the connection lines of at least one data connection so that any test information received from another interconnection unit is returned thereto. Thus, each test information transmitted tests two lines, i.e. an outgoing line and the associated incoming line.

In the prior art in which only one of the two transmission paths is used in the non-disturbed state, an internal delay time compensation must be performed. In the case of a disturbance this compensation may have to be changed. The necessity of such a delay time compensation and hence the adaptation thereof is avoided, in yet another embodiment. To accomplish this one of the transmission paths interconnecting all interconnection units serves as a write channel, only for the transmission of transmitted, but not yet evaluated data. At the same time, the other path serves as a read channel which is connected to the end of the write channel after the latter has passed through all interconnection units. The other path serves only for the transmission of the data which is transmitted by all interconnection units in order to be processed. In such an arrangement, delay time problems will no longer occur. Delay time compensation will not be required under any circumstances. Furthermore, such an arrangement enables simple control of the lines of the data connections and the synchronization device in each interconnection unit. In case of disturbance, with interconnection units which each comprise only two data connections, the connection between the two transmission paths preferably takes places in that interconnection unit which has not received correct test information. Such test information arrives via the write channel after detection of a disturbance of the data stream. In that same interconnection unit, the write channel is connected to the synchronization device and the read channel is connected to a termination element. It can thus be simply determined in which interconnection unit it is necessary to connect the synchronization device to the write channel and to interconnect the two data paths.

A further embodiment which utilizes separate write and read channels is characterized in that each data connection comprises a write channel as well as a read channel. Each such channel comprises two connection lines: one to receive a data stream via an incoming line from another interconnection unit; and another to transmit a data stream via an outgoing line to the same interconnection unit. The data path covers all interconnection units thus being formed in which the write channel and the read channel extend separately in parallel. The detector device in each interconnection unit transmits the test information upon detection of a disturbance of the data stream via the outgoing line of the write channel of all data connections. The detector device also evaluates the test information arriving via the incoming lines of both channels of all data connections. The detector device interconnects the lines of the data connections with other lines only when the external connections to both lines of both channels have been determined to be in order. Thus, the selection of the interconnection unit, in which the synchronization device is connected to the outgoing line of the write channel, is no longer dependent on the end of the transmission path. Other criteria can be used. This is more attractive for many applications, as will be explained hereinafter.

In yet a further embodiment of the arrangement in according with the invention such a further criterion is used. This criterion involves assigning a different sequence number to each interconnection unit of the arrangement. Each interconnection unit transmits its own sequence number. This sequence number is contained in the test information. Each interconnection unit also evaluates the sequence numbers contained in the test information received from the other interconnection units. The sequence number makes it possible to determine the interconnection unit which is connecting its internal synchronization device to the outgoing write line of a data connection.

In the case of multiple disturbances, the prior art attempted reconfigurations of at least one data transmission path to interconnect as many interconnection units as possible. It is known (for example, for DE-PS No. 25 52 953 or from IBM Technical Disclosure Bulletin Vol. 21, No. 8, January 1979, pages 3349 to 3350) to provide each interconnection unit with more than two data connections. Notably additional data transmission paths are formed which each skip one or more neighbouring interconnection units. For performing the reconfiguration the latter publication proposes a central unit. In DE No. 25 52 953, in each interconnection unit, a common internal data junction is switched over from one incoming line to another incoming line, when the data stream on the one incoming line is interrupted. The common data junction is permanently connected to at least two separate outputs. However, in these known arrangements an extensive reconfiguration is possible only if the disturbed locations exhibit a given distribution. In addition, for each interconnection unit four data connections are required. Moreover, it is not disclosed how a reconfiguration may be obtained when the loop, including all branch connections, is completely interrupted in a location. Furthermore, the above arrangements also require delay time compensation.

In a still further embodiment of the invention the case of an arbitrary distribution of disturbed locations is dealt with. In this embodiment, all interconnection units which are interconnected via a respective data connection can form a complete reconfiguration for data transmission by means of at least one continuous write channel and read channel. This data transmission does not require delay time compensation. The embodiment is characterized in that when each interconnection unit comprises at least three data connections, in the non-disturbed state a group of interconnection units always forms at least one closed data transmission path via two of the data connections. The further data connections are connected to corresponding data connections of other groups. Incoming line connections in each interconnection unit are connectable to the corresponding outgoing line connection of only one data connection. The transmission paths through each pair of groups form, via further data connections through one interconnection unit in each group, a data transmission path which passes through all groups. Upon detection of a disturbance of the data stream, test information is transmitted via each line by one of the two interconnection units connected thereto. The detector device in each interconnection unit connects the incoming and outgoing line connections depending on: whether the correct test information has been received on the data connections; the content of the test information; and which data connection the data stream from a synchronization device of an interconnection unit appears on first after the transmission of all test information. The detector devices connect the incoming and outgoing line connections so that at least one data transmission path is formed via all interconnection units which are interconnected via at least one data connection. The interconnection unit which does not receive a sequence number, in any test information which is lower than its own sequence number, then connects its internal synchronization device to the outgoing write line of a predetermined data connection if at the same time all transmission channels or lines of the predetermined data connection are in order.

Consequently, even if each group of interconnection units is multiply interrupted a coherent reconfiguration can still be obtained. In other words two separate sections of one group still communicate with at least one coherent section of the other group. The reconfiguration without a central unit is possible notably because each interconnection unit comprises its own synchronization device. This synchronization device can be connected, independently of the interconnection units, as required in accordance with the results of the test procedure which is performed in each interconnection unit for all data connections. Furthermore, by using the sequence numbers, it can be unambiguously determined which interconnection unit must supply the synchronization information.

This can be understood by considering a first interconnection unit which is connected to three other interconnection units. Suppose this first interconnection unit receives a sequence number, lower than its own sequence number, along with test information from one of the other interconnection units. The first interconnection unit then knows that it need not generate the synchronization information. Whether the other interconnection unit having the lower sequence number will actually generate the synchronization information or whether this will be done by a further interconnection unit, connected to the other and which has a sequence number which is even lower, is irrelevant to the first interconnection unit. There will always be only one interconnection unit which does not receive test information from other interconnection units of lower sequence number. This relevant interconnection unit will be informed and this will be sufficient for this purpose. It will be apparent that neighbouring interconnection units are assigned sequence numbers in a monotonously ascending order.

Another further embodiment of the described arrangement is characterized in that each interconnection unit comprises, for each incoming line of the write channel and the read channel, a switch which is controlled by the detector device. The switch also connects said incoming line to an outgoing line of the same channel of only one data connection, including the data connection associated with the relevant incoming line. The switches of all incoming lines are connected so that each outgoing line is connected to at the most one incoming line. The outgoing line of the write channel of a predetermined data connection is switchable from the outputs of the switch to the input of the synchronization device. The outgoing line of the read channel of the predetermined data connection is connected to a further switch. The further switch connects the relevant outgoing line of the read channel to an incoming line of the write channel of one of the data connections. This arrangement of switches enables the connections required for the reconfiguration to be established extremely quickly.

The reconfiguration is somewhat time-consuming with interconnection units, which comprise at least three data connections and which are interconnected in groups in a substantially closed loop, when several disturbances occur simultaneously via all interconnection units which can still be connected. Moreover, during this time sections of the original arrangement are not yet available for data transmission. Yet another further embodiment prepares sub-arrangements for data transmission more quickly in such cases. The interconnection of the sub-arrangements takes place subsequently. This embodiment relates to the case of: at least three data connections per interconnection unit, and the formation of a respective write channel and a read channel for each interconnection unit, which together cover all interconnection units using two selected data connections of each interconnection unit. The third data connection of at least a fraction of the interconnection units is connected to a corresponding data connection of remote interconnection units in the non-disturbed case. After detection of a disturbance of the data stream and of the transmission and evaluation of the test information, a write channel and a read channel are formed for all interconnection units connected via non-disturbed connections between the selected data connections. In this way said interconnection units are interconnected. The connection of the synchronization device to the write channel in the interconnection unit takes place at the beginning of the write channel. The connection between the write channel and the read channel in the interconnection unit takes place at the end of the write channel. Afterwards test data is exchanged via the further data connections of interconnection units which have been determined to be in order. Said test information contains the sequence numbers of the associated interconnection units in which the synchronization device is activated. Then the two groups having the lowest sequence numbers are interconnected so as to form a common data transmission path. In other words the synchronization device is activated only in the interconnection unit having the overall lowest sequence number. The described procedure is repeated until all interconnection units which have at least one common connection have been interconnected so as to form a common write and read channel. Thus, first sub-arrangements for data transmission are formed from interconnected interconnection units of a group. Once said sub-arrangements are operational, the testing of the connections between sub-arrangements of different groups is performed. A step-wire structure is thus obtained. Consequently, the sub-arrangement within which data transmission is possible is step-wise enlarged. Data transmission, independent of the other sub-arrangements, is possible in the sub-arrangements not yet connected.

Embodiments in accordance with the invention will be described in detail hereinafter with reference to the drawing. Therein:

FIG. 1 shows an arrangement consisting of interconnection units comprising only two data connections in the non-disturbed state,

FIG. 2 shows the test configuration of the arrangement shown in FIG. 1 when an interruption of the data stream occurs,

FIG. 3 shows a flowchart for testing the state of the connections connected to a data connection of an interconnection unit,

FIG. 4 shows an arrangement as shown in FIG. 1 after reconfiguration due to a disturbance,

FIG. 5 shows an arrangement of interconnection units which comprise three data connections,

FIG. 6 shows the test configuration of some arrangements as shown in FIG. 1 when an interruption of the data stream is detected,

FIG. 7 shows an arrangement as shown in FIG. 5 after reconfiguration due to several, simultaneously occurring disturbed locations,

FIG. 8 shows the arrangement of switches for establishing connections with an interconnection unit in order to perform the reconfiguration,

FIGS. to 9a to 9c show the various steps during the reconfiguration of an arrangement consisting of several interconnection units comprising three data connections each.

FIG. 1 shows six interconnection units 11 to 16. Each unit comprises two data connections. Each data connection is connected to neighbouring interconnection units via two connections. For example, one data connection of the interconnection unit 11 is connected to a data connection of the interconnection unit 12 via connections 17 and 18. The other data connection of the interconnection 11 being connected to the interconnection unit 16 via the connections 19 and 20. The peripheral apparatuses which are connected to the individual interconnection units and which receive and/or output data have been omitted for the sake of clarity, because they are irrelevant to the present invention. The directions of the data streams on the two connections between each pair of interconnection units are always opposed as indicated by the arrows on these connections.

Furthermore, input amplifiers and output amplifiers (not shown) are connected to the data connections of each interconnection unit. The connections between the interconnection units need not be electrical connections, but may also be optical connections utilizing light conductors, each input amplifier then comprising a light-sensitive element such as a photodiode and each output amplifier comprising, for example a laser diode. However, this will not be elaborated upon hereinafter because it is irrelevant for the present invention.

Each of the interconnection units 11 to 16 comprises a synchronization device 31, 32, 33 etc. for generating synchronization information. Said devices generate a constant data stream comprising periodic synchronization signals. Furthermore, each interconnection unit comprises three switches, i.e. the switches 27, 28 and 29 of the interconnection unit 11. Moreover, each interconnection unit also comprises a detector device 21, 22, 23 etc., the detector device 21 of the interconnection unit 11 monitoring the data stream on the connections 17 and 18. Furthermore, each of the interconnection units 11 to 16 also comprises a data device (not shown). This data device either transfers the data output by the peripheral apparatus (not shown) to the connections leading to the other data devices; or takes up the data from the connections originating from the other interconnection units for supply to the peripheral apparatus.

The switch 29 in the interconnection unit 11 is connected so that the synchronization information transmitted by the synchronization device 31 is transferred, via the connection 17. to the interconnection unit 12. From there, the synchronization information is transferred successively to the other interconnection units 13 to 16 and finally back to the interconnection unit 11. The connection 17 and the corresponding connections between the other interconnection units thus represent a write channel on which the data is only written but not yet processed. The synchronization information transmitted by the synchronization device 31 marks a number of time slots in the write channel. An interconnection unit wishing to transmit a message checks the write channel for the presence of a free time slot and transmits its message therein. All messages transmitted by all interconnection units are thus present on the line 20 arriving at the interconnection unit 11.

In the interconnection unit 11 the connection 20 is connected to the switch 27, shown closed. The connection 20 is subsequently coupled, via the connection 19, to the interconnection unit 16 and then successively to all other interconnection units 15 to 11. The circulating data is in this case complete, i.e. no additional data is added in any interconnection unit. This data is merely evaluated in the individual interconnection units. This means that each interconnection checks whether a message in a time slot comprises its own address. The connections 18, 19 and the corresponding connections (not numbered) thus represent the read channel. This channel ultimately extends, via the connection 18, to the interconnection unit 11. In the interconnection unit 11, the switch 28 is connected so that the data received is applied to a termination 30. Thus, in the arrangement shown in FIG. 1 each interconnection unit can transmit a message to any other interconnection unit.

As shown in FIG. 1 all interconnection units in principle have the same priority. Thus, it is arbitrary in which interconnection unit: the synchronization device is connected to the outgoing write channel, the incoming write channel is connected to the outgoing read channel, and the incoming read channel is connected to a termination. The selection of the interconnection unit 11 in FIG. 1 can be made, for example, when the arrangement is installed.

It will now be assumed that a disturbance occurs, for instance an interruption of one of the connections 37 or 38, in other words both connections between the interconnection units 13 and 14. When the connection 37 is interrupted, the interconnection units 14 to 16 immediately cease to receive data via the write channel. Via the switch 27 and the connection 19, the supply of data to the read channel is also stopped. This is detected after a given delay by the interconnection units 13, 12 and 11, when only the connection 37 is interrupted and the connection 38 is still in order. The latter interconnection units 13, 12, 11 immediately detect a data failure on the read channel only when the interconnection 38 is interrupted. In the latter case the transmission of synchronization information by the synchronization device 31 in the interconnection unit 11 is interrupted. The interconnection units 14 to 16 are thus also informed about an interruption in the read channel, for example in the connection 38. Thus, after a given delay each interconnection unit will in any case have detected that a disturbance has occurred.

Subsequently, all interconnection units 11 to 16 assume the state shown in FIG. 2, i.e. the outgoing write channel in each interconnection unit is connected to the synchronization device 32 which now, however, transmits test information. The incoming read line is connected to the termination and the incoming write line to the outgoing read line. Thus, closed data loops are formed which extend from a respective interconnection unit via the neighboring interconnection unit and back again. For example, the interconnection unit 11 can now test whether the test information transmitted by the synchronization device 31 via the connection 17 correctly arrives again via the connection 18. Moreover, it can also be tested whether further test information is transmitted via the switch 27. When this is the case, the interconnection unit 11 will know that the connections 17, lB and 20 are non-disturbed.

However, an interruption could be present in the connection 19 which interruption cannot be easily detected by the interconnection unit 11. However, when this connection 19 is non-disturbed, the interconnection unit 16 receives its test information again and subsequently transmits acknowledge information which is received by the interconnection unit 11. The interconnection 11 will then also know that the connection 19 is in order. The same is applicable to the other interconnection units.

The testing of the data connections of an interconnection unit after detection of an interruption of the data stream is shown in a flowchart in FIG. 3. The starting point 40 is a predetermined period of time after detection of the interruption of the data stream of the write channel and/or the read channel. Whether test information is received from another interconnection unit is then tested 41. When this is the case, the test information is returned 42. It will be apparent that the fact that an external test information has been received is stored in memory. If the test information transmitted by another interconnection unit also contains the sequence number thereof, this number is also stored.

Subsequently, the interconnection unit's own test information is transmitted 44. The expiration of a predetermined waiting period is tested 45. The waiting period corresponds to the time delay caused by the transmission of the test information, via the connections, to another interconnection unit and the processing therein. Block 46 represents a testing of whether the interconnection unit's own information has been received again from the other interconnection unit before expiration of the waiting period. When this is not the case, one of the two connections involved or the other interconnection unit is disturbed and the test procedure is terminated after block 59. The relevant data connection of the interconnection unit is stored 59 as being disturbed. In the case of the interconnection unit 11 this means that either the connection 17 or the connection 18 or the interconnection unit 12 is defective. In principle, any data connection where only one connection is disturbed is deemed to be defective and is not used for the subsequent reconfiguration.

However, reception of the interconnection unit's own test information in block 46 means that, for example with respect to the interconnection unit 11, the connections 17 and 18 as well as the corresponding data connection and the path in the interconnection unit 12 are in order. In the case of a positive response to the interrogation in the block 41, it has already been established that the connections 20 and the associated section of the interconnection unit 16 are in order. When the connection 19 is also in order, the interconnection unit 16 will subsequently transmit acknowledge information via the connection 20. The acknowledge information is received in the interconnection unit 11, for example at the switch 27, after a corresponding waiting period. This waiting period is completed in the block 47. Whether the acknowledge information has arrived from the other interconnection unit is then tested 48. If this information does not arrive, the connection 19 is interrupted in the case of the interconnection unit 11. In other words, the interconnection unit 16 has not received its test information back again so that it has not transmitted acknowledge information either. The procedure is then again terminated after storage 59 of the fact that the data connection is disturbed. In the case of the interconnection unit 11 the relevant disturbed data connections would be 19 and 20.

However, when the acknowledge information is received 48 from the other interconnection unit, the interconnection unit's own acknowledge information will be transmitted 49. This informs the corresponding other interconnection unit, i.e. the interconnection unit 12 in the case of the interconnection unit 11, that the connection 18 is also in order. The test procedure is subsequently terminated after block 50. Block 50 represents storage of the fact that both data connections, and also the corresponding parts of the neighbouring interconnection units, are in order.

When no test information from another interconnection unit is detected at block 41, the corresponding connection is interrupted or the other interconnection unit transmits the test information only later. In this case the interconnection unit's own test information is transmitted 51. The interconnection unit then tests for the expiration of a predetermined waiting period in block 52, corresponding to the waiting period in block 45. In block 53 the interconnection unit tests whether its own test information has been received again. When this is not the case, the test procedure is terminated via the block 59. When the interconnection unit's own test information has been received again, it has been determined that: the outgoing write channel, the incoming read channel, and the other interconnection unit connected thereto are in order. Then the arrival of the test information from the other interconnection unit is awaited 54. Failure of this test information to arrive means that the relevant data transmission path or the other interconnection unit is disturbed. The test procedure is then again terminated and the fact of the existence of the disturbance is stored again 59. When the test information from the other interconnection unit has arrived, it is returned thereto in block 55. Subsequently, the interconnection unit's own acknowledge information is transmitted in block 56. For the sake of completeness it is noted that this acknowledge information need not be returned or evaluated by the other interconnection unit and no processing step is provided for this purpose.

In block 57 the expiration of a waiting period corresponding to the waiting period in block 47 is tested. This waiting period corresponds to the delay until the test information returned in block 55 has initiated the transmission of acknowledge information. Block 58 indicates the testing of whether the acknowledge information from the other interconnection unit has arrived after expiration of this waiting period. When this is no the case, the corresponding outgoing read line is disturbed and the test procedure is terminated via the block 59. This termination is analogous to the negative decision branch stemming from block 48. However, when the acknowledge information is received from the other interconnection unit, the test procedure is terminated via the block 50. The fact that all data connections or connections and the corresponding parts of the neighbouring interconnection units are in order is stored 50.

Depending on the result of the test in each interconnection unit, this interconnection unit sets its switches 27, 28 and 29. In this way a reconfiguration of the arrangement is obtained in which all interconnection units are again interconnected via a write channel and a read channel as shown in FIG. 4. The interconnection unit 14 has detected that one of the two connections 37 or 38 or both are interrupted because it has not received test information via these connections. As a result the synchronization device 34 is connected to the outgoing write channel and the incoming read channel is connected to the termination. The interconnection units 15, 16, 11 and 12 have each determined that the connections of both data connections are in order. Therefore their respective write channels and read channels are interconnected. The interconnection unit 13, however, has established, like the interconnection unit 14, that at least one interruption is present in the connections 37 and 38. Connections 37 and 30 form the outgoing write channel and the incoming read channel for the interconnection unit 13. Therefore the interconnection unit 13 closes its switch corresponding to switch 27, thus establishing a connection between the write channel and the read channel. It will be apparent that for the described reconfiguration it is unimportant in which location the interruption occurs. Only the interconnection unit in which the synchronizing device is connected to the outgoing write channel could change. When an interruption occurs because an interconnection unit becomes defective, for example the outgoing write channel or the incoming read channel of the interconnection unit 13, the same steps are taken. However, when the interconnection unit 13 is defective to such an extent that the information on the incoming write channel cannot be transmitted via the outgoing read channel, the consequences for the interconnection unit 12 will be the same as if an interruption were present in the connection between the interconnection units 12 and 13. The interconnection unit 12 then assumes the switch position shown for the interconnection unit 13. The interconnection unit 13 is then completely skipped.

Should one or both of the connections lg or 20 also comprise an interruption in the arrangement shown in FIG. 4, the arrangement will be divided into two sections. Each of the two sections will be fully operational but, of course, they will not be able to communicate with one another any longer.

FIG. 5 shows an arrangement which in most cases enables complete reconfiguration of the transmission path through all interconnection units in the event of several defects. This arrangement comprises two groups of interconnection units: A first group comprising the interconnection units 61 to 68, and a second group comprising the interconnection units 71 to 78. Each of the interconnection units comprises three data connections. The three data connections are shown only for the interconnection units 61 and 71 because it is only therein that they ar required for the formation of a complete data transmission path through all interconnection units in the non-disturbed case initially assumed for FIG. 5. For the other interconnection units 62 to 68 and 72 to 78 only two data connections are shown. Actually the third data connection of, for example, the interconnection unit 62 is connected to the third data connection of the interconnection unit 78. Similarly, the third data connection of the interconnection unit 68 is connected to the interconnection unit 72. The same is applicable to all other interconnection units.

Each data connection comprises four lines. In FIG. 5, however, the four lines are only shown completely for the third data connection of the interconnection units 61 and 71. The reference letters and numerals of the four lines at this third data connection have the following meaning (the subscript representing the number of the data connection):

S.sub.3 (S)--outgoing or transmitting line of the write channel,

E.sub.3 (S)--incoming or receiving line of the write channel,

S.sub.3 (L)--outgoing or transmitting line of the read channel,

E.sub.3 (L)--incoming or receiving line of the read channel.

For the first and second data connections of all interconnection units, only two lines are shown, that is to say the lines S.sub.1 (S) and S.sub.1 (L) for the first data connection of the interconnection unit 61. These lines are connected via connections 69 and 70, to the incoming lines E.sub.2 (S) and E.sub.2 (L), respectively, of the interconnection 62. The line S.sub.1 (S) of the interconnection unit 61 is in this case connected to the synchronization device 80; it is to be noted that such a synchronization device is included in each of the other interconnection units, but is not used therein, so that it has been omitted for the sake of simplicity. The data transmission path departing from the synchronization device 80 extends via the connection 69 through the interconnection unit 61 and subsequently through the further interconnection units 61 to 68 and back to the interconnection unit 61 again via the incoming line E.sub.2 (S) thereof. The data transmission path represents a write channel which interconnects all interconnection units 61 to 68 of the first group. The second data transmission path which departs from the interconnection unit 61 also interconnects all the interconnection units 61-68. This second data transmission path extends via the line S.sub.1 (L) and the connection 70 through the interconnection unit 62 and the further interconnection units 63 to 68 in the same direction as the write channel. The second data transmission path subsequently enters the interconnection unit 61 again via the line E.sub.2 (L). This second path represents a read channel. Similarly, in the second group of interconnection units 71 to 78, the data transmission path which departs from the interconnection unit 71 and which extends, via the line S.sub.1 (S) and the connection 79, through the interconnection unit 72 and subsequently through all other interconnection units 73 to 78 and back again to the interconnection unit 71, represents the write channel of the second group. Similarly, the transmission path starting from the line S.sub.1 (L) of the interconnection unit 71 and extending through all interconnection units of this group via the connection 80 represents the read channel of this group. The write channel 69 of the first group is split in the interconnection unit 61 and connected, via the line S.sub.3 (S), to the interconnection unit 71. Similarly, the write channel 79 of the second group is split in the interconnection unit 71 and the return write channel is connected via the line E.sub.3 (S), to the interconnection unit 61 of the first group.

If the line E.sub.3 (S) were coupled to the line S.sub.1 (S) inside the interconnection unit 61, as in the arrangements known from the prior art discussed in the preamble, a fully closed transmission path would be obtained. Via this path any interconnection unit could exchange messages with any other interconnection unit of the same group or the other group. The read channel 70 or 80 could then be used as a spare channel in the case of a reconfiguration necessitated by disturbances. In that case, however, the direction of the data would have to be reversed in comparison with the direction shown. In this case only two lines per data connection would be required in each interconnection unit.

Hereinafter, however, it is assumed that the read channel and the write channel are separated as has already been described with reference to FIG. 1. To this end, the write channel, after having passed through all interconnection units at least once, is connected to the outgoing read channel S.sub.1 (L) when it arrives at the line E.sub.3 (S) in the interconnection unit 61, i.e. to the read channel which subsequently also passes through all interconnection units at least once. When the read channel again arrives in the interconnection unit 61 via the line E.sub.3 (L), it is connected to a termination.

It will be apparent that in FIG. 5 the connections of the third connections of the interconnection units 62 to 68 and 72 to 78 are not the only connections which are not shown. In addition the first and the second data connections are not shown, that is to say parallel to the write channel 69 to 79 and parallel to the read channel 70 to 80. Data transmission in those lines which are not shown is required only in the case of a disturbance. Such data transmission would be the direction opposite to the write channel 69, 79 and the read channel 70, 80.

A disturbance may occur in the arrangement shown in FIG. 5 due to interruption of a connection of a connection or a defect in an interconnection unit. In such a case the information stream transmitted by the synchronization device 80 is interrupted. All interconnection units will then recognize such an interruption. There will merely be a delay in the recognition which depends on the location where the failure occurs. All interconnection units will then enter a test state as shown in FIG. 6.

FIG. 6 shows four interconnection units. The interconnection units 66 and 67 form part of the first group. The interconnection units 73 and 74 form part of the second group. All four connections of each data connection of these interconnection units to one another and to the neighbouring interconnection units (not shown) are fully represented. In each of the connection bundles 86 to 89, an outgoing write line S.sub.x (S) is connected to the incoming write line E.sub.x (S) of the other interconnection unit. The outgoing read line S.sub.x (L) is connected to the incoming read line E.sub.x (L) of the other interconnection unit. The index x denotes the number of the data connection. The first data connection of an interconnection unit is connected to the second data connection of the other unit while the third data connections of each pair of interconnection units are connected. For realizing the connections of the individual lines shown, a double-crossing of connections occurs in the connection of the third data connections, as indicated for the connection bundles 88 and S9. No crossing of the individual connections occur in the connection bundles 86 and 87, because the sequence of the lines on the second data connection is chosen to be different from the sequence of the lines on the first data connection.

For all three data connections in each interconnection unit: the outgoing write line S.sub.x (S) is connected to the synchronization device 81, 82, 83, 84 respectively; and the incoming read line E.sub.x (L) is connected to a termination. Furthermore, in each interconnection unit the incoming write line E.sub.x (S) is connected to the outgoing read line S.sub.x (L) for each data connection. Consequently, each interconnection unit receives the test information, transmitted via an outgoing write line S.sub.x (S), on the incoming read line E.sub.x (L) of the same data connection, when the two relevant connections are in order. Furthermore, on each incoming write line E.sub.x (S), test information is received from another interconnection unit when the relevant connection is in order. This information is returned via the outgoing read line S.sub.x (L). All in all a test procedure as described with reference to FIG. 3 is performed for each data connection. After termination of the test procedure, the state of all four connections of each data connection is known in all interconnection units. For example, for the interconnection 66 the state of all connections in the connection bundles 85, 86 and 89 is known. The state of the connections includes the state of the two interconnection units or the relevant section connected by the connections. Moreover, after termination of the test procedure it will be known for each interconnection unit whether one of the neighbouring interconnection units has a higher or a lower sequence number.

At this point all interconnections units have been informed about the state of the connections at each of their three respective data connections. However, the final interconnections of the individual lines of the three data connections cannot be completely established until after a determination of the sequence of the first synchronization information and a determination of which data connections the first synchronization information arrives at. The synchronization information is generated by the interconnection unit in which at least the first data connection is in order and which has the lowest sequence number. This means that the interconnection unit has not found any neighbouring interconnection unit having a lower sequence number. The synchronization device of the appropriate interconnection unit is then connected to the line S.sub.1 (S). The synchronization information transmitted via this line then passes through a series of interconnection units whose number and sequence depend on the position of the relevant disturbed locations. As a result, the synchronization information returns to the unit that originally generated it. It returns via the incoming line of the write channel of one of the data connections. It will be apparent that this particular write channel can only be a non-disturbed data connection. However, it may occur that the synchronization information returns before having passed through all interconnection units which still cohere by way of at least one data connection. If this occurs the returned synchronization information must still be transmitted to the other interconnection units via an outgoing line of a data connection. However, when the synchronization information returns in the source interconnection unit after having passed through all interconnection units, it is applied to the read channel in the interconnection unit which generated the synchronization information. These different conditions are recognized, in the interconnection unit generating the synchronization, only on the basis of the data connection and the sequence in which the synchronization information arrives on an incoming write line. Subsequently, the individual interconnections inside the interconnection unit generating the synchronization information are established. The arrow indicates which incoming line is to be connected to which outgoing line. For the sake of clarity, only the lines of the write channel are indicated because the corresponding lines of the read channel are interconnected in exactly the same way. However, at the location where the incoming write channel is connected to the outgoing read channel, the incoming read channel is connected to a termination.

1. It will first be assumed that all three data connections of the interconnection unit generating the synchronization information are in order.

(1a) When the first synchronization information returns on the incoming lines E.sub.1 (S) or E.sub.2 (S) for the first time:

(1b) When the first synchronization information returns on the incoming line E.sub.3 (S) for the first time, this line is connected to the outgoing line S.sub.2 (S). The arrival of the synchronization information on such an input, however, signifies that not all feasible interconnection units have already been passed through and that the first synchronization information will arrive once more in the interconnection unit generating this information. As soon as this is the case, the input on which the synchronization information arrives for the second time is connected to the outgoing read channel. The other incoming write line on which no further synchronization information arrives and which is not included in the overall data path, can be connected to a termination in order to create predetermined conditions. In detail, the following interconnections are ultimately obtained:

(1b1) When the synchronization information arrives a second time via the line E.sub.2 (S)

(1b2) When the synchronization information arrives a second time via the line E.sub.1 (S)

2. It is now possible, as in the case of a corresponding distribution of disturbed locations, that the second or the third data connection of the interconnection unit generating the synchronization information is defective. However, this is known in this interconnection unit as a result of the test procedure. As soon as the synchronization information returns once to the source interconnection unit on the incoming line of one of the two non-disturbed data connections, it is unambiguously determined that it must arrive a second time. The second arrival will be via the incoming line of the write channel of the other data connection. In this way the data paths to be interconnected are known at the same time. In individual cases interconnection is necessary.

(2a) If the data connection 3 is defective and:

(2a1) if the synchronization information arrives for the first time on the incoming line E.sub.1 (S), then

(2a2) if the synchronization information arrives for the first time on the incoming line E.sub.2 (S), then

(2b) If the data connection 2 is defective and:

(2b1) if the synchronization information arrives for the first time on the line E.sub.1 (S), then

(2b2) if the synchronization information on the line E.sub.3 (S) arrives for the first time, then

(2c) If the second and the third data connection are defective, then the data path to be connected is

All combinations of states which can occur in the interconnection unit generating the synchronization information have thus been taken into account. For each state, ultimately unambiguous interconnection of the data paths takes place.

For the other interconnection units which do not generate the synchronization information, the data paths to be interconnected are determined similarly. That is to say, the data paths are determined no later than upon the first arrival of the synchronization information unless the data paths to be interconnected are directly determined, e.g. where there are defects in data connections.

3. If all data connections are in order

(3a) and the synchronization information arrives on the line E.sub.2 (S) for the first time, then:

(3b) However, if the synchronization information appears for the first time on one of the lines E.sub.1 (S) or E.sub.3 (S), then:

4. However, if data connections are defective, the following interconnections of data paths take place:

(4a) if the data connection 1 is defective, then:

(4b) if the data connection 2 is defective, then:

(4c) if the data connection 3 is defective, then:

(4d) if only one of the data connections is in order, the incoming write line is connected to the outgoing write line at this connection

The data connections to be established for all possible combinations of states of the data connections are thus unambiguously defined. As has already been described, the lines of the read channels are interconnected in the same way as the lines of the write channels.

FIG. 7 again shows the arrangement of FIG. 5, but the connections of the individual interconnection units and the data transmission path thus formed are shown after the reconfiguration initiated by disturbances occurring at the locations denoted by crosses. For the sake of simplicity it is assumed that the sequence numbers assigned to the interconnection units are the same as their reference numerals.

Because the interconnection unit 61 has the lowest sequence number and no disturbance has occurred on its first data connection, this interconnection unit remains the unit whose synchronization device 80 generates the synchronization information. Furthermore, it can be deduced from FIG. 7 that the second and the third data connection of the interconnection unit 61 are also in order. Thus, the conditions mentioned in numbered paragraph 1 hold for the interconnection of the data paths within the interconnection unit 61, i.e. the interconnection unit 61 must wait to see at which data connection the synchronization information appears again for the first time.

The synchronization information transmitted via the line S.sub.1 (S) is first applied to the input E.sub.2 (S) of the interconnection unit 62. It has been assumed that the third data connection thereof, i.e. the connection to the interconnection unit 78, is disturbed. Therefore interconnection condition 4c holds for the interconnection unit 62. In other words all lines of the second data connection are connected to the corresponding lines of the first data connection. From the line S.sub.1 (S) of the interconnection unit 62 the synchronization information then proceeds to the connection E.sub.2 (S) of the interconnection unit 62 in which, however, the data connection 1 is disturbed. Consequently, this interconnection unit is subject to condition 4a. Therefore all lines of the second data connection are connected to the corresponding lines of the third data connection. Consequently, the synchronization information is applied from the interconnection unit 63, via the line S.sub.3 (S), to the line E.sub.3 (S) of the interconnection unit 77. Because the first as well as the second data connection thereof is defective, this unit is subject to the interconnection condition 4d. In this way, the synchronization information returns to the line E.sub.1 (S) of the interconnection unit 61 via the line S.sub.3 (S) of the interconnection unit 77 and the interconnection units 63 and 62. Consequently, the interconnection unit 61 is subject to the interconnection condition 1a, i.e. the returned synchronization information is applied to the interconnection unit 68 via the line S.sub.2 (S).

The interconnection conditions for the other interconnection units can be found similarly. Ultimately, the data transmission paths shown in FIG. 7 are formed. As shown there, a complete write channel is formed which commences at the interconnection unit 61, extends through this unit again after return on the line E.sub.1 (S), and ultimately returns to the interconnection 61 from the interconnection unit 71 on the line E.sub.3 (S). The write channel terminates in interconnection unit 61 and is connected to the beginning of the read channel. The read channel commences via the output S.sub.1 (L) and which extends through all interconnection units parallel to the write channel. The described interconnection conditions thus enable a reconfiguration of the arrangement to be obtained even in the case of a large number of disturbed locations. All interconnection units which have at least one data connection which is connected to other interconnection units are then involved in the common data transmission path. In the case of certain disturbances, for example in the connection between the interconnection units 62 and 63, only one connection can be established between the latter unit and the interconnection unit 77 so that messages can be exchanged between these two interconnection units. However, in this case connection to the other interconnection units is no longer possible.

A corresponding reconfiguration of a transmission path which includes as many interconnection units as possible is also feasible. For example, in the non-disturbed case two fully separated groups of interconnection units may be present. In this case, one group may serve for the transmission of data, while the other group serves for the transmission of digitized speech information. The connection between the interconnection units 61 and 71, for example, in FIG. 5, therefore, would not be used initially. In the interconnection unit 61, the incoming line E.sub.2 (S) of the write channel would then be initially connected to the outgoing line S.sub.1 (L) of the read channel. The interconnection unit 71 would be connected in exactly the same way. It is only when a multiple disturbance in at least one of the groups inhibits data transmission between all interconnection units that the connections of the interconnection units of different groups via the third data connections are used. In this way, a data path is formed which covers all interconnection units in the described manner. In this case, data as well as digital speech is transmitted via the third data connections.

FIG. 8 shows an array of switches in an interconnection unit. The array of switches enables the described interconnection of the individual transmission paths to be simply realized. Therein, all elements which are not required for the following explanation have been omitted inside the interconnection unit A. For instance, in addition to the switches, only the synchronization device S.sub.y is shown.

Block SS contains the switches which establish the connections for the data paths of the write channel. Block LS contains the switches which establish the connections for the data paths of the read channel. The block SL contains the switch which can connect an incoming line of the write channel to the beginning of the read channel. The switches SP1 and SP2 serve for the interconnection of the test information. Furthermore, for each of the incoming lines E.sub.x (S) of all three incoming lines of the write channel there is provided a write channel termination switch SA1, SA2 and SA3. The write channel termination switch SA1, SA2, SA3 connects the relevant incoming line to a termination in order to prevent high-frequency interference from open lines. Similarly, for each incoming line E.sub.x (L) of the read channel, there is provided a read channel termination switch LA1, LA2 and LA3 which connects the relevant incoming line to a termination. These termination switches can be closed when, because of the relevant interconnection state of the other switches, no information enters via the relevant incoming line or when the information on the incoming line of the read channel is not be transmitted further. All switches are constructed as electronic switches.

The outgoing transmission line S.sub.1 (S) is connected to the switch SG. The switch SG connects this line to the connections a of the switches SS1, SS2 and SS3 in its position a. In the position a, the switch SS1 connects the outgoing write line S.sub.1 (S) to the incoming write line E.sub.1 (S) of the same data connection. In the position a, the switch SS2 connects the outgoing line S.sub.1 (S) of the write channel to the incoming line E.sub.2 (S) of the write channel of the data connection 2. The switch SS3 similarly connects the outgoing line S.sub.1 (S) of the write channel to the incoming line E.sub.3 (S) of the write channel of the third data connection in its position a. Only one of the switches SS1 to SS3 can occupy the position a at a given instant. In the other positions, these switches SS1 to SS3 connect the outgoing lines of the write channel of the other two data connections to a respective incoming line of the write channel of one of the data connections. Similarly, in the position a, the switches LS.sub.1 to LS.sub.3 connect the outgoing line S.sub.1 (L) of the read channel to an incoming line of the read channel of one of the data connections. It is again impossible for the three switches to occupy the same position simultaneously.

The switch SL connects the outgoing line S.sub.1 (L) of the read channel of the first data connection to one of the incoming lines E.sub.x (S) of the write channel of one of the data connections or, in the position d, to none of the incoming lines of the write channel. In this case the outgoing line S.sub.1 (L) of the read channel is connected, via the switches LS.sub.1 to LS.sub.3, to an incoming line of the read channel of one of the data connections. Connection of the outgoing line S.sub.1 (L) to several sources is avoided. This is accomplished because in any of the positions a to c, of the switch SL, the input of the relevant switch LS1 to LS3 is separated from the corresponding incoming line of the read channel by the relevant switch LAx. The relevant switch LS.sub.1 to LS.sub.3 is then in position a.

In the position b of the switch SG, the synchronization device Sy is connected to the outgoing line S.sub.1 (S) of the write channel of the first data connection. This is the normal position when the relevant interconnection unit A is to generate the synchronization information. This position b of the switch SG is also adjusted when test information is to be transmitted. Furthermore, the switches SP1 and SP2 are then closed, so that test information is also transmitted via the outgoing lines S.sub.1 (S) and S.sub.3 (S) of the write channels of the two other data connections. The incoming line E.sub.x (S) of the write channel of each data connection is connected to the outgoing line S.sub.x (L) of the read channel. The test configuration shown in FIG. 6 is thus obtained.

Th.RTM.connections of all necessary data paths can thus be established in a simple manner. The control of the individual switches is realized by a control system (not shown) which is preferably constructed as a microcomputer.

FIGS. 9a to 9c illustrate another possible reconfiguration of an arrangement of interconnection units in response to disturbances. The interconnection units have three data connections in the case of disturbances. This solution consists in the formation of a write and a read channel which include all interconnection units which are still connected. FIG. 9a shows twelve interconnection units 90 to 101. Initially, before the occurrence of a disturbance, all these units are interconnected via the connections between the data connections 1 and 2. Thus, a write channel (denoted by a solid line) is formed which covers all interconnection units 90 to 101. A corresponding read channel, denoted by a broken line, is also formed. To this end, the write channel and the read channel in the interconnection unit 93 were connected to the line 102 of the data connection 1 and the lines 103 of the interconnection unit 94. In the interconnection unit 94 the write line and the read line were also connected to the data connection 1. Similarly, in the interconnection unit 97, the lines 104 were connected at the data connection 1 to the lines 105 of the data connection 2 of the interconnection unit 98. Similarly, the lines 106 of the interconnection unit 101 were connected to the lines 107 of the interconnection unit 90. In an arbitrary interconnection unit the synchronization device was connected to the write line and the read line was connected to a termination. In this arbitrary interconnection unit or the preceding interconnection unit the connection between the write channel and the read channel was present. Overall an arrangement is assumed as shown in principle in FIG. 1. In FIG. 1 actually even more interconnection units can be present and follow, for example, the lines 102, 104 and 106, so that a correspondingly larger but otherwise simple loop is obtained for the write and the read channel.

In FIG. 9a it is assumed that the connections between the lines 102 and 103, 104 and 105 as well as between 106 and 107 are interrupted or disturbed so that no orderly data transmission can be performed thereon. Each interconnection unit detects these disturbances, as before, by interruption of the data stream on the write and the read channel. Each interconnection unit then transmits test information via at least the first and the second data connections. After transmission and evaluation of the test information, the interconnection units which are connected to another interconnection unit via the first and or the second data connection are connected pairwise. In this way they form their own sub-arrangement, in the manner described with reference to the FIGS. 2 to 4. Thus, in any interconnection unit in which the external connections are in order at the data connection 1 and in which the external connections are disturbed on its data connection 2, the write channel is connected to the synchronization device and the read channel is connected to a termination. This is shown for the interconnection units 90, 94 and 98. In the interconnection units in which the external connection is disturbed at the data connection 1 and the external connection is in order at the data connection 2, the write channel is connected to the read channel. Thus, the interconnection of the interconnection units as shown in FIG. 9a is obtained. No data are transmitted yet via the data connections 3. Thus, three sub-arrangements are obtained within which the interconnection units can exchange messages; however, they cannot exchange messages with interconnection units forming part of another sub-arrangement.

In order to enable the latter exchange, all interconnection units exchange test information via the connection of their data connections 3. Said information always contains the sequence number of the interconnection unit in the sub-arrangements in which the write channel is connected to the synchronization device. This happens because this sequence number has been transmitted to all interconnection units of each sub-arrangement during the reconfiguration of the write channel already performed. It is assumed that a non-disturbed connection 108 or 109 is detected between the interconnection units 92 to 96 as well as between 95 and 99, respectively. These non-disturbed connections are the third connections. The third connections of the other interconnection units, for example, are also liable to be disturbed or it may be that some units thereof are not connected in order to enhance the simplicity of the connections. This depends on the relevant application and the probability of occurrence of disturbances at given locations. The exchange of test information via the data connections 3 can take place without disturbing the data transmission on the write and read channels extending via the data connections 1 and 2.

During the evaluation of the test information it may occur, notably when a sub-arrangement includes a large part of the total number of interconnection units present, that the same sequence number is contained in the test information of individual interconnection units. This means that these interconnection units belong to the same sub-arrangement and are already interconnected via the data connections 1 and 2.

These interconnection units are not involved in the further reconfiguration of the overall arrangement. However, when an interconnection unit has received another sequence number in the test information received on the data connection 3 (like the interconnection units 92, 95, 96 and 99 in FIG. 9a), this sequence number is transmitted, via the already existing write and read channel to the interconnection unit in which the synchronization device is connected to the write channel. Thus, in each of the interconnection units 90, 94 and 98 it is known which sequence numbers are assigned to the neighbouring sub-arrangements.

When a sub-arrangement receives a sequence number having a higher priority, i.e. a sequence number which is lower than its own sequence number, this sub-arrangement transmits an acknowledgement to the sub-arrangement having the lowest sequence number. The acknowledgement is transmitted via the interconnection unit which is situated nearest to the beginning of the write channel. Thus, the fact is taken into account that a sub-arrangement can communicate with the same other sub-arrangement via several interconnection units. This is because an unambiguous location must be determined for the subsequent interconnection of the two sub-arrangements. The sub-arrangement having the lowest sequence number then returns an acknowledgement only to the sub-arrangement having the next-higher sequence number. This is because a plurality of sub-arrangements having different sequence numbers can directly communicate, independently from one another, with the sub-arrangement which has the highest sequence number. However, interconnection of that sub-arrangement has not yet taken place. Only the sub-arrangement receiving the acknowledgement enters a waiting state in which the beginning of the write channel in the interconnection unit is disconnected from the synchronization device and connected to the incoming line of the unused write channel. Similarly, the incoming line of the read channel, thus far connected to a termination, is connected to the outgoing line of the unused read channel. This is applicable to the data connection 1 of this interconnection unit, i.e. the interconnection unit 94. Similarly, the incoming and outgoing lines of the data connection 2 of the interconnection unit 97 at the other end of each sub-arrangement are interconnected.

At the end of a frame, the sub-arrangement having the lowest sequence number then separates the read channel and the write channel in the interconnection unit having received the lowest sequence number from the other sub-arrangement. This lowest sequence number from the other sub-arrangement is the next-higher sequence number in comparison with the sequence number of the relevant interconnection unit, i.e. the interconnection unit 92. The sub-arrangement connects the ends of the relevant interconnection unit to the corresponding line connections of the data connection. In this way the write channel and the read channel are connected, via the connection 108 and the data connection 3 of the interconnection unit 96, to the write channel and the read channel which are also separated therein. Thus from the above two sub-arrangements a new sub-arrangement is formed. The new sub-arrangement comprises the interconnection units 90 to 97. Said new sub-arrangement also comprises a write channel which extends from the interconnection unit 90 to the interconnection unit 93 and a read channel which returns therefrom to the interconnection unit 90. The first synchronization information which subsequently arrives via the newly formed write channel then interconnects two sub-arrangements into a new, larger sub-arrangement. This new larger sub-arrangement comprises a write channel and a read channel covering all interconnection units as shown in FIG. 9b. The new sub-arrangement has the sequence number of the interconnection unit 90. Special control information ensures that the information gap occurring during switching over is not interpreted as a disturbance initiating a reconfiguration.

The new sub-arrangement, consisting of the interconnection units 90 to 97, must now be connected to the original third sub-arrangement. The triangle third sub-arrangement comprises the interconnection units 98 to 101. The described procedure is therefore repeated between the two sub-arrangements now present. In other words, in the interconnection units 98 to 101 the line connections of the write channel and the read channel are connected as in the interconnection units 94 to 97. In addition, in the interconnection units 95 and 99, these channels are interrupted and interconnected via the connection 109 between the data connections 3. Ultimately, an arrangement is obtained as shown in FIG. 9c in which all interconnection units 90 to 101 are interconnected via a common write channel and read channel.

It will be apparent that such a reconfiguration can also be carried out for other disturbed locations or for other interconnections of interconnection units, via the data connections 3. For example, let us assume that a connection is present between the data connections 3 of the interconnection units 93 and 101 and that the lower sub-arrangement consisting of the interconnection units 98 to 101 has a lower sequence number than the central sub-arrangement. The central sub-arrangement consists of the interconnection units 94 to 97. The upper and the lower sub-arrangement would then first be interconnected in a similar manner, and subsequently the central sub-arrangement would be connected thereto. A write channel and a read channel covering all interconnection units would again be obtained, but with a slightly different route from that shown in FIG. 9c; however, data transmission would again be possible from any interconnection unit to any other interconnection unit.