Protection Circuit for an Insulated Gate Bipolar Transistor Utilizing a Two-Step Turn Off

1. Field of the Invention

This invention relates to a driving circuit for an insulated gate bipolar transistor (hereinafter referred to as IGBT) which drives the gate of the IGBT safely without accompanying overcurrent phenomena.

2. Prior Art

Many types of power converters which convert d.c. to a.c. or d.c. to d.c. using IGBT elements have been proposed. This IGBT has an insulated gate and is operated in a bipolar mode. The IGBT has features of short switching time and low ON voltage. Therefore this element enables miniaturization, low cost and high frequency control of high power which cannot be performed by conventional bipolar transistors or MOS FETs.

FIG. 1 is a circuit diagram of a fundamental chopper using an IGBT. According to FIG. 1, an IGBT 1 and a load 3 are connected in series to both terminals of a d.c. power source 2. Power is supplied to the load 3 by on-off controlling the IGBT 1.

In order to achieve on-off control of the IGBT 1, serially connected power sources 4 and 5 for gate and serially connected NPN transistor 6 and PNP transistor 7 are connected in parallel, and the common connection point of transistors 6 and 7 is connected to the gate terminal of IGBT 1. Moreover, the bases of transistors 6 and 7 are commonly connected to an input terminal 8 for the driving voltage.

When a positive signal is applied to the input terminal 8, transistor 6 turns on and the positive voltage is supplied to the gate of the IGBT 1 from the power source 4, resulting in turning-on of the IGBT 1.

On the other hand, when a negative signal is applied to the input terminal 8, negative voltage is supplied to the gate of the IGBT 1 to turn it off.

In this case, the relation between ON voltage, that is a collector to emitter voltage V.sub.CE when the IGBT is in the ON state, and the ON current, that is, a collector current I.sub.C when the IGBT is in the ON state, is shown in the graph of FIG. 2. The relation between the collector to emitter voltage and the maximum collector current I.sub.CMAX is shown in FIG. 3.

It will be seen from FIG. 2 that the IGBT has intermediate characteristics between transistor and thyristor, that is, it shows constant current characteristics similar to transistors in low gate voltage areas and low voltage drop in high gate voltage areas.

It is apparent that if the IGBT is driven at a higher gate voltage V.sub.GE and the lower is the ON voltage V.sub.CE, thus the power loss of the IGBT 1 is decreased.

However, there is a problem that the IGBT often breaks down due to overcurrent within the range as shown by hatching lines in FIG. 3, when a shortcircuit accident of the load 3 in FIG. 1 occurs, because the voltage of d.c. power source is directly applied across the collector and emitter.

Considering such accident, if the IGBT is driven at a low gate voltage V.sub.GE, there occurs another problem that the power loss increases because the voltage V.sub.CE increases.

FIG. 4 shows the switching characteristics of an IGBT, in which collector to emitter voltage V.sub.CE begins to drop with a time delay Td after turning the gate voltage V.sub.GE from negative to positive, and it drops below 10 V at Tf. For a high speed IGBT, Td is approx. 0.5 .mu.s and Tf is approx. 1 .mu.s.

Thus, it is difficult to determine whether a shortcircuit accident occurs or not unless it is determined whether the high collector to emitter voltage is caused by either overcurrent or transient phenomena, since the turn-on operation has the above-mentioned delay in relation to the gate voltage V.sub.GE.

In the case of some types of IGBT, a direct shortcircuit is prohibited.

As to such type of IGBT, IGT (Insulated Gate Transistor) of GE corporation is known and introduced in, for example, "Application of Insulated Gate Transistors" (Factory Electronics, 1983).

FIG. 5 shows the safe operation area (SOA) of such IGBT and it is understood that, for example, the element having gate to emitter resistance R.sub.GE =5k can always be operated safely if the collector current is limited to 20 A or less.

However, if a current larger than the rated maximum current is turned off, the so-called latch-up phenomena occurs and the collector current I.sub.C cannot be made to 0 when the gate voltage V.sub.GE is made to 0. Moreover the element will be damaged because of an increase in current density in the element. Therefore it is necessary to prevent the IGBT operation beyond the SOA.

It is an object of the present invention to provide a driving circuit for IGBT which can decrease the power loss during normal operation.

It is another object of the present invention to provide a driving circuit for IGBT which prevents the damage of the IGBT when an overcurrent accident occurs.

Therefore, according to the present invention, there is provided a driving circuit for an insulated gate bipolar transistor comprising: a power source for supplying a constant voltage; a gate voltage input circuit for applying said constant voltage to a gate terminal of an insulated gate bipolar transistor according to a control signal; a detecting circuit for detecting a collector to emitter voltage of said insulated gate bipolar transistor; and an adjusting circuit for lowering the control signal voltage according to the output of the detecting circuit, whereby said gate voltage is reduced.

In the accompanying drawings:

FIG. 1 is a circuit diagram of a conventional driving circuit;

FIG. 2 is a graph showing the relation between V.sub.CE and I.sub.C ;

FIG. 3 is a graph showing a safe operation area (SOA);

FIG. 4 is a timing chart showing the switching characteristics of an IGBT;

FIG. 5 is a graph showing the SOA of some types of IGBT;

FIG. 6 is a circuit diagram of a preferred embodiment of the invention;

FIG. 7 is a timing chart illustrating the operation of the circuit shown in FIG. 7;

FIG. 8 is a circuit diagram of a preferred embodiment of the invention;

FIG. 9 is a further preferred embodiment of the invention;

FIG. 10 is a timing chart illustrating the operation of the circuit shown in FIG. 10;

FIG. 11 is a still further preferred embodiment of the invention;

FIG. 12 is a circuit diagram of another preferred embodiment of the invention;

FIG. 13 is a graph illustrating the relation between V.sub.CE and V.sub.GE in the circuit shown in FIG. 13;

FIG. 14 shows the operation obtained by controlling the gate voltage; and

FIGS. 15, 16, 17, 18 and 19 are circuit diagrams of preferred embodiments of the invention.

FIG. 6 is a circuit diagram of an embodiment of the present invention and the same reference numerals as shown in FIG. 1 denote the same elements.

In FIG. 6, IGBT 1 and a load 3 are connected in series to a d.c. power supply 2. Power supplies 4 and 5 are connected in series to each other and to NPN transistor 6 and PNP transistor 7. The two transistors are connected complementarily.

The bases of transistors 6 and 7 are commonly connected to the input terminal 8. A series circuit composed of a resistor 10, a capacitor 18, resistors 19 and 20, and a series circuit composed of a resistor 12, a light emitting diode 13a of a photo coupler 13 and transistor 14 are connected across the input terminal 8 and the common connecting point between power supplies 4 and 5.

The common emitter connecting point of transistors 6 and 7 is connected to the gate of IGBT 1 through a resistor 11. The base of the emitter-follower transistor 14 is connected to the positive electrode of the power source 5 through a diode 15, then connected to the negative electrode of the power source 5 through a resistor 16, and then connected to the collector of IGBT 1 through a resistor 17.

An NPN transistor 21 is provided across the base of the transistor 14 and the positive electrode of power source 5, and the base of transistor 21 is connected to the common connection point of resistors 19 and 20.

A photo transistor 13b of the photo coupler 13 is connected to the positive power source, not shown, through a resistor 24, and this transistor 13b converts the voltage generated at the common connection point of the transistor 13b and the resistor 24 to the logic level. This logic level signal is input to the latch circuit 23 and the output of the latch circuit 23 is input to an AND circuit which outputs logical multiplication of the output of latch circuit 23 and the control signal V.sub.G.

The operation of the circuit shown in FIG. 6 is explained referring to a timing chart shown in FIG. 7. In FIG. 7, (a) shows the gate voltage of IGBT 1, (b) ON and OFF states of the transistor 21, (c) collector to emitter voltage of IGBT 1 and (d) the collector current of IGBT 1. In these charts, the continuous line denotes the condition when no abnormality exists in the load 3 and the short dashes line denotes the condition when the load 3 is in a shortcircuit state or near a shortcircuit state.

First, when the load 3 is in a normal state, at the time t.sub.0, the driving signal V.sub.s changes from negative to positive, transistor 21 becomes ON after a predetermined time t.sub.3 obtained by the capacitor 18 and the resistor 19 which form a differential circuit, because the base current is supplied to the transistor 21. When the transistor 21 turns on, the base and emitter of the transistor 14 are shortcircuited and the transistor 14 turns off, thus no current flowing through the light emitting diode of the photocoupler. Therefore the voltage V.sub.8 becomes high, and after this high level signal is amplified, it is applied to the gate of IGBT 1 as the gate voltage V.sub.GE. As described above, IGBT turns on with the delay time Td, starts turn-on operation at t.sub.1 and finishes the turn-on operation at t.sub.2.

At t.sub.3, transistor 21 turns off and a reverse bias voltage is applied across the base and emitter of the transistor 14 because the bias voltage is generated by the current which flows through the diode 15 and the resistor 16. Therefore, the transistor 14 does not turn on unless the current from the collector of IGTI flows therethrough and through the resistor 17 more than the current flows through the diode 15 and the resistor 16.

In this embodiment, the value of the resistor 17 is selected so that the transistor 14 is turned on when the collector to emitter voltage V.sub.CE becomes 10% of the value of the d.c. power source 2.

Thus, if the transistor 21 is turned off, the transistor 14 does not turn on, thus the gate voltage V.sub.GE being held positive during the term when the control voltage V.sub.G is positive, and the collector current I.sub.C flows as shown in FIG. 7(d). After t.sub.3 when the collector to emitter voltage V.sub.CE is 1 V or less, the IGBT can be driven in a low loss mode.

Next, if the load 3 is in a near shortcircuit condition, and at t.sub.0 the driving signal V.sub.S changes from negative to positive, the IGBT initiates a turn-on operation and the collector current I.sub.C ' increases rapidly. When the collector current I.sub.C ' of IGBT 1 reaches 3 times to 6 times of the rated current, the collector to emitter voltage V.sub.CE ' also increases rapidly As a result, when the current more than the bias current which is determined by the resistance of the resistor 16 and the voltage of the power source 5 flows, the transistor 14 is turned on. Consequently, the driving signal V.sub.S is divided in voltage by the resistors 10 and 12, and the gate voltage V.sub.GE ' drops below the half of the peak value at time t.sub.4.

When the gate voltage V.sub.GE ' drops as shown in FIG. 7, the operation mode of the IGBT 1 enters in the area where the collector current is small and the collector to emitter voltagge V.sub.CE ' tends to increase. Moreover, since the IGBT has a constant current characteristic within the range, the collector current I.sub.C ' decreases rapidly.

Because of turning on the transistor 14, the light emitting diode 13a of photocoupler 13 is supplied with current to emit light, and the receiver, the phototransistor 13b turns on and the input voltage of the latch circuit 23 drops. Since the latch circuit 23 has a delay element, the output of the latch 23 changes to "L" level at t.sub.5. Accordingly, the driving signal V.sub.s changes to "L" level, even if the control signal V.sub.G having "H" level is input to the AND circuit 22. Therefore the gate voltage V.sub.GE ' turns a negative value to break the accidental current, and then the collector current I.sub.C ' becomes exactly 0.

The reason why the latch circuit has the delay element is to prevent misoperation and to suppress the surge voltage during breaking operation by the two step breaking operation in which the accidental current is decreased at t.sub.4 in FIG. 7 first and then the collector current is made to 0. It is identified that the effective time interval between t.sub.0 and t.sub.3 is 2-3 .mu.s and that the effective time interval between t.sub.3 and t.sub.5 is 5-10 .mu.s.

FIG. 8 is a circuit diagram of another embodiment according to the present invention, and the elements referred to by the same numerals as in FIG. 6 show the same elements. In order to supply a charge current having a time constant, that is, the current flowing through the capacitor 18 and resistors 19 and 20, to the diode 15, the emitter of the transistor 21 is connected to the negative electrode of the power source 5 through a resistor 30, and the terminal of the resistor 20 is connected to the negative electrode of the power supply 5.

According to FIG. 8 the collector current of transistor 21 once increases at an instant when the driving signal V.sub.S turns positive, and then it decreases exponentially.

This circuit composition makes it possible to detect accidents faster according to the decrease in the collector to emitter voltage V.sub.CE which occurs based on the turning-on characteristics of the IGBT 1.

FIG. 9 is a circuit diagram of a further embodiment according to the present invention. In comparing this embodiment to FIG. 6, it may be seen that the series-connected circuit composed of a capacitor 18, resistors 19 and 20 and a transistor 21 is removed from the circuit shown in FIG. 6 and a capacitor 31 is connected in parallel to the resistor 10.

FIG. 10 is a timing chart for explaining the operation, in which (a) shows changes in the gate voltage of IGBT 1, (b) shows the changes in the collector to emitter voltage, and (c) shows the changes in the collector current of IGBT 1. In this chart, the continuous lines denote the condition when no abnormality exists in load 3 and the short dashes lines denote the condition when the load 3 is in a shortcircuit state.

In this embodiment, the transistor 14 is in an ON state at time t.sub.0 and when the driving signal V.sub.S turns positive, the driving voltage V.sub.8 is instantaneously equal to the driving signal V.sub.S. At the moment, if the load is in a shortcircuit condition, the collector current I.sub.C ' increases rapidly but the collector to emitter voltage V.sub.CE ' does not decrease, and the transistor 14 holds an ON state. While the gate voltage V.sub.GE ' drops as the decrease of the charge current for capacitor 31, and at t.sub.4 the gate voltage V.sub.GE ' is equal to the normal value so that the collector current I.sub.C ' is decreased.

When the load 3 is in a normal state, since the collector to emitter voltage V.sub.CE lowers at time t.sub.1 as a result of turning on the IGBT 1, the gate voltage V.sub.GE lowers slightly and returns to the normal voltage soon. At this time, the collector to emitter voltage V.sub.CE becomes low, which denotes a completely saturated mode. This makes it possible to operate with minimum loss.

In the above embodiment, the voltage adjusting circuit composed of a resistor 12, light emitting diode 13a of the photocoupler and a transistor 14 is connected to the bases of complementarily connected transistors 6 and 7. However, when the power loss is a minor problem, the voltage adjusting circuit may be connected to the common emitter point of transistors 6 and 7.

Moreover, the technique to lower the gate voltage when the collector to emitter voltage exceeds the predetermined value is applicable to overcurrent protection of general FET.

FIG. 11 is a circuit diagram showing another embodiment of the invention. According to FIG. 11, the photocoupler 13 shown in FIG. 6 is removed and a current detector 32 is provided between the emitter of the IGBT 1 and the negative electrode of the power source 2. The output of the current detector 32 is input to the latch circuit 23 through a level detector 33.

In this circuit, the accidental collector current is detected directly by the current detector 32 and when the collector current exceeds the predetermined value, the collector to emitter voltage is adjusted by the same operation as described above.

FIG. 12 is a circuit diagram of an embodiment of the present invention. According to FIG. 12, the voltage of the power source 4 is applied to the gate of the IGBT 1 through the complementarily connected transistors 6 and 7 to whose common base connection point the driving signal V.sub.S is applied. To the base common connection point as mentioned above, the collector of the NPN transistor 14 is connected, the emitter of the transistor 44 is connected to the negative electrode of the power source 4 through a resistor 43, and the base of transistor 44 is connected to the collector of the IGBT 1 through a resistor 41. A Zener diode 45 and a resistor 42 are connected in parallel across the base of the transistor 44 and the negative electrode of the power source 4.

The operation of this circuit is as follows:

Resistors 41 and 42 form a bleeder which divides the collector to emitter voltage V.sub.CE as a result of which at both ends of the resistor 42, a voltage which is proportional to the V.sub.CE appears. Since the transistor 44 and the resistor 43 compose an emitter-follower, the collector current of transistor 44 is proportional to the voltage drop at the resistor 42.

When the transistor 44 is in an OFF state, the driving signal V.sub.S is power amplified by the transistors 6 and 7 and applied to the gate of the IGBT 1 as the gate voltage V.sub.GE. As to the conditions for OFF state of transistor 44, it is necessary that the voltage drop between emitter and the base is larger than that of resistor 42. Therefore the collector to emitter voltage of the IGBT 1 is not more than 1 V which generates the voltage drop at the resistor 42 exceeding the voltage drop across the emitter and the base of the transistor 44. If the voltage V.sub.CE exceeds this voltage V1 as shown in FIG. 13, transistor 44 begins to send the collector current, which is in proportion to the voltage drop of the resistor 12 as described above. Thus this collector current generates the voltage drop at the resistor 40, and consequently the driving signal Vs lowers and the gate voltage V.sub.GE also drops until the collector voltage V.sub.CE lowers to the voltage V1 which cannot send the collector current through the emitter-follower. When the collector voltage V.sub.CE further rises and exceeds the predetermined voltage V2, the Zener diode 15 prevents the voltage from rising. As a result, the voltage V.sub.GE is maintained at a predetermined minimum value.

FIG. 14 is a graph illustrating the operation by the control of the gate voltage V.sub.GE and FIG. 14 (a) illustrates a line A for I.sub.c =20 A which is the limit line for preventing latch-up phenomena. A line shown in FIG. 14(b) shows the plotted points where line A and the V.sub.GE curves are crossed in FIG. 14(a). A line C in FIG. 14(b) is an approximate line of curve B. The maximum gate voltage V.sub.GE can be determined by selecting the characteristics of the emitter-follower transistor 44 and resistances of resistors 41 and 42 which divide V.sub.CE and the minimum value of gate voltage V.sub.GE can be determined by selecting the characteristics of the Zener diode 15. Thus the current flowing through the IGBT can always be controlled within the maximum permissible current by controlling the gate voltage V.sub.GE of IGBT within a predetermined range.

FIG. 15 to FIG. 19 are circuit diagrams of other embodiments according to the present invention.

In FIG. 15, a resistor 46 is added to the Zener diode 45 in series. In this embodiment, the gate voltage V.sub.GE when the collector to emitter voltage of the IGBT rises is shown as a dashed line in FIG. 14, because some voltage drop is generated at the resistor 16. This makes it possible to approximate the constant current characteristics more precisely.

FIG. 16 is a circuit diagram of another embodiment of the invention, in which Zener diodes 47 and 48 are provided at collector and base of the emitter-follower transistor 44. However, the Zener diode across the base and emitter of the transistor 44 and the resistor at the emitter are removed. In this circuit, two Zener diodes 17 and 18 determine the collector voltages V1 and V2 which vary the gate voltage V.sub.GE thus the gate voltage V.sub.GE changes its value alternately between V1 and V2, which is sufficient in practice.

FIG. 17 shows a circuit diagram of another embodiment, in which a resistor 49 is substituted for the Zener diode and the Zener diode in FIG. 16 is removed. The fundamental operation of this embodiment is similar to that of the circuit shown in FIG. 16.

FIG. 18 shows the control circuit which supplies the driving signal to the circuit shown in FIG. 17.

In this circuit, the control signal V.sub.G is input to an AND circuit 51 and its output signal is applied to the resistor 40 as the driving signal V.sub.s. A light emitting diode 52a of a photocoupler is connected between the collector of the transistor 44 and the bases of transistors 6 and 7. The phototransistor 52b of the photocoupler is connected to the positive power supply through a resistor 53, and the common connection point is connected to a SET terminal of a time delay circuit 54. The current flowing through the transistor 44 is detected by the light emitting diode 52a, and the phototransistor 52b sends photocurrents, and thus the logic level signal is input to the SET terminal of the time delay circuit. The output of this time delay circuit 54 is input to a latch circuit 55. When the control signal V.sub.G rises, the time delay circuit is reset. At this time, if the collector current detected by the photocoupler 52 continues to flow longer than the predetermined time interval set by the time delay circuit 54, which means an accident in which the collector voltage V.sub.CE of the IGBT does not drop because of an overcurrent, accident information is held by the latch circuit 55. Therefore the output of the AND circuit 51 is off and the IGBT 1 is turned off to protect it from the accident.

FIG. 19 shows a circuit diagram of another embodiment, in which the photocoupler 52 shown in FIG. 18 is removed and a current detector 56 is provided between the emitter of the IGBT 1 and the negative electrode of the power source 4. The output of the current detector 56 is input to the latch circuit 55 through a level detector 57.

According to this circuit, the collector to emitter voltage of the IGBT 1 is adjusted by the same operation as described by referring to FIG. 18, based on the direct collector current detection.

In the above embodiments, only one IGBT element is used. However, in the practical use, four or six IGBTs each of which has reversely connected free wheeling diode between collector and emitter are used to form a bridge.

Moreover, in the above embodiment, the adjustment point of the voltage adjustment circuit including the emitter-follower transistor is connected to input side of the amplifying transistor for gate of IGBT, but it may be connected to the output side of the amplifying transistor.