US 4,719,628 AGrant
Method and Apparatus for Decoding Error Correction Code
Issue Date:1988-01-12
•6 Claims
•3 Drawing Sheets
Abstract
In a method for decoding an error correction code in which a first correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) is encoded for every k.sub.1 information symbols arranged in each column and a second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) are encoded for every k.sub.2 information symbols arranged in each row of a two dimensional arrangement of (k.sub.1 .times.k.sub.2), a first pointer formed by decoding the first error correction code is stored in a memory having n.sub.2 bits, a second pointer formed by decoding the second error correction code is stored in a memory having k.sub.2 bits, reliability of the information symbols is evaluated on the basis of status of the first and second pointers when the information symbols is outputted. In the case when the second error correction code is decoded, an erasure correction may be made with respect to each of the code series of the second error correction code by employing the first pointer and a part of the calculation for obtaining an error value in this erasure correction may be carried out only once with respect to each of the code series of the second error correction code.
Metadata
Assignee
- Sony Corporation
Inventors
- Shinya Ozaki
- Kentaro Odaka
- Tadashi Fukumi
Application Information
Application Number:US 7677839
Filing Date:1985-08-19
Priority Date:1983-12-20
Art Unit:236
Classifications
IPC:
G06F 1110
Field of Search:
37150;37;39;40
Patent Drawings (3 sheets)
Description
Technical Field
This invention relates to a method and an apparatus for decoding error correction code.
Background Art
Product codes are well known such that information symbols are arranged in two-dimensional form; error correction codes are encoded for each row and column on the two-dimensional arrangement so that each information symbol is included in two error correction code series. In decoding the product code, an error correction code is decoded for each column, and an error correction code can be decoded for each row by employing the decoded information. The decoded information is called a pointer.
In the conventional method, since each information symbol is associated with a pointer, it is required that the total number of pointers is at least equal to the number of the information symbols.
Further, in the case where erasure correction is made by employing the pointers, since the pointers are read out from a pointer memory and the error values are calculated for every row, there exists a problem in that the number of processing steps such as memory accesses, calculations and so on inevitably increases.
On the other hand, in the case where complicated codes such as BCH codes are employed as error correction codes, since the operations for obtaining error values become inevitably complicated, there exists a problem in that a great number of program steps are required in the case where the calculations are implemented by hardware.
Disclosure of the Invention
An object of this invention is to provide a method and an apparatus for decoding error correction codes which enable one to reduce the number of pointers required in decoding as well as the memory space required for pointers and to reduce the number needed for times of reading and writing the pointers.
Another object of this invention is to provide a method and an apparatus for decoding error correction codes which enable one to markedly reduce the number of processing steps in dependence upon the fact that the pointers with respect to each row are the same.
Still another object of this invention is to provide an apparatus for decoding error correction codes which enables one to reduce the number of calculating steps in an erasure correction.
A still further object of this invention is to provide a method for decoding error correction codes which can obtain error values in decoding in dependence upon a simple construction and using a small number of processing steps.
To achieve the above mentioned technical task, the present invention provides a method of decoding error correction code in which first error correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) are encoded for every k.sub.1 information symbols in each column of two-dimensional arrangement (k.sub.1 .times.k.sub.2) and second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) are encoded for every k.sub.2 information symbols in each row, the method for decoding error correction code comprises the steps of storing first pointers formed by decoding the first error correction code in a memory having n.sub.2 bits, storing second pointers formed by decoding the second error correction code in at least a memory having k.sub.1 bits, and evaluating the reliability on the basis of the status of the first and second pointers in outputting the information symbols.
Further, in the present invention, a method of decoding error correction codes comprises the steps of storing first pointers formed by decoding the first error correction code in a memory having n.sub.2 bits, implementing erasure correction with respect to each code series of the second error correction code by employing the first pointer and implementing a part of calculations for obtaining error values in the erasure correction only once with respect to each code series of the second error correction code in decoding the second error correction code.
Further, in the present invention, paying attention to the fact that in linear non-dualistic code having a root of 1, one of the syndromes is an addition of (mod. 2) of a received symbol series, an apparatus for decoding error correction code stores a syndrome in a syndrome register and forms an error value with respect to a single symbol by subtracting other error values from a value stored in the syndrome register in correcting a plurality of erroneous symbols.
Brief Description of the Drawings
FIG. 1 is a schematic block diagram showing an encoder according to an embodiment of the present invention.
FIG. 2 is a schematic diagram for assistance in explaining the operation of an embodiment of the present invention.
FIG. 3 is a schematic block diagram showing a decoder according to one embodiment of this invention.
FIG. 4 is a block diagram showing an embodiment of this invention.
FIG. 5 is a block diagram showing an essential portion of an embodiment of this invention.
FIG. 6 is a block diagram showing an construction of an embodiment for use with this invention.
FIG. 7 is a block diagram for assistance in explaining a processing circuit of FIG. 6.
Best Mode for Carrying Out the Invention
An embodiment of the present invention will be described, referring to the drawings. FIG. 1 shows a structure of an encoder for product code. The reference numeral 1 denotes an input terminal, the reference numeral 2 denotes a C.sub.2 (the second error correction code) parity generator. The input data from the input terminal 1 are supplied to the C.sub.2 parity generator 2 and one input terminal of a selector 3, and the C.sub.2 parity data formed by the C.sub.2 parity generator 2 are supplied to the other input terminal of the selector 3. The selector 3 repeats k.sub.1 times the operations for selecting (n.sub.2 -k.sub.2) parity data after k.sub.2 information symbols are selected. During this operation, the information symbols and the parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller 5.
The data read out from the RAM 4 are supplied to a C.sub.1 (the first error correction code) parity generator 6 and the one input terminal of a selector 7, and the C.sub.1 parity data formed by the C.sub.1 parity generator 6 are supplied to the other input terminal of the selector 7. The selector 7 selects ((n.sub.1 -k.sub.1).times.k.sub.2) C.sub.1 parity data after having selected (k.sub.1 .times.n.sub.2) symbols including the C.sub.2 parity data. The digital data derived from an output terminal 8 of the selector 7 are transmitted or recorded on a magnetic tape (not shown) with a magnetic head, for instance. In this case, it is possible to write again the encoded output once into the RAM 4 and to read it out in a different sequence for recording.
FIG. 2 shows a configuration of code formed by the encoder as described above. The information symbols are arranged in two dimensions of (k.sub.1 .times.k.sub.2). The k.sub.2 information symbols in every lateral direction, that is, in every row of the two-dimensional arrangement, are subjected to encoding process for the C.sub.2 code. The k.sub.1 information symbols in every vertical direction, that is, in every column, are subjected to encoding process for the C.sub.1 code. The C.sub.2 parity data are also encoded into the C.sub.1 code. The C.sub.1 code is, for instance, (n.sub.1, k.sub.1) Reed-Solomon code, by which it is possible to correct errors of up to (n.sub.1 -k.sub.1)/2 symbols.
The general method of decoding the Reed-Solomon code will be described.
The Hamming distance of the (n, k) Reed-Solomon code (n denotes the code length and k denotes the number of information symbols) on a Galois Field GF(2.sup.m) can be expressed as (d=n-k+1) and the generator polynominal can be expressed as ##EQU1## If the received words are (r.sub.0, r.sub.1, r.sub.2, . . . , r.sub.n-1), the syndrome can be obtained by operating the following expression: ##EQU2##
An error location polynominal .sigma.(z) and an error evaluation polynominal .omega.(z) are obtained by employing the syndrome S.sub.j. As to this method, Euclid's mutual division method, Varlay-Camp's method, Peterson's method and so on have been proposed.
By solving .sigma.(z)=0, the error location X.sub.i can be obtained. For this purpose, Chien search is employed.
Then, the error value Y.sub.i can be obtained on the basis of the error location X.sub.i and the error evaluation polynominal .omega.(z).
The above calculations in the decoding steps are explained with the error location as X.sub.i (i=1, 2, . . . , e: e denotes the number of errors), and the error value as Y.sub.i. Since the Reed-Solomon code is a linear code, the syndrome can be expressed as: ##EQU3## if the syndrome is expressed by a polynominal as: ##EQU4## a following expression is obtained: ##EQU5## If the error location polynominal and the error evaluation polynominal are defined as: ##EQU6## then .omega.(z) can be expressed as ##EQU7## The error value Y.sub.i can be obtained by substituting X.sub.i.sup.-1 into z and by transforming the expression as follows: ##EQU8##
As an example, (32, 24) Reed-solomon code having roots of .alpha..sup.0 to .alpha..sup.7 will be explained. Since this code is (d=9), it is possible to correct errors of up to 4 symbols. If the error locations of the 4 symbols are X.sub.1 to X.sub.4 and the error values are Y.sub.1 to Y.sub.4, the syndrome is obtained from following expression. ##EQU9## Namely, S.sub.0 is as follows among 4 syndromes: ##EQU10## Once the error values Y.sub.1, Y.sub.2, Y.sub.3 can be obtained, the remaining error value Y.sub.4 is obtained as follows without implementing complicated calculations:
In codes on GF(2.sup.m), a subtraction is equivalent to an addition of (mod. 2).
FIG. 3 shows a configuration of the encoder of this embodiment. In FIG. 3, the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C.sub.1 decoder 12. In the C.sub.1 decoder 12, the decoding of the C.sub.1 code is performed. All errors of up to (n.sub.1 -k.sub.1)/2 symbols are corrected in the C.sub.1 decoding. In the case, however, where the number of errors in a single series of C.sub.1 code is more than or equal to a (.ltoreq.(n.sub.1 -k.sub.1)/2), the C.sub.1 pointers of this series is set to "1", the other pointers are set to "0". In FIGS. 2 and 3, the reference numeral 13 denotes a pointer memory for storing the pointers of the C.sub.1 code, which has n.sub.2 bits. The output of the C.sub.1 decoder 12 is stored temporarily in a RAM 14 in sequence under the control of an address controller 15.
The output read out from the RAM 14 are supplied to a C.sub.2 decoder 16 to be subjected to the decoding of the C.sub.2 code. The C.sub.2 decoder 16 is supplied with the C.sub.1 pointer from the pointer memory 13. Since the C.sub.1 pointer is common to the all of K.sub.1 series of C.sub.2 code, it is possible to decode the C.sub.2 code in accordance with the same procedure in each series. The C.sub.2 decoder 16 corrects errors of up to (n.sub.2 -k.sub.2)/2 symbols and generate three kinds of pointers in the C.sub.2 code which is stored in a pointer memory 17.
When error correction is performed by the C.sub.2 decoder 16, the C.sub.2 pointers with respect to the series is set to "0". When error correction can not be performed by the C.sub.2 decoder 16 and the C.sub.1 pointers are copied because of its high reliability, the C.sub.2 pointers are set to "1". When error correction can not be performed by the C.sub.2 decoder 16 and all symbols are determined to be erroneous symbols because of low reliability of the C.sub.1 pointer, the C.sub.2 pointers are set to "2". Therefore, the C.sub.2 pointers have 2 bits and the pointer memory 17 has 2K.sub.1 bits.
These pointer memories 13 and 17 are disposed separately from the RAM 14 for storing information symbols and parity data in decoding or disposed in common with the RAM 14 by using a part of memory regions of the RAM 14.
Without being limited to 1 bit, the C.sub.1 pointer may have 2 bits or more. Further, it is possible to implement the error correction code processing of C.sub.2 code for the C.sub.1 parity, while providing a C.sub.2 pointer memory of (2n.sub.1) bits.
The output data of the C.sub.2 decoder 16 ae supplied to an interpolation circuit 18 to conceal error in the symbols which have not been corrected. The interpolation circuit 18 performs the mean value interpolation, for instance. The interpolation circuit 18 is controlled by a control circuit 19 which is supplied with the C.sub.1 pointers and the C.sub.2 pointers from the pointer memories 13 and 17. The output data of the interpolation circuit 18 are derived at an output terminal 20. The control circuit 19 determines by every information symbol whether interpolation is necessary on the basis of the c.sub.1 pointer and c.sub.2 pointer. In FIG. 2, There exist all the combinations of C.sub.1 pointers designated as 13' and C.sub.2 pointers designated as 17'.
When the C.sub.2 pointer is "0" irrespective of the fact that the C.sub.1 pointer is "0" or "1", the interpolation circuit 18 does not work. When the C.sub.2 pointer is "1" and the C.sub.1 pointer is "0", since it is determined that the information symbol has no error, no interpolation is done. When the C.sub.2 pointer is "1" and the C.sub.1 pointer is "1", since it is determined that it is erroneous symbol, the interpolation operation is performed. Further when the C.sub.2 pointer is "2" irrespective of the fact that the C.sub.1 pointer is "0" or "1", since it is determined that it is erroneous symbol, the interpolation operation is performed.
The reliability of the C.sub.1 pointers is evaluated by the C.sub.2 decoder. For instance, provided that up to 2 symbol errors can be corrected by the C.sub.2 code, if correction by the C.sub.2 code can not be performed in spite of the fact that only one C.sub.1 pointer is "1", it is determined that the reliability of the C.sub.1 pointer is low because the above is abnormal. Even if errors are not corrected by the C.sub.2 code, it is possible to eliminate the necessity of interpolation by providing three kinds (0, 1, 2) of the C.sub.2 pointers and by discriminating the copies of C.sub.1 pointers from all errors.
In the above mentioned C.sub.2 decoder 16, when the C.sub.1 pointers are copied, the erasure correction is made where the number of the C.sub.1 pointers is less than or equal to (n.sub.2 -k.sub.2) and when the erasure correction is made, the C.sub.2 pointer is set to "0".
As described above, the decoding of the Reed-Solomon code is performed by calculation of the error location polynominal .sigma.(z) and the error evaluation polynominal .omega.(z) in every row and by employing syndrome obtained by n.sub.2 symbols in each row. In the case of erasure correction, since the locations where the C.sub.1 pointers are "1" are determined as the error locations, it is possible to obtain the error value Y.sub.i from the error location X.sub.i and the error evaluation polynominal .omega.(z). That is to say, by substituting X.sub.i.sup.-1 in place of z, Y.sub.i can be obtained as follows as in expression (8): ##EQU11## (where i=1, 2, 3, . . . s; s denotes the number of symbols) In the above expression, the denominator term can be determined by only the error locations. For instance, provided that the error locations shown by the C.sub.1 pointer are X.sub.1, X.sub.2, X.sub.3, the terms of denominator of the expressions for obtaining the error values Y.sub.1, Y.sub.2, Y.sub.3 are:
Here, the pointers stored in the pointer memory 13 are the same in all of the K.sub.1 series of the C.sub.2 code. Therefore, it is sufficient to implement the calculation of the denomimator term in the above expression to obtain error value only once with respect to the k.sub.i series.
FIG. 4 shows the configuration of an error correcting decoder for use with the above mentioned C.sub.1 decoder and C.sub.2 decoder. The received data are supplied to an input terminal designated by the reference numeral 21 and supplied to a delay circuit 22 and a syndrome generating circuit 23. The syndromes formed by the syndrome generating circuit 23 are supplied to an error location and error value calculating circuit 24. The error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. 2). The received data from the delay circuit 22 and the error corrected data from the exclusive OR gate 25 are supplied to a selector 26. The selector 26 is controlled by the error location data. At the error locations, the output of the exclusive OR gate 25 is selected by the selector 26 to be derived at an output terminal 27 in place of the received data.
In the case of an audio PCM signal recording and reproducing apparatus, the reproduced data are once written in a RAM. By use of the data read out from the RAM, the syndrome is generated and on the basis of which the error locations and the error values are calculated. FIG. 5 shows a part of the error location and error value calculating circuit 24. In FIG. 5, the reference numeral 28 denotes a data bus through which data and syndrome and so on are transferred.
In FIG. 5, the reference numeral 29 denotes a syndrome register in which the syndrome S.sub.0 is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31. The syndrome S.sub.0 has m bits in the case of Reed-Solomon code on GF(2.sup.m). The syndrome S.sub.0 from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32.
When the syndrome S.sub.0 is stored in the syndrome register 29, the obtained error values Y.sub.1, Y.sub.2, Y.sub.3 are supplied to the exclusive OR gate 31 in sequence from the data bus 28 through the bus buffer 30. Therefore, the output of the exclusive OR gate 31 is (S.sub.0 .sym.Y.sub.1), (S.sub.0 .sym.Y.sub.1 .sym.Y.sub.2) and (S.sub.0 .sym.Y.sub.1 .sym.Y.sub.2 .sym.Y.sub.3 =Y.sub.4). The error value Y.sub.4 is left in the syndrome register 29. The error value Y.sub.4 is outputted to the data bus 28 through the bus buffer 32 to be employed for error correction.
FIG. 6 shows another example of hardware for decoding in an erasure correction. A main RAM 35 is connected to the data bus 28 through a writing register 33 and a reading register 34. The syndrome register 29, a working RAM 36 and an operation logic circuit 37 are provided to the data bus 28.
The erasure correction by Reed-Solomon code can be concluded by solving the following n-order linear simultaneous equations in the same way as in expression (2): ##EQU12## where, .nu.=0 to d-2
n: Number of erasure
X.sub.k : Location of kth
S.sub..nu. : Syndrome
Y.sub.k : Magnitude of error in the erasure of kth
d: Minimum distance of code
Here, n, X.sub.k, S.sub..nu., are known, Y.sub.k is unknown.
To solve the above equation, the following method has been conventionally adopted: if ##EQU13##
Y.sub.i can be obtained as in expression (8) as follows: ##EQU14##
In this method, however, if the number of actual calculation steps is counted when d=9 and n=8, for instance.
(i) Expansion of .LAMBDA.(z)
(ii) Previous calculations for obtaining the denominator of ##EQU15##
(iii) Calculations for obtaining .omega.(z)=S(z).LAMBDA.(z), mod. Z.sup.8
(iv) Calculations for obtaining .omega.(X.sub.i.sup.-1)
(v) Calculations for obtaining Y.sub.i
When these calculations need each one step, the number of steps is 408 in total.
In the circuit shown in FIG. 6, the roots of expression (9) are calculated by: ##EQU16## where .LAMBDA..sub.nij : Coefficient of Z.sup.j of ##EQU17## 1: Any integer more than or equal to 0 which satisfies l.ltoreq.d-n-1
That is to say, in order to implement erasure correction, l=0, i=n are substituted into the expression (11) as follows: ##EQU18## By this calculation, Y.sub.n is obtained and Y.sub.n X.sub.n.sup..nu. is added to each syndrome S as follows:
where .nu.=0 to n-2
Since the data at the location X.sub.n are correct, the syndrome includes (n-1) erasures. Therefore, by reducing n by 1, Y.sub.n-1 can be obtained: ##EQU19## By this calculation, Y.sub.n-1 is obtained and Y.sub.n-1 X.sub.n-1.sup..nu. is added to each syndrome S as follows:
where .nu.=0 to n-3
By repeating the above, the last remaining erasure Y.sub.1 can be obtained as
Y.sub.1 =S.sub.0
As explained above, an erasure correction can be implemented. In this case, the actual number of operation steps is counted in the same way as in the conventional method, provided that d=9 and n=8.
(i) Expansion of .LAMBDA..sub.nnj
(ii) Previous calculations for obtaining the denominator of ##EQU20## where it is sufficient to obtain only II.sub.3 to II.sub.8, since II.sub.2 =X.sub.1 +Y.sub.2 =.LAMBDA..sub.331.
(iii) Calculations for obtaining the numerator of Y.sub.n
(iv) Calculations for obtaining Y.sub.n, since Y.sub.1 =S.sub.0
(v) S.sub..nu. .rarw.S.sub..nu. +Y.sub.n X.sub.n.sup..nu.
The number of the above calculations steps as 202 in total.
Therefore, in the case of expression (11), it is possible to reduce the number of calculation steps to 50% of the conventional case in the expression (10).
Further, in the case where the above mentioned correction code is a product code, provided that 30 symbols are arranged in the vertical direction, 128 symbols are arranged in the lateral direction, the C.sub.1 code is formed to the vertical direction, and the C.sub.2 code is formed to the lateral direction, the erasure corresponds to the location of the C.sub.1 pointers, and the location X.sub.k (k=1 to n) is the same in all the C.sub.2 code series. This means that it is possible to previously calculate .LAMBDA..sub.nnj and ##EQU21## in expression (11)' without calculating these terms every the C.sub.2 decoding. That is to say, in this example, the above calculation is implemented only once while the C.sub.2 decoding is performed 30 times.
Therefore, in the number of the above calculation steps, since the number of the calculations of (i) and (ii) is only once every 30 times of C.sub.2 decoding, provided that the number of steps of (i) and (ii) is 90/30=3, the total number of steps is 115. compared with that in the conventional method, where the number of steps in (i) and (ii) is 224/3=74.7 and the total number of steps is 191.5, it is possible to reduce the number of steps by about 40%.
Accordingly, the method as above described has advantages such that it is possible to markedly reduce the number of calculation steps, processing time, hardware load for processing and so on as compared with the conventional method.
Additionally, although the above calculations are performed by employing the operation logic 37, in the case where, for example, S.sub..nu. .rarw.S.sub..nu. +X.sub.i.sup..nu. Y.sub.i is obtained, a concept as shown in FIG. 7 is adopted. In FIG. 7, the reference numerals 38, 39, 40 denote registers, the reference numeral 41 denotes an adder, the reference numeral 42 denotes a multiplier, the reference numeral 43 denotes a selector, which are comprise the operation logic 37. In this circuit,
[1] S.sub.0 is set to the register 39 38, Y.sub.i is set to the register, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S.sub.0 +Y.sub.i is outputted from the adder 41 to the data bus 28.
[2] The content of the multiplier 42, X.sub.i Y.sub.i is set (feedbacked) to the register 39 through the selector 43, and S.sub.1 is set to the register 38 from the data bus 28. Therefore, S.sub.1 +X.sub.i Y.sub.i is outputted from the adder 41 to the data bus 28.
[3] Further, the content of the multiplier 42, X.sub.i.sup.2 Y.sub.i is feedbacked to the register 39 through the selector 43, and S.sub.2 is set to the register 38 from the data bus 28. Therefore, S.sub.2 +X.sub.i.sup.2 Y.sub.i is outputted from the adder 41 to the data bus 28.
[4] By repeating the above steps, S.sub.3 +X.sub.i.sup.3 Y.sub.i, S.sub.4 +X.sub.i.sup.4 Y.sub.i, . . . are obtained sequentially, and supplied to the syndrome register 29 through the data bus 28 so as to rewrite each value. The calculation are implemented as described above.
In the above explanation, although all of X.sub.1 to X.sub.n are assumed as erasures, in the case where X.sub.1 to X.sub.n-1 are erasures and X.sub.n is an error, it is possible to correct the symbols. In this case, the number of unknown quantity are (n+1) of Y.sub.1 to Y.sub.n and X.sub.n. X.sub.n can be obtained by using the above .LAMBDA..sub.nnj as follows: ##EQU22## Therefore, the unknown quantity are Y.sub.1 to Y.sub.n, and thereafter, these unknown quantity can be obtained in the same way as in the erasure correction.
For instance, in the case where d=9 (6 erasures+1 error) in product code,
[1] Check locations of the erasures X.sub.1, X.sub.2, . . . , X.sub.6.
[2] Obtain and store .LAMBDA..sub.nnj, here 21 symbols in total of
[3] Obtain and store 5 symbols in total of ##EQU23## (n=2 to 6). The above processings are made once for each 30 times.
[4] Calculate syndromes S.sub.0 to S.sub.7.
[5] Obtain X.sub.7 by an expression as follows: ##EQU24##
[6] Obtain Y.sub.7 by the following expression and feedback the syndrome Y.sub.7 X.sub.7 : ##EQU25## Thereafter, Y.sub.6 to Y.sub.1 (=S.sub.0) are sequentially obtained.
Although a case where expression (11)' is used is shown in this example, the operation is the same if 1.noteq.0.
As described above, it is possible to implement the correction of errors including erasures and one error. In this case, the number of calculation steps can be reduced as in the erasure correction described above.
The proof of the above expressions (11) and (12) will be described hereinafter:
[Lemma] If ##EQU26## the following expression is clearly obtained: ##EQU27##
[Theorem 1] The n-order linear simultaneous equations: ##EQU28## (.nu.=0 to n-1: Y.sub.i is unknown quantity) has the roots as: ##EQU29## Therefore, it is understood from Theorem 1 that errors can be corrected in the erasure correction by use of any of S.sub.1 to S.sub.n, S.sub.2 to S.sub.n+1, . . . , S.sub.d-1-n to S.sub.d-2 among the series of S.sub.0 to S.sub.n-1. That is, n continuous syndromes are necessary for n erasures correction, the remaining syndromes are usable for checking, so that n.ltoreq.d-1.
Further, to obtain X.sub.n from the theorem 2, total n+1 syndromes of S.sub.1 to S.sub.n+1 are necessary, so that n.ltoreq.d-2. In this case, the number of erasures is n-1.ltoreq.d-3. The remaining syndromes can be used for checking as in the above case.
In the conventional method, the pointer areas are required for the total number of data (n.sub.1, n.sub.2) corrsponding to the error correction code. According to the present invention, however it is possible to reduce the number of pointers to (n.sub.2 +2n.sub.1) and further to reduce the capacity of the memory required in decoding. Further, according to the present invention, it is possible to reduce the number of steps for writing or reading the pointers. Further, according to the present invention, in the case where the erasure correction in the C.sub.2 decoding is implemented by the use of pointers formed by the C.sub.1 decoding, since the pattern of the pointers with respect to each series of C.sub.2 code is common and a part of the operations to obtain error value become common, it is possible to implement the operation only once. Therefore it is possible to markedly reduce the number of processing steps in decoding and to realize a high-speed in decoding operation.
Furthermore, the present invention makes it unnecessary to obtain the whole error values in accordance with complicated error evaluation polynomial in obtaining a plurality of error values, it is possible to obtain one of the error values by a simple construction and to reduce the number of the processing steps.
Moreover, according to the present invention, it is possible to markedly reduce the number of calculation steps in erasure correction.
Claims
What is claimed is:
1. A method for decoding error correction code in which a first error correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) is encoded for every k.sub.1 information symbols arranged in each column and a second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) are encoded for every k.sub.2 information symbols arranged in each row of a two dimensional arrangement of (k.sub.1 .times.k.sub.2), the method comprising the steps of: storing a first pointer formed by decoding said first error correction code in a memory having n.sub.2 bits; storing a second pointer formed by decoding said second error correction code in a memory having k.sub.2 bits; and manifesting an indication of the reliability of said information symbols in response to the status of said first and second pointers when outputting said information symbols.
2. An apparatus for decoding error correction code in which a first error correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) is encoded for every k.sub.1 information symbols arranged in each column and a second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) are encoded for every k.sub.2 information symbols arranged in each row of a two dimensional arrangement of (k.sub.1 .times.k.sub.2), the apparatus comprising: memory means for storing a first pointer formed by decoding said first error correction code in a memory having n.sub.2 bits; memory means for storing a second pointer formed by decoding said second error correction code in a memory having k.sub.2 bits; and means for manifesting an indication of the reliability of said information symbols on the basis of status of said first and second pointers when outputting said information symbols.
3. A method for decoding error correction code in which a first error correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) is encoded for every k.sub.1 information symbols arranged in each column and a second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) and encoded for every k.sub.2 information symbols arranged in each row of a two dimentional arrangement of (k.sub.1 .times.k.sub.2), the method comprising the steps of: storing a first pointer formed by decoding said first error correction code in a memory having n.sub.2 bits; and decoding said second error correction code by implementing an erasure correction for each code series of said second error correction code by employing said first pointer and by implementing a calculation for obtaining an error value only once for each code series of said second error correction code in said erasure error correction.
4. An apparatus for decoding error correction code in which a first error correction code of (n.sub.1, k.sub.1) (where n.sub.1 denotes the code length) is encoded for every k.sub.1 information symbols arranged in each column and a second error correction code of (n.sub.2, k.sub.2) (where n.sub.2 denotes the code length) are encoded for every k.sub.2 information symbols arranged in each row of a two dimentional arrangement of (k.sub.1 .times.k.sub.2), the apparatus comprising: means for storing a first pointer formed by decoding said first error correction code in a memory having n.sub.2 bits; and means for decoding said second error correction code by implementing an erasure correction for each code series of said second error correction code by employing said first pointer and by implementing a calculation for obtaining an error value only once for each code series of said second error correction code in said erasure error correction.
5. An apparatus for decoding a non-dualistic error correction code in which one of a plurality of syndromes is a result of an addition of a series of received symbols in (mod. 2) and by which errors of a plurality of symbols in said series of received symbols, can be corrected, the apparatus comprising: a syndrome register for storing said syndromes; wherein an error value with respect to a symbol is formed by substracting an error value from a value stored in said syndrome register in correcting a plurality of erroneous symbols.
6. A method for decoding and correcting Reed=Solomon code comprising the steps of solving the expression ##EQU30## where, .nu.=0to d-2 n: Number of erasure X.sub.k : Location of kth element S.nu.: Syndrome Y.sub.k : Magnitude of error in the erasure of kth element d: Minimum distance of code to obtain the roots ##EQU31## where .LAMBDA..sub.nij : Coefficient of Z.sup.j of ##EQU32## 1: Any integer more than or equal to 0 which satisfies 1.ltoreq.d-n-1 and making erasure correction of errors encoded in said Reed.dbd.Solomon code in accordance with said roots.
Patent Citations (7)
Non-Patent Literature (1)
- U. Olderdissen, "Fast Double Error Correction", IBM TDM, vol. 25, No. 5, 10/1982, pp. 2343-2346.