Dejitterizer Method and Apparatus

1. Field of the Invention

The present invention is related to digital transmission of voice and data. More particularly, the invention removes jitter commonly found in repeater-transmitted digital signals.

2. Discussion of Related Art

Regenerative repeaters that provide some form of correction for high frequency timing errors, commonly referred to as jitter, are known. U.S. Pat. No. 4,054,747 describes means for correcting phase errors in transmitted data. Errors exceeding one unit interval produces a reset. U.S. Pat. No. 4,270,183 describes means for removing jitter from digital signals played back from a magnetic tape recording, in which many bits of data are offset by phase errors as a result of jitter.

In the '183 patent, data is clocked into a multi-part cascaded FIFO buffer in response to a coincidence of a given pulse of the data clock and a pulse from a fixed-frequency local clock. Data is output in response to a coincidence between local and given clock pulses. The dejitterizer's output rate is reset in response to a half-full buffer status detected by tapping the "input ready" line of a FIFO device in the middle of the buffer. The rate at which data is output as a serial bit stream is a function of the amount of data in the buffer at a given moment, to maintain adequate "head room" in the buffer.

Dejitterizers are particularly important in transmission networks where frequent amplification is required to maintain adequate signal levels, such as T4 fiber optic systems, and in longdistance data links generally. For T1 carrier applications, where the suggested maximum jitter offset is eight bits wide*, only one 64-bit FIFO device is required. However, when only one FIFO device is used in the buffer, instead of the multiple devices disclosed in the '183 patent, the input ready signal from the buffer device cannot be used to control the FIFO buffer because it only indicates when the buffer is full. Some other means for accurately determining the "half-full" status must be provided when using a single FIFO device. Also, if an up-down counter is used to determine buffer status some means must be found to prevent a simultaneous up and down count inputs to assure an accurate count, since the signals which clock the input and the output of the FIFO buffer are effectively asynchronous.

The present invention provides a simple, reliable correction for jitter in the digital transmission of voice and data signals.

In accordance with the present invention, data from a jittered signal is clocked into a first-in/first-out (FIFO) buffer by a jittered clock pulse signal derived from the jittered signal. The data is clocked out of the FIFO buffer by a local clock pulse signal. A counter is incremented by each jittered clock pulse and decremented by pulses of the local clock pulse signal. Means for preventing coincidence of said given and local clock pulses is provided, to assure that the count is accurate. The frequency of the local clock pulse signal varies as a function of the phase relation between the local and given clock pulse signals to prevent buffer overflow.

The invention and its advantageous features will be more clearly understood when the detailed description of a preferred embodiment, given below, is considered in conjunction with the drawings.

The single feature of the drawing is a functional block diagram of the preferred embodiment.

With reference to the drawing, apparatus in accordance with the preferred embodiment of the present invention comprises a standard T-carrier signal line regenerator 10 with automatic gain control, for use on T-1 carrier transmission lines. A T1 bipolar signal from a repeated line is supplied to the regenerator 10. The regenerator 10 separates the bit stream of the transmitted data, hereinafter referred to as "data signal" and transmitted clock pulse signal hereinafter referred to as the "jittered" clock pulse signal, from the T1 signal. The data signal from regenerator 10 is then supplied to a flip-flop circuit 12, which converts the return-to-zero (RZ) data signal into a non-return-to-zero (NRZ) data signal. The NRZ signal is supplied to a 64-bit first-in/first-out (FIFO) buffer 14, and then to a gate 16 and bipolar signal conversion circuit 18 which reconverts the NRZ signal into a balanced bipolar return-to-zero (BRZ) format. The regenerator 10 can be any one of a variety of well-known integrated circuit devices suitable for use with the T1 telecommunications signal format. The transmitted data rate and, therefore, the frequency of the transmitted clock pulse signal derived by the regenerator 10 from the T1 format signal is nominally 1.544 Mhz.

A local timing pulse signal is produced by a voltage-controlled crystal-oscillator (VCXO) 20 at a frequency of approximately 6.176 Mhz, which varies with the average frequency of the jittered clock. The frequency of the timing pulse signal is divided by 4 at frequency divider 19 to provide a substantially synchronous "local" clock pulse signal which is applied to the FIFO buffer 14 through control logic 30 to clock data out of the FIFO buffer 14.

The frequency of the VCXO 20 is controlled by a phase lock loop in which the frequency of the local clock pulse signal and the frequency of the jittered clock pulse signal are each divided by 16 in two dividers 21 and then supplied to a phase shift detector 22. The time between clock pulses when used to measure jitter offset is referred to as a "unit interval". Dividing the clock pulse signal frequency by 16 allows the phase lock loop to track up to 16 unit intervals of jitter.

The phase shift detector 22 outputs a variable duty cycle pulsed error voltage signal that varies with the phase difference between the local and jittered clock pulse signals. This signal is then filtered by a 20 db per decade (6 db per octave) active low-pass filter network 24 which provides a 3 db reduction at 4.5 Hz., before it is applied to the VCXO 20. Thus, the output voltage of the filter network 24 varies with the phase error between the output signals of the frequency dividers 21 averaged over an interval determined by the time constant of the filter network 24. Accordingly, at any given moment, the output of the VCXO 20 is a function of the weighted average of the phase error between the local clock and the jittered clock over more than 16 clock pulses of the jittered clock, because of the action of filter network 24. Determining phase shift over as many as one-fourth of the number of clock cycles required to fill the buffer is advantageous in that it smoothes potentially destabilizing step-function changes in the frequency of the jittered clock while assuring adequate headroom in the buffer to accomodate a normal range of frequency fluctuations.

The local clock pulse signal supplied to the FIFO buffer is enabled by control logic 30 in response to input from a 64-bit up-down counter 32. The up-down counter 32 is controlled by two transition detectors 34, 36. The transition coincidence detector 34 increases the count of the up-down counter 32 for each pulse of the jittered clock pulse signal applied thereto from the regenerator 10, on the falling edge of the next subsequent timing pulse signal applied thereto from the VCXO 20. Transition detector 36 decreases the count of up-down counter 32 for each pulse of the enabled local clock pulse signal applied to the transition detector 36 from the frequency divider 19 through control logic 30 on the rising edge of each enabled local clock pulse. This arrangement prevents up-counts and down-counts from occurring simultaneously, thus assuring accurate buffer control.

When the power switch is activated, the dejitterizer is initialized by the reset circuit 37. The reset circuit 37 holds the FIFO buffer 14 and the up-down counter 32 in a clear state and holds the control logic 30 in its reset mode for a predetermined time to allow the power supply to reach a stable voltage. That turn-on delay period is determined by the combination of resistor R1 and capacitor C1 is charged. When the predetermined time has elapsed, the FIFO buffer 14 and up-down counter 32 are enabled. The control logic 30 remains in the reset mode, in which it blocks the application of the local clock to the FIFO buffer, until the up-down counter 32 indicates that the FIFO buffer is half-full.

During the first few seconds that the phase-lock-loop is energized the up-down counter 32 will overflow and trigger the on shot 38. The firing of the one shot 38 provides a high signal to the input of the reset circuit 37, producing a low on the output which again clears the counter 32 and the FIFO buffer 14 and resets the control logic to cause it to block the local clock pulse signal while the phase-lock-loop attains lock. One shot 38 is activated by the presence of a count of "0" (empty) or "64" (full) in the updown counter 32. Thus, when the FIFO is clocked to an empty state--as a result of the T1 input signal being lost, for example--the one-shot provides a reset to reinitialize signal processing in the dejitterizer.

After being initialized by the output of the reset circuit 37, the up-down counter 32 counts up in response to input pulses from the transition coincidence detector 34. At this time the control logic 30 will be blocking the local clock pulse signal from reaching the FIFO buffer 14 and the transition detector 36 so that there is no clocking of data out of the FIFO buffer 14 and no count down of the counter 32. When the count in the up-down counter 32 of the pulses from coincidence detector 34 reaches "32" (half full) the up-down counter 32 outputs a signal to set the control logic 30 which enables the local clock pulse signal, thereby providing the local clock pulse signal to the FIFO buffer 14 and the transition detector 36.

While the local clock pulse signal is enabled, the counter 30 counts down in response to each local clock pulse and the FIFO buffer 14 outputs NRZ data to gate 16, which is enabled by a high signal from the control logic 30 that is applied to the input of gate 16 when the local clock pulse signal is enabled. The gate 16 then outputs the data received from FIFO buffer 14 to bipolar converter circuit 18 which is continuously supplied with the local timing pulse signal. The bipolar conversion circuit 18 converts NRZ data from gate 16 to the BRZ format and outputs a dejitterized T1 signal.

This invention has been described with particular reference to a presently preferred embodiment thereof but it will be readily understood by one skilled in the art that many variations and modifications thereof are possible within the spirit and scope of the present invention. For example, to correct more extensive digital time base errors, such as those produced by tape transports, multiple dejitterizer units may be supplied with the jittered signal sequentially, using progressively more stable local clocks to further minimize residual clock frequency deviation.