Logarithmic Compression Circuit

1. Field of the Invention

The present invention relates to a logarithmic compression circuit and particularly to a logarithmic compression circuit which performs logarithmic compression using a transistor.

2. Related Background Art

Prior art logarithmic compression circuits will be described with respect to the drawings.

FIGS. 1A and 1B are schematics of prior art logarithmic compression circuits. Reference numeral 1 denotes an operational amplifier; reference numeral 2 a logarithmic compression transistor; reference numeral 3 an inverting input terminal of the amplifier; and reference numeral 4 a non-inverting input terminal of the amplifier. The signal current flowing into input terminal 3 is converted by transistor 2 into a logarithmically compressed voltage. In the circuit of FIG. 1A, the base terminal of transistor 2 is connected with the collector terminal of same. In the circuit of FIG. 1B, the base terminal of transistor 2 is connected with non-inverting input terminal 4 of the amplifier. According to the circuit construction of FIG. 1A, the occurrence of oscillations is difficult, but the logarithmic compression characteristic is deteriorated when a low signal current is input. According to the circuit construction of FIG. 1B, the logarithmic compression characteristic is good, but, disadvantageously, the circuit is likely to oscillate when a high signal current is input.

In view of the above prior art problems, an object of the present invention is to prevent deterioration of the logarithmic compression characteristic of a logarithmic compression circuit when a low signal current is input thereto and to prevent oscillation of the circuit when a high signal current is input thereto.

Another object of the present invention is to provided a logarithmic compression circuit which includes switching means provided at the base terminal of a logarithmic compression transistor.

FIGS. 1A and 1B are each a diagram of a conventional logarithmic compression circuit; FIG. 1A being a diagram of a compression circuit suitable for a high signal current input; and FIG. 1B being a diagram of a compression circuit suitable for a lower signal current input.

FIGS. 2A and 2B are first and second embodiments of a logarithmic compression circuit according to the present invention; FIG. 2A being a diagram of a circuit in which an NPN transistor is used for logarithmic compression; and FIG. 2B being a diagram of a circuit in which a PNP transistor is used for logarithmic compression.

FIG. 3 shows a third embodiment of the logarithmic compression circuit according to the present invention.

The embodiments of the present invention will now be described in more detail with respect to the drawings.

FIGS. 2A and 2B show first and second embodiments, respectively, of a logarithmic compression circuit according to the present invention. FIG. 2A is a diagram of a circuit in which an NPN transistor is used for logarithmic compression; and FIG. 2B is a diagram of a circuit in which a PNP transistor is used for logarithmic compression. In FIGS. 2A and 2B, reference numeral 1 denotes an operational amplifier; references 2 and 2' denote logarithmic compression NPN and PNP transistors, respectively; reference numerals 3 and 4 denote the inverting and non-inverting input terminals, respectively, of each amplifier; reference numeral 8 denotes switching means which, in this case, are each a relay such as an electromagnetic relay constituting a mechanical switching means; reference numerals 5 and 6 denote the contacts of each relay 8; and reference numeral 7 denotes the common contact of the relay. Contact 5 is connected to the respective collector terminals of transistors 2 and 2'; contact 6 is connected to the respective corresponding non-inverting inputs 4 of amplifiers 1; and common contact 7 is connected to the respective corresponding base terminals of transistors 2 and 2'.

In FIG. 2A, when a low signal current flows into inverting input 3, relay contact 6 is connected to common contact 7 while a high signal current flows into input 3, contact 5 is connected to contact 7.

FIG. 2B, when a low signal current flows out of inverting input 3, contact 6 is connected to contact 7 while when a high signal current flows out of input 3, contact 5 is connected to contact 7.

FIG. 3 shows a third embodiment of the present invention, wherein in the FIG. 2A embodiment relay 8 is replaced with electronic switching means, shown herein as MOS FETs 9 and 10. When a low signal current flows into inverting input 3, a gating signal is applied to the gate of FET 10 to render same conductive. When a high signal current flows into terminal 3, a gating signal is applied to FET 9 to render same conductive. If semiconductor elements such as MOS FETs 9 and 10 are used as switching means, they may be formed on a semiconductor substrate of the logarithmic compression circuit according to the present invention, and the resulting circuit will be inexpensive and easy to control from external means.

In the above embodiments, if a circuit portion such as shown in FIG. 1A, which does not oscillate when a high signal current is input thereto, is used by switching the switching means when a high signal current is input to a circuit portion, while the circuit portion such shown in FIG. 1B, the logarithmic compression characteristic of which does not deteriorate when a lower signal current is input thereto, is used by switching the switching means when a lower signal current is input to the circuit portion just mentioned, the entire circuit can cope with a wide range of signal currents.

As described above in detail, according to the embodiment of a logarithmic compression circuit, provision of switching means serves to prevent both oscillation of the circuit during high signal current input to same and deterioration of the logarithmic compression characteristic of the circuit during low signal current input to same. Thus a low-cost logarithmic compression circuit which can cope with a wide range of signal currents is provided.