Pipelined Digital-to-Analog Converter

This invention relates to a digital to analog converter wherein a series of three capacitor and transistor switch sections convert three bit segments of a digital word to an analog voltage which is pipelined to successive sections wherein the voltage across the last capacitor is, in fact, an analog representation of the applied digital signal.

Most conventional techniques for digital to analog conversion require both high performance analog circuitry, such as operational amplifiers, and digital circuitry for counting, sequencing, and data storage. This has tended to result in hybrid circuits consisting of one or more bipolar analog integrated circuit chips and an MOS chip to perform the digital function. High performance and fairly complex signal processing has recently become possible on a single monolithic chip due to the fact that very accurate capacitor ratios could be obtained in MOS technology to replace cumbersome conventional techniques such as diffused resistors, complex thin film process, or ion implanted resistors. One problem with existing integratd circuits is that the area of silicon occupied by capacitors increases exponentially as a function of the number of input bits. Hence, in the prior art it has been difficult to get enough accuracy for ten bit resolution with reasonable silicon area. Also, for high speeds (say, 10.sup.7 conversions/second) the amplifiers may not be fast enough.

The present invention discloses a series of three capacitor and switch sections to convert a three bit segment of a digital word. For a ten bit digital word, for example, three 3-capacitor sections would be required with an additional capacitor section. The voltage across the output, or last, capacitor is the analog voltage in direct relation to the input digital word. Each of the three capacitor sections works in relation to switched transistors to charge and discharge, in a predetermined fashion, said capacitors, in relation to the binary level of each of the three digits in the input digital word. The circuit operates from the least significant bit to the most significant bit, and converts the input digital word to an output analog voltage.

For a more complete understanding of the invention, reference may be had to the following detailed description of the invention in conjunction with the drawings wherein:

FIG. 1 is a schematic diagram of the digital to analog converter of the present invention showing two 3-capacitor sections; and

FIG. 2 is a schematic diagram of the sequence of timing signals applied to and utilized in the present invention.

FIG. 1 discloses a schematic diagram of a circuit which accomplishes the digital to analog conversion of the present invention, for 6-bit digital words. All capacitors are of equal size. Across the bottom of FIG. 1 can be seen capacitors C.sub.0 through capacitor C.sub.7. The next row up from the row of capacitors is a row of transistor switches Q.sub.0 through Q.sub.7. Each of these switch transistors is enabled by one of the timing signals .PHI..sub.1, .PHI..sub.2, or .PHI..sub.3. A row of switching transistors M.sub.1 through M.sub.12 selectively couples the circuit to the input binary digits under analysis. The PMOS transistor M.sub.1 would be responsive to the first binary digit b.sub.1.sup.k if it was in the logic one state. The NMOS transistor M.sub.2 would have the same first binary digit but be responsive to the logic zero state of this binary digit. The input to transistor M.sub.1 is the voltage suply V.sub.R which, as an example, may be 5 volts. The input to transistor M.sub.2 is connected to ground potential. Thus, the source electrode of transistor M.sub.1 is coupled to voltage V.sub.r, the gate electrode when .PHI..sub.1 is high is coupled to the input binary digit, while the drain electrode is coupled to the drain electrode of transistor M.sub.2 and to the capacitor network as shown in FIG. 1. When .PHI..sub.1 is high, transistor M.sub.2 's gate electrode is coupled to the complement of the input binary digit, while the source electrode of transistor M.sub.2 is connected to ground. The subsequent capacitor combinations are similar and will be described hereinafter.

When phase signal .PHI..sub.1 is applied to the circuit, none of the other two phase signals .PHI..sub.2 or .PHI..sub.3 are applied; thus they are non-overlapping timing signals. When timing signal .PHI..sub.1 is applied, transistor M.sub.1 or M.sub.2 would be enabled depending upon whether or not the input binary digit is a logic one or a logic zero. Also, upon the application of timing signal .PHI..sub.1, transistor switch Q.sub.0 is closed and capacitor C.sub.0 is coupled directly to ground through transistor Q.sub.0, thus discharging it completely. Transistor switch Q.sub.1 is open because timing signal .PHI..sub.2 has not yet been applied to transistor Q.sub.1. Thus, at .PHI..sub.1 =1, if the binary digit applied is a logic one, then transistor switch M.sub.1 is closed, M.sub.2 remains open, and the supply voltage V.sub.R is applied directly to and charges capacitor C.sub.1. As stated above, transistor Q.sub.1 is open because .PHI..sub.2 has not been applied; as is transistor Q.sub.2 open because timing signal .PHI..sub.3 has not been applied. Thus, at this particular moment T, with a binary digit b.sub.1 being in the logic one state, transistor M.sub.1 is on, with V.sub.R charging capacitor C.sub.1 to V.sub.R, which in this instance may be 5 volts. The resulting charge in C.sub.1 is q=C.sub.1 V.sub.R.

While the rest of the description will be analyzed with all binary one digits applied, it can be seen, however, that if binary digit b.sub.1 is a logic zero, transistor Q.sub.0 would still be closed, capacitor C.sub.0 would still be discharged to ground, transistors Q.sub.1 and Q.sub.2 would still be open because of the absence of timing signals .PHI..sub.2 and .PHI..sub.3, but now transistor M.sub.2 would be directly coupled to ground thereby discharging capacitor C.sub.1 to ground potential.

When timing signal .PHI..sub.1 turns off and a finite time elapses, timing signal .PHI..sub.2 is now applied, see FIG. 2. Transistor Q.sub.0 opens, transistor Q.sub.1 closes, transistor Q.sub.3 remains open, capacitors C.sub.0 and C.sub.1 are now connected through transistor Q.sub.1 in parallel and share their capacitive charge with each other. However, since C.sub.0 had no charge while C.sub.1 was charged to 5 volts, the charge on both C.sub.0 and C.sub.1 is now q/2. At this moment, assuming that bit b.sub.2 is also a logic one, capacitor C.sub.2 is charging to the supply voltage V.sub.R. Since at this moment timing signal .PHI..sub.3 is off, transistor Q.sub.2 is open. Thus, at this particular time, the charge on capacitor C.sub.0 is q/2, the charge on capacitor C.sub.1 is q/2, while the charge on capacitor C.sub.2 is equal to q.

Thus, the charge in the combined parallel capacitor combination of C.sub.0 and C.sub.1 is now q while the voltage is V.sub.R /2=2.5 volts. The voltage on capacitor C.sub.2 is equal to 5 volts at this moment. However, when timing signal .PHI..sub.2 turns off, capacitor C.sub.1 is alone again with a voltage of 2.5 volts and a charge of q/2. Capacitor C.sub.2 is also alone at this moment with a voltage of 5 volts and a charge of q.

When the next timing signal .PHI..sub.3 goes high, capacitors C.sub.1 and C.sub.2 are now connected in parallel for the first time. Thus, these capacitors, C.sub.1 and C.sub.2, share their charges as other capacitors share their charges above; so at this particular moment, the total charge of capacitors C.sub.1 and C.sub.2 is 3q/2, because the charge on capacitor C.sub.1 is q/2 while the charge on capacitor C.sub.2 is q, the total charge being 3q/2. Since each value of capacitance for capacitors C.sub.0 through C.sub.6 is the same, the voltage on each of the capacitors C.sub.1 and C.sub.2 is now the average of the 2.5 volts and the 5 volts, or combined voltage of 3.75 volts. Next, phase signal .PHI..sub.3 would go low leaving the 3.75 volt signal level on capacitor C.sub.2. Now, when timing signal .PHI..sub.1 goes high again, the charge on capacitor C.sub.2, that is 3q/4, is shared with capacitor C.sub.3 which is now charged to the charge q if the signal of bit 3 in the digital word is a logic 1. As above, the voltage on capacitor C.sub.3 is 5 volts but when it shares its voltage with capacitor C.sub.2, which above was seen to be 3.75 volts, the resultant voltage on capacitor C3 when timing signal .PHI..sub.1 goes low and C.sub.3 is isolated will be reduced. The voltage at this point on capacitor C.sub.3 would be the average of the 3.75 volts with the 5 volt signal or 4.375 volts at this particular moment. The charge is thus propagated along but is divided by two every time. Thus is introduced the weighting of the voltage by powers of 2. The formula for output voltage, for the case when all digits of the digital word equal 1, is therefore

where N is the number of bits b.sub.i. Thus, for a 4 bit word the resultant output analog voltage for a 4 bit word of all logic 1's would be 4.6875 volts; while for an 8 bit word the output analog voltage for all 1's in the 8 bit word would be approximately 4.98 volts. The voltage would decrease down to zero linearly for a combination of input binary digits of all logic zeroes. In the general case, the formula giving the output voltage is

Each of the three capacitor sections could have the input bits applied simultaneously and stored at the inputs to transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5, or M.sub.6, because the phase pulses .PHI..sub.1, .PHI..sub.2, and .PHI..sub.3 are sequential and non-overlapping. For a 10 bit converter, the circuit would comprise three 3-capacitor sections with an additional capacitor stage to equal 10 stages. It is the right most capacitor that has the output analog voltage on it. The last capacitor in FIG. 1 is designated C.sub.6, but in general can be C.sub.N for any number N of binary digits. If, however, the input digits were exactly six as shown in FIG. 1, capacitor C.sub.6 would be the output capacitor.

The main advantage to the above circuit is that no amplifiers are needed which would slow down the operation. The circuit only uses the capacitors and the switching transistors as set forth in the Figure.

Since the circuit shown updates the output voltage across C.sub.N only once in each 3 block cycles, 3 switched capacitor arrays, similar to that shown in FIG. 1 but operated by clock signals which are shifted by one clock interval from array to array, may be combined to realize a system which generates a new analog output signal in each clock interval.

It can be shown that clock feedthrough effects affect only the gain and the offset voltage, but not the linearity of the converter. This is acceptable in many applications.

While the invention has been described with reference to a specific embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, many modifications may be made without departing from the essential teachings of the invention. For instance, two reference voltages V.sub.R1 and V.sub.R2 may be used in FIG. 1 at the sources of M.sub.1 -M.sub.2, M.sub.3 -M.sub.4, etc., rather than V.sub.R and ground.