Adaptive Recursive Phase Offset Tracking System

1. Field of the Invention

This invention relates to radio receivers. More specifically, this invention relates to communications modems which incorporate phase tracking systems.

While the present invention is described herein with reference to particular embodiments and applications, it is to be understood that the invention is not limited thereto. Those of ordinary skill in the art having access to the teachings of this invention will recognize additional applications and embodiments within the scope thereof.

2. Description of the Prior Art

Many communication systems require rapid acquisition and accurate tracking of a data signal. In many satellite communication systems, such as coherent time division multiple access burst communication systems or coherent communications systems which utilize a fading transmission media, there is a requirement for a rapid initial acquisition (or a rapid reacquisition after a fade) of the signals phase. A coherent system is one which requires long term phase continuity relative to the time constant of the receiver. To facilitate communication, a satellite may send or receive a burst transmission of a coherent signal. The burst typically includes a train of blank pulses and a sequence of bits in a known pattern. The blank pulses are utilized to align the phase of the carrier with that of the local oscillator. The known bit pattern is utilized to ensure alignment of the bit sequence with the sampling mechanism of the receiver. The effectiveness of the communication system is a function of its ability to receive, interpret and align itself with the burst transmission.

Most communication systems typically utilize a phase locked loop to acquire and track the transmitted signal. The phase locked loop typically includes a single phase detector and occasionally exhibits unduly prolonged phase transients during initial acquisition or lock. The loop appears to stick, temporarily, at a large value of phase error before settling to its normal tracking condition of small error. This phenomenon has been dubbed the "hangup" effect and is discussed by Floyd M. Gardner in "Hangup in Phase Locked Loops", IEEE Transactions on Communications, Vol. COM-05, No. 10, October 1977. pp. 1210-1214.

Gardner points out that almost all phase detectors have a periodic characteristic of output voltage versus phase error. Because of the periodicity, the characteristic must have two nulls per cycle. One null has a slope which provides negative feedback for the loop and is the stable null for equilibrium tracking. The other null has a reverse slope which provides unstable, positive feedback so stable tracking about this null is not possible.

Experiments have indicated that if the initial phase error in a phase lock loop is very close to the reverse slope null, the loop can dwell in the vicinity of the null for a prolonged time. This is the "hangup effect".

Since the dwell time at the reverse null is finite, the loop cannot remain indefinitely at the unstable null. It must eventually move away and converge toward the normal equilibrium null assuming that no conditions exist that prevent eventual locking. However, if fast phase acquisition is needed, the hangup interval can be excessively long and can severely degrade the performance of fast time division multiple access sytems. For example, in the burst-mode digital communication system, rapid acquisition is demanded for efficient usage of channel time. Failure of the phase lock loop to settle within the allotted synchronization preamble (burst) prevents correct detection of the indentification preamble and causes loss of the entire burst.

Recent attempts to solve this problem have resulted in the substitution of narrow-band tuned filters for the phase lock loop. These systems typically split the received signal into two paths one of which contains a crystal filter. The crystal filter isolates the carrier which is subsequently reinserted into the second path to demodulate the received signal. Since the crystal filter typically has some delay, there is an alignment/static calibration problem which must be solved in order to ensure proper synchronization of the filtered carrier with the received signal. In addition, the tuned filters are typically expensive, complex and suffer other unwanted characteristics.

Yet another proposed solution suggests the use of a second phase detector in the phase lock loop. These systems are also more expensive, complex requiring more parts and effort in assembly. For example, these systems typically require a voltage controlled oscillator which prevents the system from being completely digital in design. The use of analog circuitry forces a compromise in performance in the acquisition and tracking of the carrier signal.

The present invention provides improved performance and reduced cost relative to conventional carrier phase tracking systems. The present invention improves the performance of the communication system by rapidly acquiring and reliably tracking the carrier signal with substantially digital hardware. The present invention has no reverse slope null characteristic and therefore does not suffer from hangup. As such, acquisition time is independent of phase error. These solutions are provided without the added expense and callibration problems of a crystal filter nor the performance compromise of the dual phase detector phase lock loop.

The present invention includes circuitry which removes the carrier from the received data signal and converts the signal to a complex baseband signal. The baseband signal is subsequently sampled to provide a plurality of complex samples. The phase error of each sample is extracted and accumulated to create an estimate of the absolute phase offset. The phase estimate is then applied to phase shifting circuitry which substantially compensates for the phase offset in the received data signal.

The FIGURE shows a block diagram of an illustrative embodiment of the present invention.

An illustrative embodiment of the present invention 10 is shown in the FIGURE. The RF subsystem 12 is not part of the invention and is shown for the purpose of illustration only. Radio signals received by the RF subsystem 12 are fed into demodulators 14 and 16 which are driven by the cos and the sin of .omega..sub.o t respectively. The sin .omega..sub.o t and cos .omega..sub.o t are generated by the phase splitter 20 which operates on the output of the local oscillator 18. The carrier signal is removed by the demodulators 14 and 16 which simultaneously generate the complex representation of the received signal. The outputs of the demodulators 14 and 16 are filtered by circuits 22 and 24. The filters 22 and 24 are low pass filters typically of the integrate and dump variety. The outputs of the circuits 22 and 24 are switched by gates 26 and 28, respectively, which operate on the control of a clock 27. (For the purposes of this illustration, the remaining clock connections to the circuits of the present invention are not shown. The timing and clocking of the present invention would be obvious to one of ordinary skill in the art.) Analog-to-digital converters (A/D) 30 and 32 are connected between the gates 26 and 28 and the phase shifter 34, respectively. The real part of the complex digital data signal is provided on line 36. The imaginary part of the complex digital data signal is provided on line 38.

The phase shifter 34 effectively corrects the phase of the signal received on lines 36 and 38 by an amount determined by the circuitry to be discussed more fully below. The real part of the signal shifted by the phase shifter 34 appears on line 40 and is input to a summing circuit 42. The imaginary part output of the phase shifter 34 appears on line 44 and is input to a phase detector 46 and a squaring operator 48. The output of the summing circuit 42 is input to the phase detector 46 and a second squaring operator 50. The outputs of the two squaring operators 48 and 50 are combined by summing circuit 52. Square root operator 54 takes the square root of the sum of the inputs from the squaring operators 48 and 50. A damping amplifier 56 multiplies the output of the square root operator by predetermined damping factor F. The output of the damping amplifier 56 is fed back to the summing operator 42 via delay operator 58.

The operation of the present invention can best be understood with reference to the following mathematical discussion. The signals received by the RF subsystem 12 can be assumed to be of the form Z(t). This represents a continuous signal at a center carrier frequency of .omega..sub.o. The demodulators 14 and 16 operate with the local oscillator 18 and the phase splitter 20 to remove the carrier signal and create a complex baseband signal from the received signal Z(t). A quadrature mix may be utilized to provide complex baseband signals without departing from the scope of this invention.

The low pass filters 22 and 24 average the received signal Z(t) by integrating over a time interval T.sub.s. Gates 26 and 28 are clocked to sample the complex baseband signal to derive a plurality of complex samples. The kth sample of a complex baseband signal may be expressed by the following equation: ##EQU1## Multiplication by e.sup.-j.omega..sbsp.o.sup.t represents the action of demodulators 14 and 16. The integral is evaluated at a time t which is equal to the product of the sample number k times the sampling interval T.sub.s.

The complex signal on lines 36 and 38 has its carrier component removed, but may have an arbitrary phase offset .psi.. It is this phase offset which the present invention removes from the baseband signal. Note that .psi. must remain essentially constant for intervals which are short compared to the loop bandwidth.

The first sample is passed through the phase shifter 34 to the squaring operators 48 and 50 without correction. The summing circuits 42 and 52, squaring operators 48 and 50, square root operator 54, damping amplifier 56 and delay operator 58 provide means for filtering the output of the phase shifter 34 to remove the effects of noise. The output of the low pass filter is given by the following equation:

where .phi..sub.k is the measured phase offset of the k.sup.th input sample Z.sub.k and .rho..sub.k e.sup.j.psi..sbsp.k is the output of the low pass filter expressed as a complex quantity; .psi..sub.k is the phase of the filter output and .rho..sub.k is the magnitude of the filter output. .psi..sub.k-1 is the estimated phase offset and F.rho..sub.k-1 is the bandwidth control parameter and a measure of loop tracking quality. F is the damping factor of the filter chosen as a system parameter to determine filter averaging time and thus to control the loop bandwidth. In the absence of noise, .phi..sub.k will assume the constant value .psi.. In that case, the k.sup.th filter output is equal to ##EQU2## Thus, for k>1, the estimate .psi..sub.k-1 will be equal to the actual phase offset .psi..

Squaring operators 48 and 50, summer 52 and square root operator 54 cooperate to provide the magnitude of the phasor output of the phase shifter 34. The damping factor F is applied by amplifier 56 and fed back to delay operator 58 so that F.rho..sub.k is stored and becomes F.rho..sub.k-1 for subsequent iteration. The low pass filter operation may be best explained in polar coordinates. Equation [2] is equivalent to Equations [3] and [4] below. That is, to examine the magnitude .rho..sub.k of Equation [2], one may multiply the right hand side of the equation by the term e.sup.j.psi..sbsp.k-1. This term is an argument term; it does not affect the magnitude .sigma..sub.k which may therefore be expressed by Equation [3] below.

Equation [3] above provides the magnitude of the filter output and Equation [4] below provides the phase. The phase .psi..sub.k is equal to the argument of Equation [3] plus a term which compensates for the multiplication at the right hand side of Equation [2] by e.sup.-j.psi..sbsp.k-1. Thus,

The phase detector 46, summing operator 60 and delay operator 62 provide means for extracting the argument term of Equation [4] which represents the phase estimate of the filtered samples. It provides the arguments of the sum of the current phasor with the previous filter output. The delay operator 62 serves to store the previous phase estimate .psi..sub.k-1 and input it to summing circuit 60 where it is added to the current phase detector output. Thus, the updated phase estimate .psi..sub.k is input to the phase shifter 34 via line 64.

The phase shifter 34 provides means for correcting the received data signal in response to the phase estimate to substantially compensate for a phase offset in the received data signal. It applies the absolute phase correction to the input signal Z.sub.k and provides an output signal which is the corrected input signal Z.sub.k e.sup.-j.psi..sbsp.k-1.

The embodiment of FIG. 1 is referred to as an illustrative embodiment, because the preferred embodiment of the tracking and filtering subsystem (components 34-62) would be implemented on a digital computer.

A typical program (written in the language PASCAL) is attached. Its inputs are the signals from lines 36 and 38 and its outputs are the signals on lines 40 and 44.

The digital computer program is diagramatically represented by components 34-62. The phase shifter 34 effectively corrects the phase of the signal received on lines 36 and 38 and provides a corrected output signal on lines 40 and 44. The real part of the received signal is provided on line 36, and a corresponding corrected real part of the output signal is provided on line 40. The imaginary part of the received signal is provided on line 38, and a corresponding corrected imaginary part of the output signal is provided on line 44. Components 42 and 46-64 calculate an updated phase estimate, .psi.k, in a manner described in detail above based upon the corrected signal on lines 40 and 44, and input that updated phase estimate to the phase shifter 34 on line 64.

Thus, the phase correction applied to a signal provided on lines 36 and 38 by the phase shifter 34 is based upon a phase estimate, .psi.k, calculated based upon previous corrected output signals on lines 40 and 44. A corrected output signal on lines 40 and 44, therefore, can provide both as an output signal from the system 10 and a data signal used by components 42 and 46-64 to calculate an updated phase estimate.

While the present invention has been described above with reference to particular embodiments and applications, it is to be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings of this invention will recognize additional embodiments and applications within the scope thereof.

For example, a slightly modified version of the present invention may be utilized in systems which employ differential phase shift keyed data demodulation. In these systems, it is necessary to estimate the phase of the signal on a symbol-by-symbol basis. Conventional phase lock loops are unsuitable for this purpose because they cannot track a signal with phase discontinuities. The present invention may be adapted for such applications as follows. The damping parameter F would be set to zero to allow symbol-by-symbol phase estimation, and as a result .rho..sub.k would always be zero. This could be accomplished simply by removing from the illustrative embodiment of FIG. 1 summing circuits 42 and 52, squaring operators 48 and 50, square root operator 54, damping factor amplifier 56 and delay operator 58. In this case, Equation [4] reduces to

so that the output of the system is

Since .phi..sub.k-1 is by definition the argument of Z.sub.k, this modified system would implement phase-comparison detection for DPSK signals. ##SPC1##