US 4,709,346 AGrant
CMOS Subtractor
Issue Date:1987-11-24
•1 Claims
•1 Drawing Sheets
Abstract
A subtractor for an N-bit digital number comprising N cascaded cells, each cell being adapted to effect subtraction by two's complement arithmetic and to provide a carry-out signal in accordance with the level of two bits being processed and a carry-in signal.
Metadata
Assignee
- Raytheon Company
Inventor
- Dennis A. Henlin
Application Information
Application Number:US 7184123
Filing Date:1985-04-01
Priority Date:1985-04-01
Art Unit:231
Classifications
IPC:
G06F 742G06F 750H03K 1921H03K 1920
Field of Search:
364307768;784;785;786471;472
Patent Drawings (1 sheets)
Description
Background of the Invention
This invention pertains generally to CMOS very large scale integrated (VLSI) circuits formed on semiconductor chips and particularly to a CMOS binary difference cell.
The most common method of performing a subtraction of two binary numbers (A-B) is to invert the subtrahend (B) and add it to the minuend (A) in a binary adder, the carry-in input being set to a logic level one. When the binary numbers being processed are N-bit numbers (where "N" is an integer greater than one), N+1 inverter and binary adder stages are required. Each inverter stage occupies space on the semiconductor chip, consumes power and slows operation. Furthermore, the complexity of the design of each binary adder stage is increased to be sure that the carry-in input is at a logic level one when subtraction is being carried out. Finally, it will be appreciated that the N+1 binary adder stage is required for subtraction utilizing two's complement arithmetic on two N-bit numbers to allow sign information of the difference to be provided.
Summary of the Invention
With the foregoing background of the invention in mind, it is a primary object of this invention to provide a CMOS binary difference cell wherein an extra stage is not required to take care of a sign bit.
It is another object of this invention to provide a CMOS binary difference cell wherein the speed of subtraction of two binary numbers is increased.
The foregoing and other objects of this invention are generally attained by providing an N-stage subtractor, each stage being a CMOS binary cell that produces an output in two's complement form which represents the difference (A-B) where A is the minuend and B is the subtrahend of corresponding bits in two binary numbers being processed. Each binary cell operates on three inputs A.sub.i, B.sub.i and X.sub.i (where A.sub.i and B.sub.i are two binary digits and X.sub.i is a borrow input signal) to provide a difference output, D.sub.i, and a borrow output, X.sub.i+1, that, when N cells are combined, form an N-bit subtractor.
Brief Description of the Drawings
For a more complete understanding of this invention, reference is now made to the following description of the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of a CMOS binary difference cell according to this invention; and
FIG. 2 is a sketch illustrating how N binary difference cells of FIG. 1 may be combined to form an N-bit subtractor.
Description of the Preferred Embodiment
Referring now to FIG. 1, a CMOS binary difference cell 10 according to this invention is shown to receive A.sub.i, B.sub.i and X.sub.i input signals and to provide a difference, D.sub.i, and a borrow-out, X.sub.i+1, output signals. The truth table for the binary difference cell 10 is presented in TABLE 1.
From an inspection of the truth table of Table 1, it will be apparent to one of skill in the art that the difference output, D.sub.i, of the binary difference cell 10 can be described by the following Boolean equation:
The borrow-out output, X.sub.i+1, of the binary difference cell 10 may be defined as follows:
It should now be appreciated by those of skill in the art that if the borrow-in input, X.sub.i, of Equation (1) were replaced with a carry-in input, C.sub.i, then Equation (1) would provide the sum of A.sub.i, B.sub.i and C.sub.i. The borrow-out term, X.sub.i+1, defined by Equation (2) is, however, substantially different from the equation defining the carry-out output, C.sub.OUT, of a full adder. In a co-pending application (Ser. No. 648,930 filed Sept. 10, 1984 and assigned to the same assignee as the present invention) a high speed CMOS full adder was described and claimed, and in that application the carry-out output, C.sub.OUT, of the full adder was defined as follows:
It follows, therefore, that the implementation of the borrow-out output defined by the Equation (2) is essentially different from the implementation of the carry-out output defined by Equation (3).
Before proceeding with a detailed explanation of the operation of the CMOS binary difference cell 10, it should be noted that the device is partially fabricated from transmission gates that represent a manner of connecting MOS transistors that is unique to CMOS logic. In general, the transmission gate is effective to pass the signal on its input terminal to the output terminal when the n-channel terminal is at a logic level 1 and the p-channel terminal is at a logic level 0. Conversely, when the n-channel terminal is at a logic level 0 and the p-channel terminal is at a logic level 1, the transmission gate is in its OFF condition and there is no transmission through the device.
Inverters I.sub.1 and I.sub.2 together with transmission gates T.sub.1 and T.sub.2 are effective to form an exclusive-OR gate that provides an A.sub.i .sym.B.sub.i output that is hereinafter referred to as the P signal. Inverter I.sub.3 then provides the exclusive-NOR output A.sub.i .sym.B.sub.i, referred to hereinafter as the P signal. The P and P signals are used to control the transmission gates T.sub.3, T.sub.4 and T.sub.5. It will be appreciated that the transmission gates T.sub.3 and T.sub.4 together with the inverter I.sub.4 are effective to form an exclusive-OR gate that produces the difference output, D.sub.i. Thus, when the P signal is a logic level 0 (indicating that the A.sub.i and B.sub.i inputs are the same, i.e., at either a logic level 0 or 1), transmission gate T.sub.4 is OFF, transmission gate T.sub.3 is ON and the borrow-in input, X.sub.i, is the difference output, D.sub.i. Conversely, when the P signal is a logic level 1 (indicating) that the A.sub.i and B.sub.i inputs are dissimilar) transmission gate T.sub.3 is OFF, transmission gate T.sub.4 is ON, and the borrow-in signal, after inversion in inverter I.sub.4, is the difference output, D.sub.i.
The borrow-out output, X.sub.i+1, is formed by transmission gate T.sub.5, the p-channel field effect transistors (FETS) P1 and P2, and the n-channel FETS N3 and N4. The p-channel FET, P1, and the n-channel FET, N4, are both gated by the A.sub.i input, while the p-channel FET, P2, and the n-channel FET, N3, are gated by the inverse B.sub.i input, B.sub.i, out of the inverter I.sub.2. The p-channel FETS P1 and P2 generate the borrow output when the A.sub.i and B.sub.i inputs are, respectively, a logic level 0 and 1. Thus, when A.sub.i is a logic level 0, n-channel FET, N4, is gated OFF and p-channel FET is gated ON; and when B.sub.i is a logic level 1, the inverter I.sub.2 is effective to provide a logic level 0 to the gate terminals of n-channel FET N3 and p-channel FET P2, turning those devices OFF and ON, respectively. With the p-channel FETS P1 and P2 ON and the n-channel FETS N3 and N4 OFF, a logic level 1 is provided as the borrow-out output, X.sub.i+1. From the foregoing, it should now be appreciated that the n-channel FETS N3 and N4 are effective to kill the borrow output (i.e., provide a logic level 0 as the borrow-out output, X.sub.i+1) when the A.sub.i and B.sub.i inputs are, respectively, a logic level 1 and 0.
Finally, when the A.sub.i and B.sub.i inputs are both either a logic level 0 or 1, neither the p-channel FETS P1 and P2 nor the n-channel FETS N3 and N4 are both simultaneously ON or OFF and, therefore, the borrow-in input, X.sub.i, is provided, via the transmission gate T.sub.5, as the borrow-out output, X.sub.i+1.
From the truth table presented in Table 1 and the foregoing description of the operation of the CMOS binary difference cell 10, it will now be appreciated by those of skill in the art that if A.sub.i and B.sub.i are bits of the minuend and the subtrahend, respectively, and if A.sub.i =0 and B.sub.i=1, there will be a borrow-out, X.sub.i+1 to the bits of next higher numerical significance. In subtracting multibit numbers, therefore, one must take account of the borrow-out, X.sub.i, from the immediately previous stage.
Referring now to FIG. 2, the CMOS binary difference cell 10 can be cascaded (repeated) N times, as shown, to form an N-bit subtractor 20. It should be noted that the N-bit subtractor 20 is effective to perform the subtraction of two N-bit numbers with a total of N stages (cells) as opposed to two's complement arithmetic wherein N+1 stages are required, the extra stage providing for the sign bit. Here the sign bit information is provided by the borrow-out output of the N.sup.th stage. In order to illustrate the operation of the N-bit adder 20, consider the case where the minuend, A, is seven, the subtrahend, B, is five and the least significant borrow-in, X.sub.0, is set to zero. The minuend, A, as a four-bit word is (0111) and the subtrahend, B, as a four-bit word is (0101). From Table 1, it follows that D=(0010) and X.sub.N+1 =0, meaning that the difference is two and that there is no borrow-out output. If, on the other hand, the minuend, A, were 5(0101) and the subtrahend, B, were 7(0111) and the least significant borrow-in, X.sub.0, were set to zero, then from Table 1, the difference D=1110 and the borrow-out output X.sub.N+1 =1, which may be interpreted as indicating that the difference is negative. If this is the case, it will be recognized that the difference, D=1110, is indeed the two's complement form of -2.
Having described a preferred embodiment of this invention, it will now be apparent to those of skill in the art that many changes may be made without departing from the inventive concepts described. It is felt, therefore, that this invention should not be limited to the disclosed embodiment, but rather by the spirit and scope of the appended claims.
Claims
What is claimed is:
1. In a digital computer wherein the difference between two N-bit binary numbers is to be calculated, N stages of cascaded binary adders to effect subtraction by utilizing two's complement arithmetic, starting from the least significant bits in the two N-bit binary numbers, each one of the N stages being fabricated in CMOS circuitry to accept corresponding bits A.sub.i, B.sub.i, and a borrow-in signal, X.sub.i, and to produce a difference signal, D.sub.i, and a carry-out signal, X.sub.i+1, each one of the N stages comprising: (a) a first and a second inverter, responsive respectivey to the A.sub.i and B.sub.i bits to product A.sub.i and B.sub.i signals; (b) a first transmission gate conditioned to pass the A.sub.i bit when the B.sub.i bit is at a logic zero level and the B.sub.i signal is at a logic one level; (c) a second transmission gate conditioned to pass the A.sub.i signal when the B.sub.i bit is at a logic one level and the B.sub.i signal is at a logic zero level; (d) OR gate means, responsive to the outputs of the first and the second transmission gates, for producing a signal P corresponding to the one of the first and second transmission gates conditioned to pass a signal; (e) a third inverter, responsibe to the signal P, for producing a signal P; (f) a fourth inverter, responsibe to the borrow-in bit X.sub.i, for producing a signal X.sub.i ; (g) third and fourth transmission gates, conditioned by the signal P and to the signal P to pass either the borrow-in bit X.sub.i or the signal X.sub.i ; and (h) borrow-out generating means, responsive to the carry-in signal, X.sub.i, the P signal, the P signal, the bit A.sub.i and the output B.sub.i of the second inverter, to produce a borrow-out signal described by the Boolean expression, [(A.sub.i +B.sub.i)X.sub.i +A.sub.i B.sub.i ], the borrow-out generating means consisting of: (i) a pair of p-channel FETS and a pair of n-channel FETS connected serially between a voltage source and ground and controlled by the bit A.sub.i and the output B.sub.i of the second inverter to produce the carry-out signal X.sub.i+1 when the logic level of the bits A.sub.i, B.sub.i differ, the pair of p-channel FETS being conductive when A.sub.i =0 and B.sub.i =1 to produce X.sub.i+1 =1 and the pair of n-channel FETS being conductive when A.sub.i =1 and B.sub.i =0 to produce X.sub.i+1 =0; and (ii) a fifth transmission gate, conditioned by the P and P signals to produce X.sub.i+1 =X.sub.i when A.sub.i =B.sub.i.
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