US 4,707,197 AGrant
Method of Producing a Silicide/Si Heteroepitaxial Structure, and Articles Produced by the Method
Issue Date:1987-11-17
•8 Claims
•2 Drawing Sheets
Abstract
Described is a method for producing metal silicide/silicon heterostructures. The method comprises depositing a very thin Si "template" layer on a relatively cold (<200.degree. C.) silicide substrate, raising the substrate temperature into the approximate range 500.degree.-800.degree. C. and maintaining it there while depositing further Si onto the template. The resulting Si layer can be of high crystalline perfection. The silicide advantageously is CoSi.sub.2, Co.sub.x Ni.sub.1-x Si.sub.2, CoSi.sub.y Ge.sub.2-y, or NiSi.sub.2, with 0<x<1,1<y<2.
Metadata
Assignee
- American Telephone and Telegraph Company, AT&T Bell Laboratories
Inventors
- John C. Hensel
- Anthony F. J. Levi
- Raymond T. Tung
Application Information
Application Number:US 8205817
Filing Date:1986-01-17
Priority Date:1984-08-02
Art Unit:114
Classifications
IPC:
H01L 21203
Field of Search:
14829156357427175;1.5;187;DIG. 140;DIG. 147;DIG. 25;DIG. 72576 E;576 T612;60316;6086
Patent Drawings (2 sheets)
Description
Field of the Invention
This invention pertains to the field of electronic devices comprising a single crystal semiconductor substrate with an epitaxial metal layer thereon, and to methods for producing such devices.
Background of the Invention
Since the early days of semiconductor device development, researchers have proposed metal base transistors, i.e., electronic devices in which electrons are injected from a semiconductor emitter into a thin metal base layer. For at least one type of metal base transistor, it is required that a significant fraction of the injected electrons traverse the base layer without being scattered, and furthermore, penetrate a metal/semiconductor interface to enter into the semiconductor collector.
Early theoretical treatment of such structures suggested that practical metal base transistors of this type were achievable without the necessity for further significant advances in technology. For instance, in a paper by J. L. Moll (IEEE Transactions on Electron Devices, Vol. ED/10, pp. 299-304, (1963)) it was stated that gold appears to be the most favorable metal for the metal base, that a 200 .ANG. thick gold film will transmit approximately 60 percent of the injected electrons, and that the quantum mechanical reflection at the base/collector interface is probably very small.
However, careful later work showed that, because of fundamental physical limitations, even the performance of proposed optimal metal base transistors would fall far short of previous expectations. For instance, the Si/Au/Ge metal base transistor was found to have a maximum low frequency common base current gain in the neighborhood of 0.3. It was also stated that it is unlikely that a materials combination exists that is capable of yielding substantially higher current gain. (S. M. Sze et al, Solid State Electronics, Vol. 9, pp. 761-769, (1966), incorporated herein by reference.) The authors of that paper also concluded that the greatest unsolved technological problem in semiconductor/metal/semiconductor transistor technology is the deposition of device-quality semiconductor materials on thin metal films, since, as of the date of the paper, there had been no reports of epitaxial growth of semiconductor material on films of the metals with longest electron mean free paths, namely, gold and silver.
Possibly to avoid the above-referred to technological problems, transistor structures that avoided the necessity to grow device-quality semiconductor material atop a metal layer were proposed and built. For instance, C. O. Bozler et al (IEEE Technical Digest, International Electron Device Meeting, pp. 384-387, (1979)), disclosed a permeable-base transistor in which an extremely fine tungsten grating is embedded inside a single crystal of n-type gallium arsenide, with the grating providing means for controlling the current from the emitter to the collector.
A major step towards realization of practical ballistic electron devices was the discovery, by J. C. Bean et al, of a method for preparing metal silicide/silicon heterostructures that yield a device-quality metal layer, the silicide layer, atop a single crystal silicon substrate. Since the silicide layer could be grown to be epitaxial with the substrate, the silicide layer could form the substrate for growth thereon of an epitaxial semiconductor layer, making possible the growth of epitaxial heterostructures incorporating a metal layer. See U.S. patent application Ser. No. 156,649, filed June 5, 1980, now U.S. Pat. No. 4,492,971, and U.S. patent application Ser. No. 445,014, filed Nov. 29, 1982, now U.S. Pat. No. 4,554,045 both co-assigned with this and incorporated herein by reference. In the former application are disclosed also articles comprising a single crystal silicon substrate, a single crystal metal silicide layer overlying the silicon substrate, and a single crystal silicon layer overlying the metal silicide, with the thus formed composite structure having an essentially continuous single crystal lattice between the three layers. Cobalt silicide and nickel silicide are exemplary silicides disclosed in the above applications.
Further relevant disclosures were made by Gibson et al (U.S. patent application Ser. No. 429,291, now U.S. Pat. No. 4,477,308, co-assigned with this), and incorporated herein by reference, namely, a method for growing epitaxial silicide on silicon comprising deposition of a thin template layer. This approach permits, inter alia, control of the orientation of silicide grown on (111)-oriented silicon, where the epitaxial material can grow in one of two orientations (A or B), or as a mixture thereof. H. Ishiwara et al, Materials Research Society Symposium Proceedings, Vol. 25, pp. 393-403 (1984) disclose growth of Si on a CaF.sub.2 substrate by pre-deposition of a thin Si layer at room temperature, followed by deposition thereon of a thick Si film at 800.degree. C.
Although great strides have recently been made in the growth of epitaxial metal layers on semiconductors, we know of no practical ballistic electronic devices. Because of the great promise of such a device, especially its potential for very high frequency operation, such a device would be of considerable commercial interest. This application discloses such a device.
Definitions
"Electron mean free path" is used herein in its conventional sense, namely, the average distance an electron travels between collisions. See, for instance, J. M. Ziman, Electrons and Phonons, Oxford University Press (1960), page 259. The mean free path is understood herein to be the mean free path of electrons at or near the Fermi energy. The average distance between collisions for electrons at other energies, e.g., "hot" electrons, typically will differ from the mean free path.
The "composition" of the layers of multiconstituent materials referred to herein is the nominal average composition of the layer material. For instance, if the layer material is not homogenous, e.g., when a layer of Si is deposited onto a previously deposited layer of Co, the "composition" of the layer material is the same as if the same amounts of Co and Si had been co-deposited.
By "metal silicide" we mean herein binary materials such as NiSi.sub.2 and CoSi.sub.2, as well as ternary materials such as Co.sub.x Ni.sub.1-x Si.sub.2 and CoSi.sub.y Ge.sub.2-y.
Summary of the Invention
We have discovered that a silicon/metal silicide/silicon heterostructure can be used to construct ballistic metal base transistors and other ballistic electronic devices of a quality far better than was thought possible in the prior art. In preferred embodiments, the metal silicide is nickel silicide (NiSi.sub.2), cobalt silicide (CoSi.sub.2), Co.sub.x Ni.sub.1-x Si.sub.2 (0<x<1, preferably 0.5<x), or CoSi.sub.y Ge.sub.2-y (1<y<2, preferably 1.5<y) with the cobalt silicide and the ternary materials being more preferred. In preferred embodiments the crystal lattice of the single crystal silicide substrate is oriented to have a (111) lattice plane substantially parallel (typically within about 5 degrees, as is often the practice in MBE growth) to the silicon/silicide interface.
In general terms, the invention is an article comprising two bounding members (frequently referred to herein as "emitter" and "collector") and a single crystal metal silicide layer (often referred to herein as "base") therebetween. One of the bounding members is a single crystal silicon substrate onto which the silicide layers is deposited. The other bounding member is a silicon layer overlying the silicide layer. The silicide layer is epitaxial with the silicon substrate, and the silicon layer typically is epitaxial with the silicide layer; that is to say, the crystal lattice direction, normal to the interface, namely, the [111] direction, is essentially continuous across the substrate/silicide layer interface and preferably also across the silicide layer/silicon layer interface. Although the silicon layer preferably consists of B-type (or A-type) material only, for some applications the layer can consist of a mixture of A- and B-type material, or possibly even be polycrystalline. Heterostructures according to the invention are thermally stable, at least to the degree that it is possible to anneal a Si/silicide structure with a relatively thick (e.g., 5000 .ANG.) Si layer thereon at about 800 degrees C. for about 30 minutes, sufficient to remove implantation damage in the Si layer.
The inventive article is adapted for injecting electrons from one of the bounding members, the emitter, into the metal silicide layer. This typically requires means for making electrical contact at least to the emitter and to the silicide layer (typically also to the collector). Injection requires application of voltages of the appropriate polarity, typically between the emitter and the silicide layer, and also between the silicide layer and collector.
In articles according to the invention, the electron mean free path (mfp) in the silicide layer at or below 25 degrees C. typically is longer than the thickness of the silicide layer, thereby making possible a high current transfer ratio between emitter and collector. Unless otherwise stated, values of all physical parameters herein are understood to be the values at 25 degrees C.
An electronic device having the above-specified property that the room temperature electron mean free path in the silicide layer exceeds the thickness of the silicide layer we call a ballistic electronic device. This is to be contrasted with conventional devices, e.g., bipolar transistors, in which essentially all electrons suffer a multiplicity of collisions during their transit of the base layer, executing a diffusive drift motion across the base. Such motion is relatively slow. On the other hand, the ballistic traversal of the silicide layer in the device according to the invention is extremely fast (of the order 10.sup.-14 seconds), since the electron velocity is of the order of the Fermi velocity in the silicide, a metal, and the silicide layer can be very thin, of the order of 100 .ANG., due to the high conductivity of the silicide. Devices according to the invention thus have the potential of operation at very high frequencies.
A novel method for producing a Si layer that is epitaxial with an underlying metal silicide layer comprises depositing a very thin layer (typically between about 10 .ANG. and about 100 .ANG. thick) onto the silicide layer substrate, with the substrate maintained at a relatively low temperature, typically below about 300 degrees C. Subsequently, the substrate temperature is raised, typically to the range 500-800 degrees C., maintained at the higher temperature for a time effective to result in ordering of the deposited Si, typically less than about 15 minutes, and further Si deposited. An optional brief intermediate temperature anneal may at times be advantageously used. With this deposition technique we have succeeded in growing Si layers that are epitaxial with the underlying metal silicide layer and have a .chi..sub.min <10 percent.
Brief Description of the Drawings
FIG. 1 is a schematic representation of an exemplary Si/silicide/Si structure according to the invention;
FIG. 2 is a band diagram for an exemplary heterostructure according to the invention;
FIG. 3 is a further exemplary band diagram;
FIG. 4 shows the resistivities of NiSi.sub.2 and CoSi.sub.2 as a function of temperature; and
FIG. 5 shows the magnetoresistance of CoSi.sub.2.
Detailed Description
In the broadest sense, the invention is an article comprising a multilayer composite structure, the structure comprising a single crystal silicon substrate, a single crystal metal silicide layer overlying the substrate, and a silicon layer overlying the silicide layer. Although the article may comprise further layers, including further metal silicide layers, the discussion herein will be generally in terms of a three-level structure only. This is for purposes of concreteness only and is not intended to imply that the invention is thus limited.
A central aspect of the invention is the requirement that (at 25 degrees C. or below) the electron mfp in the metal silicide layer be long, typically exceeding the silicide layer thickness. This implies use of a very thin silicide layer and/or use of highly perfect silicide material in which electrons can travel a considerable distance before being scattered.
We have found that a reasonable layer thickness is about 100 .ANG., with the useful range of thickness typically being from about 50 .ANG. to about 200 .ANG., and have discovered a method that can reliably produce such thin layers of highly perfect epitaxial single crystal silicide. We have also discovered that metal silicides, in particular, cobalt silicide (CoSi.sub.2) and nickel silicide (NiSi.sub.2), can be prepared such as to have a surprisingly long electron mfp. Of these, CoSi.sub.2 has a particularly long mfp, about 200 .ANG. at room temperature, and is currently considered to be the most preferred silicide for devices according to the invention.
The finding that metal silicides can have such long mfp is surprising in view of contrary teachings in the prior art. For instance, the prior art teaches that Au and Ag have the longest mfp (about 220 .ANG. and 350 .ANG., respectively), that other monovalent metals and transition metals are expected to have a mfp smaller than Au, and that, due to the presence of additional scattering mechanisms, all intermetallic components such as MoSi.sub.2 have a still shorter mfp. (Sze et al, op. cit., page 755.)
At least some metal silicides e.g., (CoSi.sub.2, Co.sub.x Ni.sub.1-x Si.sub.2, CoSi.sub.y Ge.sub.2-y and NiSi.sub.2) not only have an unexpectedly long mfp, comparable to that of Au, but they can also be grown epitaxially on a Si substrate. Furthermore, Si can be grown epitaxially on these silicides, making possible growth of a multilayer structure in which the crystal lattice orientation is continuous throughout. Some techniques for such epitaxial growth were disclosed in previously referred to U.S. patent applications Ser. Nos. 156,649 and 445,014.
An exemplary three-terminal device 10 according to the invention is schematically depicted in FIG. 1. Single crystal silicide layer 12 is sandwiched between two Si bounding members, namely, substrate 11 and layer 13. Electrical contact can be made to substrate, silicide layer, and Si layer by means of terminals 14, 15, and 16, respectively.
Typically, both Si bounding members comprise doped material. For instance, at least the substrate material at the substrate/base interface (typically epitaxial Si), as well as the interface portion material of the Si layer, may be doped with a donor element (col. V), e.g., As. However, doping with an acceptor element (col. III) is also possible and is contemplated. Furthermore, the dopant may be distributed substantially uniformly in the relevant part of a bounding member, or a nonuniform doping profile may be used. For instance, it may be desirable to provide for a relatively lightly doped (e.g., about 10.sup.16 cm.sup.-3 dopant atoms) Si region at the interface with the silicide, and a relatively heavily doped (e.g., 10.sup.19 cm.sup.-3 dopant atoms) Si region bordering thereon. Such doping is discussed, for instance, in Sze et al. On the other hand, it may be desirable to heavily dope the Si at and near the interface with the silicide, resulting in a tunneling barrier between the silicide and the Si member. Another possibility is "spike" doping of the Si layer material, e.g., forming a very thin p-type layer in n-type material. Such a layer could, for instance, be formed by MBE at, or close to, the silicide/Si layer interface, to increase the Schottky barrier height.
FIG. 2 shows an exemplary equilibrium band diagram of a three-layer combination (Si/silicide/Si) according to the invention. Bounding members 20 and 22 are shown to be n-type material, having roughly equal moderate dopant concentration, since Fermi levels 25 are shown within the energy gap between valence bands 23 and close to conduction band edges 24. The energy bands of silicide layer 21 are filled to the Fermi level 26. As is well known, in equilibrium the potentials at a junction between dissimilar materials adjust such as to make the Fermi levels equal throughout the sample. This results in bending of the semiconductor band structure near the junctions, as shown in FIG. 2. The quantities .phi..sub.e and .phi..sub.c are the Schottky barrier heights between the silicide and the "emitter" bounding member, and between the silicide and the "collector" bounding member, respectively. In FIG. 2, .phi..sub.e is shown to be approximately equal to .phi..sub.c. This is not necessarily the case, and it may actually be advantageous for .phi..sub.c to be less than .phi..sub.e.
An exemplary band diagram of a heterostructure with .phi..sub.e >.phi..sub.c is shown in FIG. 3. Applied potentials V.sub.e (<0) and V.sub.c (>0) forward bias the emitter base junction and reverse bias the base/collector junction, respectively, resulting in a net current from 20 to 22 by injecting electrons from 20 into the "base" 21, a fraction .alpha. of the injected electrons crossing over the base/collector barrier.
The probability that a carrier will be able to penetrate the collector from the base increases with increasing excess energy of the carrier over the collector barrier. For this reason, it is advantageous to choose a heterostructure such that .phi..sub.e >.phi..sub.c. The Si/silicide system offers a unique opportunity for achieving this, while at the same time maintaining the crystal lattice orientation continuous throughout the device, as will now be discussed.
As was disclosed before (U.S. patent application Ser. No. 429,291), at least some metal silicides, including CoSi.sub.2 and NiSi.sub.2, can grow on a (111)-oriented Si substrate epitaxially as either A-type material, B-type material, or as an A-B mixture. A-type material has an orientation identical in every way to that of the substrate. In particular, every crystal lattice direction [abc] is identical in the Si substrate material and A-type silicide overlying the substrate. On the other hand, in B-type material the lattice orientation is continuous across the Si/silicide interface (both substrate and silicide are of (111) orientation), but the overlying silicide lattice is rotated by 180 degrees with respect to the substrate lattice. This results in discontinuity of some crystal lattice directions across the interface. For instance, the [111] direction normal to the interface is continuous across the interface, whereas all [100] directions are discontinuous.
It has been found that A-type NiSi.sub.2 on Si and B-type NiSi.sub.2 on Si do not have identical Schottky barrier heights, but that the latter exceeds the former by about 0.14 eV. (R. T. Tung, Physical Review Letters, Vol. 52, page 461 (1984).) Since it is possible to selectively grow either A-type or B-type material, it is thus possible to manufacture devices comprising Si/silicide/Si heterostructures with non-symmetrical barrier heights. For instance, in an exemplary metal base transistor the (111)-oriented Si substrate is the collector, the base is A-type NiSi.sub.2, and the Si emitter is B-type with respect to the base (and collector).
The major hurdle towards realization of a viable metal base transistor that was encountered by the prior art was the inability to grow device-grade semiconductor material atop the metal base. The Si/silicide system overcomes this problem. NiSi.sub.2 and CoSi.sub.2 have the same crystal structure as Si, and have lattice constants that are very close to that of Si (5.41 .ANG. and 5.37 .ANG., respectively, vs. 5.43 .ANG.). Ternary materials such as Co.sub.x Ni.sub.1-x Si.sub.2 (0.5<x<1) and CoSi.sub.y Ge.sub.2-y (1.5<y<2) can have better lattice match than CoSi.sub.2 while retaining much of the high conductivity of CoSi.sub.2, can be grown such as to form an essentially continuous layer of high quality epitaxial material, and are considered by us to be materials that may advantageously be used in electronic devices according to the invention, e.g., in a metal base transistor. In heterostructures according to this invention, the Si layer overlying the silicide layer typically has a Rutherford backscattering ratio .chi..sub.min less than about 10 percent, preferably less than about 6 percent. .chi..sub.min is the ratio of the backscattering yield in a channeling direction, e.g., [111], to the yield in a random direction, and is a well-known measure of crystal perfection.
Due, inter alia, to the long electron mfp in the silicide (as compared to the base layer thickness), the high crystalline perfection of the Si layer overlying the base, and the continuity of lattice orientation and minimal change of lattice constant throughout the inventive heterostructure, metal base transistors according to the invention can have current transfer ratios exceeding those previously thought possible. Such transistors typically will have DC common base current gain of at least 0.5 at 25 degrees C. or below, but preferably have a current gain greater than 0.8 or 0.9.
As we have stated above, CoSi.sub.2, when grown under appropriate conditions on Si, can have an unexpectedly long electron mfp. This manifests itself, inter alia, in an unexpectedly low value of the residual resistivity of such material, as is shown in FIG. 4, in which the resistivity of a thick (>1000 .ANG.) CoSi.sub.2 film is contrasted with that of a similar NiSi.sub.2 film. As can be seen, the latter has a residual resistivity (at T.about.4.2 degrees K.) almost eight times that of the former. On the other hand, the linear portions of the two resistivity curves are quite similar, implying similar electron-phonon coupling in the two materials.
The electron mfp is most directly determined by means of magnetoresistance measurements, since:
and
where:
.LAMBDA..sub.e is the electron mfp,
k.sub.F is the Fermi wavevector,
h is Planck's constant,
c is the velocity of light,
e is the electron charge,
H is the value of the magnetic field,
.omega..sub.c is the cyclotron frequency,
.tau. is the electron mean free time,
.rho. is the resistivity at zero magnetic field,
.DELTA..rho. is the change in resistivity with magnetic field, and
A is a known factor of order unity. In CoSi.sub.2, for instance, A is about 0.5. A curve of magnetoresistance of CoSi.sub.2 at 4.2 degrees K. as a function of magnetic field is shown in FIG. 5.
Evaluating Equation 1 for CoSi.sub.2 at 4.2 degrees K. yields an electronic mfp of about 1000 .ANG., and a mfp of about 200 .ANG. in CoSi.sub.2 at room temperature.
Detailed analysis of the magnetoresistance of CoSi.sub.2 indicates that both electrons and holes participate in charge transport in CoSi.sub.2, and tentative results suggest that the carrier density ratio n.sub.e /n.sub.h .about.5 percent, with n.sub.h .about.2.multidot.10.sup.22 cm.sup.-3.
Although the determination of the mfp is relatively straightforward when the material is in the form of a thin layer (since the usual transport properties, including magnetoresistance, can then easily be measured), it is more complicated in a device of the type relevant herein. As is known to those skilled in the art, such determination requires typically measurement of the current gain, and correction for the barrier reflection and excess (hot electron) scattering.
Although other growth techniques, e.g., the method disclosed in U.S. Pat. No. 4,492,971 can produce metal silicide layers of acceptable quality, we have discovered a novel growth technique that can produce very thin, single crystal, silicide layers of very high crystalline quality and good thermal stability. This technique is currently preferred by us for growing devices according to the invention.
The novel techniques comprises deposition of metal and silicon onto a relatively cold silicon substrate. The substrate, which is cleaned and otherwise prepared by methods well known in the art (see, for instance, U.S. patent application Ser. No. 156,649; also, A. Ishizaka et al, Proceedings of the 2nd International Symposium on Molecular Beam Epitaxy, page 183, Tokyo, 1982), is maintained at a relatively low temperature, typically below about 200 degrees C., preferably at or near room temperature, while deposition takes place. The procedure (as well as all other material deposition procedures referred to herein) is advantageously carried out in UHV (e.g., about 10.sup.-9 Torr), and deposition can be by any appropriate method, such as molecular beam or other vapor deposition method, by co-deposition, or by sequential deposition. The fluxes are advantageously adjusted such that the deposit is metal-rich. For instance, we found that a 1:1 Co/Si deposit can yield high quality CoSi.sub.2, and we believe that a deposit of average composition MSi.sub.x, 0.ltoreq.x.ltoreq.2.6, preferably 0.5<x<1.5, can result in metal silicide MSi.sub.2 of good quality.
After deposition of the appropriate quantity of metal and Si, the substrate temperature is typically raised to an intermediate temperature above about 300 degrees C., typically in the range 300-500 degrees C., for a few minutes, typically less than about 30 minutes, and then is further raised to a final temperature, typically in the range 500-700 degrees C., and maintained at the final temperature for a few minutes, typically also less than about 30 minutes. In a typical processing sequence, we have deposited about 35 .ANG. of Co, followed by deposition of about 63 .ANG. of Si, onto a [111]-oriented Si substrate at room temperature. The rate of deposition typically was about 0.5 .ANG./sec for Co, and about 1 .ANG./sec for Si. However, we believe that the deposition rates are not critical process parameters.
Following deposition, the substrates typically are heated to about 400 degrees C. and maintained at that temperature for about 5-10 minutes. Following this intermediate temperature step, the substrates typically are maintained at about 600 degrees C. for about 15 minutes. With this technique, we have routinely produced single crystal CoSi.sub.2 (and NiSi.sub.2) having .chi..chi..sub.min of about 4 percent. Layers produced by this technique were as thin as 50 .ANG., and we know of no reason why even thinner layers of device quality could not be formed. We believe that metal silicides of similar quality could also be formed by pulsed laser melting and liquid phase epitaxial regrowth. See U.S. patent application Ser. No. 506,069, filed June 20, 1983, now U.S. Pat. No. 4,555,301 co-assigned with this. Some variations on the above described method for forming an epitaxial metal silicide layer on a Si substrate are also possible. For instance, we have found that deposition onto a "cold" Si substrate (i.e., <200.degree. C.) of a thin layer of metal (e.g., Co, Ni, or Co.sub.x Ni.sub.1-x, with 0<x<1, preferably 0.5<x<1), or of a thin layer of the metal followed by a thin layer of Si, or Si and Ge, with subsequent heating (typically for a time <30 minutes, e.g., <5 minutes) to a temperature in the range 450.degree. C.-650.degree. C. K, can result in formation of epitaxial metal silicide of high crystalline perfection. Co-deposition of metal and silicon, or Si and Ge, onto a "cold" substrate, followed by ordering at the higher temperature (for a time <30 minutes, typically <5 minutes), is also possible, and is currently preferred by us for forming a thin layer of epitaxial Co.sub.x Ni.sub.1-x Si.sub.2, or CoSi.sub.y Ge.sub.2-y.
We have also discovered a novel technique for growing an epitaxial Si layer on a silicide substrate, typically, the metal silicide layer of a heterostructure according to the invention. The novel technique can solve a problem associated with prior art techniques, namely, the instability of the silicide (e.g., NiSi.sub.2), which tends to diffuse to the surface of the Si layer formed on the silicide. The technique comprises depositing, at a relatively low substrate temperature (typically less than about 300 degrees C., preferably less than 200 degrees C.), a very thin layer of Si onto the substrate. Typically, the layer is between about 10 and 100 .ANG. thick, preferably less than 50 .ANG.. For instance, in some embodiments we have advantageously used layers about 20 .ANG. thick. The deposition rate is not critical; we have used rates between about 0.5 .ANG./sec and about 3 .ANG./sec. After raising the substrate temperature to a temperature between about 500 degrees C. and about 800 degrees C., preferably between about 500 degrees C. and about 700 degrees C., and maintaining it at that temperature for typically less than about 15 minutes, preferably about 5 minutes or less, further Si is deposited until the desired thickness of Si is reached. The deposition rate is not critical; we have used rates between about 3 .ANG./sec and about 10 .ANG./sec. In general, raising the temperature of the substrate to a temperature above 400.degree. C. transforms the thin layer of Si (the template layer) into epitaxial crystalline material.
By way of example, we have deposited a 20 .ANG. layer of Si onto an approximately 100 .ANG. thick layer of [111]-oriented CoSi.sub.2, the substrate being at about 80 degrees C., then raised the substrate temperature to about 700 degrees C. After 2 minutes at that temperature, we deposited about 0.5 .mu.m of Si onto the previously deposited Si, while maintaining the substrate temperature substantially constant. The Si was deposited from an evaporation source at a rate of about 5 .ANG./sec.
Some variations on the above described method for forming an epitaxial Si layer on a metal silicide substrate are also possible. For instance, we have found that deposition of the thin Si template layer onto a "cold" (<200.degree. C.) NiSi.sub.2 layer, followed by a brief (typically <5 minutes) pause, e.g., for measurement purposes, at an intermediate temperature (450.degree.-500.degree. C.), which in turn was followed by vapor deposition of the remainder of the Si at a higher substrate temperature (500.degree.-600.degree. C.), resulted in formation of an epitaxial layer of Si of excellent crystal quality, without significant out-diffusion of metal from the nickel silicide layer. Similar intermediate temperature pauses, or even more complicated time/temperature programs, may be possible in general in the formation of Si/silicide/Si heteroepitaxial structures.
The same processes can, of course, be adapted to the deposition of doped Si, for instance, the co-evaporation of dopant and Si. Silicon layers formed by the above processes can also be doped by ion implantation, followed by an anneal. These and other doping techniques are known to those skilled in the art and require no elaboration. Furthermore, it will be appreciated by those skilled in the art that the methods disclosed herein can be used to fabricate metal/semiconductor superlattices, i.e., heterostructures comprising a plurality (two or more) of silicide layers separated by semiconductor layers. Devices comprising metal/semiconductor superlattices can be expected to have novel electrical and/or optical properties not attainable with conventional semiconductor superlattices, and are contemplated by us. For instance, such devices may comprise strained layer superlattices in which at least the layers of one type (e.g., the silicide layer) are so thin (e.g., <100 .ANG.) that their lattice constant is essentially equal to that of their substrate and overlayer.
Example I
A [111]-oriented wafer of n-type silicon (resistivity about 0.2 .OMEGA. cm) was cleaned and otherwise prepared substantially as described in A. Ishizaka et al, op. cit. On this wafer was grown an about 184 .ANG. thick layer of CoSi.sub.2. With the substrate being at room temperature, we deposited a 51 .ANG. thick layer of Co, followed by deposition of a 65 .ANG. thick layer of Si. The temperature was raised to about 400 degrees C., the wafer maintained at that temperature for about 10 minutes, then the temperature was raised to about 600 degrees C. and the wafer maintained at that temperature for about 15 minutes. After cooling of the wafer to about 80 degrees C., and without breaking of the vacuum, we deposited a 20 .ANG. thick layer of Si onto the CoSi.sub.2 layer. After raising the temperature of the wafer to about 700 degrees C. and maintaining it at that temperature for about 2 minutes, we deposited about 0.5 .mu.m of Si onto the previously deposited Si layer. Into the thus formed Si layer we implanted P ions (155 KeV) such as to obtain n-type material (3.10.sup.15 cm.sup.-3) at the Si/CoSi.sub.2 interface. The near-surface region of the Si layer was heavily implanted with P, such that a layer of degenerate silicon was formed. The composite structure was annealed at 800 degrees C. for about 30 minutes in vacuum to remove implantation damage. Collector contacts were formed by depositing Sb onto the back surface of the wafer, and laser melting and recrystallizing appropriately located Sb-covered surface regions. This resulted in formation of degenerate contact regions.
We formed mesa structures on the top surface of the wafer by standard lithography and plasma etching techniques. The mesas were basically circular, for provision for contacting the base with the Si substrate and the CoSi thereon (collector and base, respectively) having about 300 .mu.m diameters, and the top Si layer (emitter) a diameter of about 200 .mu.m. Electrical measurements were made on the mesa-type transistors by a conventional method. For instance, we measured a transistor in a common base configuration. We obtained a family of curves representing the collector I/V characteristics, with each curve representing a different emitter injection current, the base/collector junction being reverse biased. The collector current was found to be substantially independent of collector voltage for a collector voltage between about 1 and 3 volts. The measurements indicate that two back-to-back Schottky barriers were formed. The measurements also indicate that the DC common base current gain of the structure is greater than 0.5.
Example Ii
A Si(111) substrate was prepared substantially as in Example I, followed by deposition thereon, by e-gun evaporation (at about 1 .ANG./sec), of about 18 .ANG. of Ni, with the substrate at room temperature. Raising the substrate temperature to about 500.degree. C. and maintaining it at that temperature for about 1 minute resulted in formation of a 65 .ANG. thick layer of NiSi.sub.2 (111) of type A orientation. After lowering of the substrate temperature to room temperature, a 20 .ANG. thick layer of Si was deposited (at 1 .ANG./sec) by e-gun evaporation, and the temperature raised, with a 1 minute pause at about 450.degree. C. to obtain a LEED pattern. Subsequently the substrate temperature was raised to about 540.degree. C. and 2000 .ANG. of Si deposited at a rate of 2 .ANG./sec, followed by cooling of the sample to room temperature. All of the processing subsequent to formation of the oxide layer on the Si substrate was carried out in UHV, with the pressure always <5.10.sup.-8 Pa. The thus produced Si layer on NiSi.sub.2 had .chi..sub.min .about.3%, with the interface being smooth and impurity free.
Example Iii
A Si/Co.sub.x Ni.sub.1-x Si.sub.2 /Si heteroepitaxial structure is formed by a method substantially as described in Example II, except as noted below. A 90 .ANG. thick layer of Co.sub.0.75 Ni.sub.0.25 Si.sub.2 is formed by co-deposition (at 1 .ANG./sec) from separate e-gun evaporators, of Ni, Co, and Si. The fluxes are adjusted to result in a substantially stoichiometric deposit. After completion of deposition, the substrate temperature is raised to 600.degree. C. for 1 minute. The layer of Si atop the silicide layer is grown as described in Example II, except that, after room temperature deposition of 30 .ANG. of Si, the temperature is raised to 560.degree. C. and 3000 .ANG. of Si are deposited. The thus formed Si layer has .chi..sub.min <5%, with the interface being smooth and impurity free.
Example Iv
A Si/CoSi.sub.2 /Si heteroepitaxial structure was formed by a method substantially as described in Example II, except as noted below. A 30 .ANG. thick layer of Co was deposited onto a Si(111) substrate at room temperature, the temperature raised to 550.degree. C. for about 3 minutes, resulting in formation of a 110 .ANG. thick layer of CoSi.sub.2.30 .ANG. of Si were deposited (at 1 .ANG./sec) at room temperature onto the CoSi.sub.2 layer, the temperature raised to 600.degree. C. for about 1 minute, followed by deposition of 1500 .ANG. of Si, at a rate of 2 .ANG./sec, at about 640.degree. C. The resulting Si layer had .chi..sub.min .about.4%, with the interface being smooth and impurity free.
Example V
A Si/CoSi.sub.y Ge.sub.2-y /Si heteroepitaxial structure is formed by a method substantially as described in Example III, except that the 90 .ANG. thick layer of CoSi.sub.1.8 Ge.sub.0.2 is formed by co-deposition (1 .ANG./sec), from separate e-gun evaporators, of Co, Si, and Ge.
Claims
What is claimed is:
1. Method of forming a metal silicide/silicon heterostructure comprising a layer of silicon grown on a single crystal metal silicide substrate, the Si layer having a thickness t, the method comprising: (a) depositing a first layer of silicon onto the silicide substrate, the first layer thickness t.sub.1 being less than t, the substrate being at a template deposition temperature below about 300.degree. C.; (b) raising the temperature of the substrate with the first layer of silicon thereon to a bulk deposition temperature between about 500 degrees C. and about 800 degrees C.; and (c) depositing silicon onto the first silicon layer, the substrate being maintained substantially at the bulk deposition temperature, the amount of silicon deposited being the amount required to result in a Si layer of thickness t.
2. Method of claim 1, wherein the metal silicide is selected from the group consisting of CoSi.sub.2, Co.sub.x Ni.sub.1-x Si.sub.2, with 0<x<1, CoSi.sub.y Ge.sub.2-y, with 1<y<2, and NiSi.sub.2, the template deposition temperature is less than about 200 degrees C., and the bulk deposition temperature is between about 500 degrees C. and about 700 degrees C.
3. Method of claim 1, wherein t.sub.1 <100 .ANG..
4. Method of claim 3, wherein the metal silicide is selected from the group consisting of CoSi.sub.2, NiSi.sub.2 Co.sub.x.sub.Ni.sub.1-x Si.sub.2, x.gtoreq.0.5, and CoSi.sub.y Ge.sub.2-y, y.gtoreq.1.5.
5. Method of claim 1, wherein step (b) comprises maintaining the substrate at an intermediate temperature between the template deposition temperature and the bulk deposition temperature.
6. Method of claim 1, wherein the metal silicide/silicon heterostructure is at least part of an electronic device.
7. Method of claim 1, wherein the metal silicide/silicon heterostructure is at least part of a composite heteroepitaxial structure of alternating layers of silicon and metal silicide.
8. Method of claim 7, wherein the composite heteroepitaxial structure is at least part of an electronic device or of an optical device.
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